Coverage Report for TRA

Table of Contents

  1. Analysis Information
  2. Tests
  3. Summary
  4. Details

Analysis Information

Model Information

  Model version   'M112C123'
  Author   xigkd
  Last saved   Tue Sep 07 12:59:53 2021

Harness information

  Harness model(s)   TRA_Harness1
  Harness model owner   TRA

Simulation Optimization Options

  Default parameter behavior   inlined
  Block reduction   forced off
  Conditional branch optimization   on

Coverage Options

  Analyzed model   TRA
  Logic block short circuiting   off
  MCDC mode   masking

Blocks Eliminated from Coverage Analysis

# Model Object Rationale
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/Abs Simulink optimization for unsigned value
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero/FaultProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero1/FaultProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempDiffDiag/DebounceStartZero1/FaultProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero/FaultProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero/HealProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/FaultProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/FaultProcess/Increase/Saturation It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/HealProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/HealProcess/Decrease/Switch It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/HealProcess/Switch It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/FaultProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/FaultProcess/Increase/Saturation It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/HealProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/HealProcess/Decrease/Switch It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/HealProcess/Switch It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/FaultProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/FaultProcess/Increase/Saturation It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/HealProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/HealProcess/Decrease/Switch It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/HealProcess/Switch It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/FaultProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/FaultProcess/Increase/Saturation It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/HealProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/HealProcess/Decrease/Switch It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/HealProcess/Switch It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/FaultProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/FaultProcess/Increase/Saturation It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/HealProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/HealProcess/Decrease/Switch It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/HealProcess/Switch It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/FaultProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/FaultProcess/Increase/Saturation It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/HealProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/HealProcess/Decrease/Switch It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/HealProcess/Switch It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/FaultProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/FaultProcess/Increase/Saturation It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/HealProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/HealProcess/Decrease/Switch It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/HealProcess/Switch It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/FaultProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/FaultProcess/Increase/Saturation It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/HealProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/HealProcess/Decrease/Switch It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/HealProcess/Switch It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/FaultProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/FaultProcess/Decrease/Switch It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/HealProcess/Decrease/Relational Operator It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/HealProcess/Increase/Saturation It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ArbShortSOCIDFit/Logical It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ArbShortSOCIDFit/Relational Operator3 It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ArbShortSOCIDFit/Switch2 It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcShortMinSOCID/Switch1 It might not be executed because of Conditional input branch optimization
 TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcShortSOCDiff/Switch1 It might not be executed because of Conditional input branch optimization

Tests

Test# Started execution Ended execution
Test 1 08-Sep-2021 14:19:25 08-Sep-2021 14:21:21

Summary

Model Hierarchy/Complexity Test 1  
Decision Condition MCDC Execution  
1. TRA 2948 60%
   
61%
   
10%
   
86%
   
 
2. . . . TRA 2943 60%
   
61%
   
10%
   
86%
   
 
3. . . . . . . ThemRunAway_10ms 2943 60%
   
61%
   
10%
   
86%
   
 
4. . . . . . . . . . ThemRunAway_10ms_sys 2942 60%
   
61%
   
10%
   
86%
   
 
5. . . . . . . . . . . . . RunawayFinishChk 7 60%
   
50%
   
0%
   
100%
   
 
6. . . . . . . . . . . . . . . . BMSDelay 4 67%
   
50%
   
NA 100%
   
 
7. . . . . . . . . . . . . . . . . . . Unit Delay Resettable 2 75%
   
NA NA 100%
   
 
8. . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg1 2 50%
   
NA NA 100%
   
 
9. . . . . . . . . . . . . RunawayStateDet 5 63%
   
NA NA 100%
   
 
10. . . . . . . . . . . . . . . . LDP_GeLDP_CC2St_enum 2 50%
   
NA NA 100%
   
 
11. . . . . . . . . . . . . RunawayTempCheck 2797 61%
   
61%
   
5%
   
90%
   
 
12. . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg 2 50%
   
NA NA 100%
   
 
13. . . . . . . . . . . . . . . . RunawayBusbarTempCheck 1338 63%
   
66%
   
27%
   
98%
   
 
14. . . . . . . . . . . . . . . . . . . BMSDelay2 4 100%
   
100%
   
NA 100%
   
 
15. . . . . . . . . . . . . . . . . . . . . . Unit Delay Resettable 2 100%
   
NA NA 100%
   
 
16. . . . . . . . . . . . . . . . . . . BusbarMaxTempDiag 28 75%
   
88%
   
50%
   
97%
   
 
17. . . . . . . . . . . . . . . . . . . . . . DebounceStartZero 14 77%
   
92%
   
NA 97%
   
 
18. . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 100%
   
NA 100%
   
 
19. . . . . . . . . . . . . . . . . . . . . . . . . FaultProcess 6 75%
   
75%
   
NA 93%
   
 
20. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 50%
   
50%
   
NA 75%
   
 
21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
22. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 50%
   
NA NA 100%
   
 
23. . . . . . . . . . . . . . . . . . . . . . . . . HealProcess 6 75%
   
100%
   
NA 100%
   
 
24. . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 100%
   
NA 100%
   
 
25. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 100%
   
100%
   
NA 100%
   
 
26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 100%
   
 
27. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 50%
   
NA NA 100%
   
 
28. . . . . . . . . . . . . . . . . . . . . . DebounceStartZero1 14 73%
   
83%
   
NA 97%
   
 
29. . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 100%
   
NA 100%
   
 
30. . . . . . . . . . . . . . . . . . . . . . . . . FaultProcess 6 75%
   
75%
   
NA 93%
   
 
31. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 50%
   
50%
   
NA 75%
   
 
32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
33. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 50%
   
NA NA 100%
   
 
34. . . . . . . . . . . . . . . . . . . . . . . . . HealProcess 6 67%
   
83%
   
NA 100%
   
 
35. . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 100%
   
NA 100%
   
 
36. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 100%
   
100%
   
NA 100%
   
 
37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 100%
   
 
38. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 50%
   
NA NA 100%
   
 
39. . . . . . . . . . . . . . . . . . . BusbarTempDiffDiag 14 77%
   
93%
   
NA 97%
   
 
40. . . . . . . . . . . . . . . . . . . . . . DebounceStartZero1 14 77%
   
92%
   
NA 97%
   
 
41. . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 100%
   
NA 100%
   
 
42. . . . . . . . . . . . . . . . . . . . . . . . . FaultProcess 6 75%
   
75%
   
NA 93%
   
 
43. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 50%
   
50%
   
NA 75%
   
 
44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
45. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 50%
   
NA NA 100%
   
 
46. . . . . . . . . . . . . . . . . . . . . . . . . HealProcess 6 75%
   
100%
   
NA 100%
   
 
47. . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 100%
   
NA 100%
   
 
48. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 100%
   
100%
   
NA 100%
   
 
49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 100%
   
 
50. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 50%
   
NA NA 100%
   
 
51. . . . . . . . . . . . . . . . . . . BusbarTempGradDiag 1292 62%
   
65%
   
23%
   
98%
   
 
52. . . . . . . . . . . . . . . . . . . . . . BMSDelay 4 83%
   
75%
   
NA 100%
   
 
53. . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay Resettable 2 75%
   
NA NA 100%
   
 
54. . . . . . . . . . . . . . . . . . . . . . BusbarTempGradDiag 1276 62%
   
65%
   
23%
   
98%
   
 
55. . . . . . . . . . . . . . . . . . . . . . . . . Counter Reset Enabled 3 50%
   
NA NA 83%
   
 
56. . . . . . . . . . . . . . . . . . . . . . . . . Counter Reset Enabled 1 3 75%
   
NA NA 100%
   
 
57. . . . . . . . . . . . . . . . . . . . . . . . . DebounceStartZero 14 73%
   
83%
   
NA 94%
   
 
58. . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 100%
   
NA 100%
   
 
59. . . . . . . . . . . . . . . . . . . . . . . . . . . . FaultProcess 6 75%
   
75%
   
NA 93%
   
 
60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 50%
   
50%
   
NA 75%
   
 
61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 50%
   
NA NA 100%
   
 
63. . . . . . . . . . . . . . . . . . . . . . . . . . . . HealProcess 6 67%
   
83%
   
NA 93%
   
 
64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 100%
   
NA 100%
   
 
65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 50%
   
50%
   
NA 75%
   
 
66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 50%
   
NA NA 100%
   
 
68. . . . . . . . . . . . . . . . . . . . . . . . . DebounceStartZero1 625 62%
   
67%
   
NA 100%
   
 
69. . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 51%
   
NA 100%
   
 
70. . . . . . . . . . . . . . . . . . . . . . . . . . . . FaultProcess 288 51%
   
51%
   
NA 100%
   
 
71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 48 51%
   
51%
   
NA 100%
   
 
72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 100%
   
 
73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 96 50%
   
NA NA 100%
   
 
74. . . . . . . . . . . . . . . . . . . . . . . . . . . . HealProcess 288 75%
   
84%
   
NA 100%
   
 
75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 51%
   
NA 100%
   
 
76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 48 100%
   
100%
   
NA 100%
   
 
77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 100%
   
 
78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 96 50%
   
NA NA 100%
   
 
79. . . . . . . . . . . . . . . . . . . . . . . . . DebounceStartZero2 625 62%
   
67%
   
NA 100%
   
 
80. . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
81. . . . . . . . . . . . . . . . . . . . . . . . . . . . FaultProcess 288 50%
   
51%
   
NA 100%
   
 
82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 48 51%
   
51%
   
NA 100%
   
 
83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 100%
   
 
84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 96 50%
   
NA NA 100%
   
 
85. . . . . . . . . . . . . . . . . . . . . . . . . . . . HealProcess 288 75%
   
84%
   
NA 100%
   
 
86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 51%
   
NA 100%
   
 
87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 48 100%
   
100%
   
NA 100%
   
 
88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 100%
   
 
89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 96 50%
   
NA NA 100%
   
 
90. . . . . . . . . . . . . . . . . . . . . . . . . EdgeRising 1 NA 50%
   
0%
   
100%
   
 
91. . . . . . . . . . . . . . . . . . . . . . . . . EdgeRising2 1 NA 50%
   
0%
   
100%
   
 
92. . . . . . . . . . . . . . . . . . . . . . . . . MaxBusbarTempGrad_ForIterator1 1 100%
   
NA NA 100%
   
 
93. . . . . . . . . . . . . . . . . . . . . . . . . MaxBusbarTempGrad_ForIterator2 1 100%
   
NA NA 100%
   
 
94. . . . . . . . . . . . . . . . . . . . . . CalcBusbarTempGrad 10 100%
   
NA NA 100%
   
 
95. . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC 2 100%
   
NA NA 100%
   
 
96. . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC1 2 100%
   
NA NA 100%
   
 
97. . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC2 2 100%
   
NA NA 100%
   
 
98. . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC3 2 100%
   
NA NA 100%
   
 
99. . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC4 2 100%
   
NA NA 100%
   
 
100. . . . . . . . . . . . . . . . RunawayCellTempCheck 1374 60%
   
63%
   
0%
   
84%
   
 
101. . . . . . . . . . . . . . . . . . . BMSDelay1 4 100%
   
100%
   
NA 100%
   
 
102. . . . . . . . . . . . . . . . . . . . . . Unit Delay Resettable 2 100%
   
NA NA 100%
   
 
103. . . . . . . . . . . . . . . . . . . CellMaxTempDiag 42 38%
   
50%
   
0%
   
82%
   
 
104. . . . . . . . . . . . . . . . . . . . . . DebounceStartZero 14 38%
   
50%
   
NA 78%
   
 
105. . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
106. . . . . . . . . . . . . . . . . . . . . . . . . FaultProcess 6 33%
   
50%
   
NA 79%
   
 
107. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 50%
   
50%
   
NA 75%
   
 
108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
109. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 0%
   
NA NA 0%
   
 
110. . . . . . . . . . . . . . . . . . . . . . . . . HealProcess 6 42%
   
50%
   
NA 73%
   
 
111. . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
112. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 0%
   
0%
   
NA 25%
   
 
113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
114. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 50%
   
NA NA 100%
   
 
115. . . . . . . . . . . . . . . . . . . . . . DebounceStartZero1 14 38%
   
50%
   
NA 78%
   
 
116. . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
117. . . . . . . . . . . . . . . . . . . . . . . . . FaultProcess 6 33%
   
50%
   
NA 79%
   
 
118. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 50%
   
50%
   
NA 75%
   
 
119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
120. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 0%
   
NA NA 0%
   
 
121. . . . . . . . . . . . . . . . . . . . . . . . . HealProcess 6 42%
   
50%
   
NA 73%
   
 
122. . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
123. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 0%
   
0%
   
NA 25%
   
 
124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
125. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 50%
   
NA NA 100%
   
 
126. . . . . . . . . . . . . . . . . . . . . . DebounceStartZero2 14 38%
   
50%
   
NA 78%
   
 
127. . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
128. . . . . . . . . . . . . . . . . . . . . . . . . FaultProcess 6 33%
   
50%
   
NA 79%
   
 
129. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 50%
   
50%
   
NA 75%
   
 
130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
131. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 0%
   
NA NA 0%
   
 
132. . . . . . . . . . . . . . . . . . . . . . . . . HealProcess 6 42%
   
50%
   
NA 73%
   
 
133. . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
134. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 0%
   
0%
   
NA 25%
   
 
135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
136. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 50%
   
NA NA 100%
   
 
137. . . . . . . . . . . . . . . . . . . CellTempDiffDiag 14 38%
   
50%
   
NA 82%
   
 
138. . . . . . . . . . . . . . . . . . . . . . DebounceStartZero1 14 38%
   
50%
   
NA 78%
   
 
139. . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
140. . . . . . . . . . . . . . . . . . . . . . . . . FaultProcess 6 33%
   
50%
   
NA 79%
   
 
141. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 50%
   
50%
   
NA 75%
   
 
142. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
143. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 0%
   
NA NA 0%
   
 
144. . . . . . . . . . . . . . . . . . . . . . . . . HealProcess 6 42%
   
50%
   
NA 73%
   
 
145. . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
146. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 0%
   
0%
   
NA 25%
   
 
147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
148. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 50%
   
NA NA 100%
   
 
149. . . . . . . . . . . . . . . . . . . CellTempGradDiag 1292 62%
   
64%
   
0%
   
95%
   
 
150. . . . . . . . . . . . . . . . . . . . . . BMSDelay 4 83%
   
75%
   
NA 100%
   
 
151. . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay Resettable 2 75%
   
NA NA 100%
   
 
152. . . . . . . . . . . . . . . . . . . . . . CalcTempGrad 10 100%
   
NA NA 100%
   
 
153. . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC 2 100%
   
NA NA 100%
   
 
154. . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC1 2 100%
   
NA NA 100%
   
 
155. . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC2 2 100%
   
NA NA 100%
   
 
156. . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC3 2 100%
   
NA NA 100%
   
 
157. . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC4 2 100%
   
NA NA 100%
   
 
158. . . . . . . . . . . . . . . . . . . . . . CellTempGradDiag 1276 61%
   
64%
   
0%
   
94%
   
 
159. . . . . . . . . . . . . . . . . . . . . . . . . Counter Reset Enabled 3 50%
   
NA NA 83%
   
 
160. . . . . . . . . . . . . . . . . . . . . . . . . Counter Reset Enabled 1 3 50%
   
NA NA 83%
   
 
161. . . . . . . . . . . . . . . . . . . . . . . . . DebounceStartZero 14 38%
   
50%
   
NA 78%
   
 
162. . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
163. . . . . . . . . . . . . . . . . . . . . . . . . . . . FaultProcess 6 33%
   
50%
   
NA 79%
   
 
164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 50%
   
50%
   
NA 75%
   
 
165. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
166. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 0%
   
NA NA 0%
   
 
167. . . . . . . . . . . . . . . . . . . . . . . . . . . . HealProcess 6 42%
   
50%
   
NA 73%
   
 
168. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 0%
   
0%
   
NA 25%
   
 
170. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
171. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 50%
   
NA NA 100%
   
 
172. . . . . . . . . . . . . . . . . . . . . . . . . DebounceStartZero1 625 62%
   
67%
   
NA 100%
   
 
173. . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
174. . . . . . . . . . . . . . . . . . . . . . . . . . . . FaultProcess 288 50%
   
50%
   
NA 100%
   
 
175. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 48 50%
   
50%
   
NA 100%
   
 
176. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 100%
   
 
177. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 96 50%
   
NA NA 100%
   
 
178. . . . . . . . . . . . . . . . . . . . . . . . . . . . HealProcess 288 75%
   
83%
   
NA 100%
   
 
179. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
180. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 48 100%
   
100%
   
NA 100%
   
 
181. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 100%
   
 
182. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 96 50%
   
NA NA 100%
   
 
183. . . . . . . . . . . . . . . . . . . . . . . . . DebounceStartZero2 625 62%
   
67%
   
NA 100%
   
 
184. . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
185. . . . . . . . . . . . . . . . . . . . . . . . . . . . FaultProcess 288 50%
   
50%
   
NA 100%
   
 
186. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 48 50%
   
50%
   
NA 100%
   
 
187. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 100%
   
 
188. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 96 50%
   
NA NA 100%
   
 
189. . . . . . . . . . . . . . . . . . . . . . . . . . . . HealProcess 288 75%
   
83%
   
NA 100%
   
 
190. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
191. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 48 100%
   
100%
   
NA 100%
   
 
192. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 100%
   
 
193. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 96 50%
   
NA NA 100%
   
 
194. . . . . . . . . . . . . . . . . . . . . . . . . EdgeRising 1 NA 50%
   
0%
   
100%
   
 
195. . . . . . . . . . . . . . . . . . . . . . . . . EdgeRising2 1 NA 50%
   
0%
   
100%
   
 
196. . . . . . . . . . . . . . . . . . . . . . . . . MaxCellTempGrad_ForIterator1 1 100%
   
NA NA 100%
   
 
197. . . . . . . . . . . . . . . . . . . . . . . . . MaxCellTempGrad_ForIterator2 1 100%
   
NA NA 100%
   
 
198. . . . . . . . . . . . . . . . . . . EdgeRising 1 NA 50%
   
0%
   
100%
   
 
199. . . . . . . . . . . . . . . . . . . EdgeRising1 1 NA 50%
   
0%
   
100%
   
 
200. . . . . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg1 2 50%
   
NA NA 100%
   
 
201. . . . . . . . . . . . . . . . . . . MaxTempDiag1 9 8%
   
0%
   
NA 8%
   
 
202. . . . . . . . . . . . . . . . . . . . . . MinCellTemp_ForIterator 7 0%
   
0%
   
NA 8%
   
 
203. . . . . . . . . . . . . . . . . . . . . . . . . MaxCellTemp_ForIterator 6 0%
   
0%
   
NA 9%
   
 
204. . . . . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC 2 0%
   
NA NA 0%
   
 
205. . . . . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC2 2 0%
   
NA NA 0%
   
 
206. . . . . . . . . . . . . . . . . . . TempGradCalc 9 8%
   
0%
   
NA 8%
   
 
207. . . . . . . . . . . . . . . . . . . . . . MaxCellTempGrad_ForIterator 7 0%
   
0%
   
NA 8%
   
 
208. . . . . . . . . . . . . . . . . . . . . . . . . MaxCellTemp_ForIterator 6 0%
   
0%
   
NA 9%
   
 
209. . . . . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC 2 0%
   
NA NA 0%
   
 
210. . . . . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC2 2 0%
   
NA NA 0%
   
 
211. . . . . . . . . . . . . . . . RunawayVoltTempCheck 83 48%
   
51%
   
0%
   
89%
   
 
212. . . . . . . . . . . . . . . . . . . RunawayVoltCheck 36 43%
   
50%
   
0%
   
87%
   
 
213. . . . . . . . . . . . . . . . . . . . . . Counter Reset Enabled 3 50%
   
NA NA 83%
   
 
214. . . . . . . . . . . . . . . . . . . . . . DebounceStartZero1 14 38%
   
50%
   
NA 78%
   
 
215. . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
216. . . . . . . . . . . . . . . . . . . . . . . . . FaultProcess 6 33%
   
50%
   
NA 79%
   
 
217. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 50%
   
50%
   
NA 75%
   
 
218. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
219. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 0%
   
NA NA 0%
   
 
220. . . . . . . . . . . . . . . . . . . . . . . . . HealProcess 6 42%
   
50%
   
NA 73%
   
 
221. . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
222. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 0%
   
0%
   
NA 25%
   
 
223. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
224. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 50%
   
NA NA 100%
   
 
225. . . . . . . . . . . . . . . . . . . . . . DebounceStartZero2 14 38%
   
50%
   
NA 78%
   
 
226. . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
227. . . . . . . . . . . . . . . . . . . . . . . . . FaultProcess 6 33%
   
50%
   
NA 79%
   
 
228. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 50%
   
50%
   
NA 75%
   
 
229. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
230. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 0%
   
NA NA 0%
   
 
231. . . . . . . . . . . . . . . . . . . . . . . . . HealProcess 6 42%
   
50%
   
NA 73%
   
 
232. . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
233. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 0%
   
0%
   
NA 25%
   
 
234. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
235. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 50%
   
NA NA 100%
   
 
236. . . . . . . . . . . . . . . . . . . . . . EdgeRising 1 NA 50%
   
0%
   
100%
   
 
237. . . . . . . . . . . . . . . . . . . . . . EdgeRising1 1 NA 50%
   
0%
   
100%
   
 
238. . . . . . . . . . . . . . . . . . . . . . EdgeRising2 1 NA 50%
   
0%
   
100%
   
 
239. . . . . . . . . . . . . . . . . . . . . . MaxCellVolt_ForIterator 1 100%
   
NA NA 100%
   
 
240. . . . . . . . . . . . . . . . . . . . . . MinCellVolt_ForIterator 1 100%
   
NA NA 100%
   
 
241. . . . . . . . . . . . . . . . . . . RunawayVoltGradCheck 43 53%
   
50%
   
0%
   
89%
   
 
242. . . . . . . . . . . . . . . . . . . . . . CellVoltGrad_ForIterator 1 100%
   
NA NA 100%
   
 
243. . . . . . . . . . . . . . . . . . . . . . CellVoltGrad_ForIterator1 1 100%
   
NA NA 100%
   
 
244. . . . . . . . . . . . . . . . . . . . . . Counter Reset Enabled 3 50%
   
NA NA 83%
   
 
245. . . . . . . . . . . . . . . . . . . . . . DebounceStartZero1 14 38%
   
50%
   
NA 78%
   
 
246. . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
247. . . . . . . . . . . . . . . . . . . . . . . . . FaultProcess 6 33%
   
50%
   
NA 79%
   
 
248. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 50%
   
50%
   
NA 75%
   
 
249. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
250. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 0%
   
NA NA 0%
   
 
251. . . . . . . . . . . . . . . . . . . . . . . . . HealProcess 6 42%
   
50%
   
NA 73%
   
 
252. . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
253. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 0%
   
0%
   
NA 25%
   
 
254. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
255. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 50%
   
NA NA 100%
   
 
256. . . . . . . . . . . . . . . . . . . . . . DebounceStartZero2 14 50%
   
58%
   
NA 81%
   
 
257. . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 100%
   
NA 100%
   
 
258. . . . . . . . . . . . . . . . . . . . . . . . . FaultProcess 6 58%
   
50%
   
NA 79%
   
 
259. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 0%
   
0%
   
NA 25%
   
 
260. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
261. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 50%
   
NA NA 100%
   
 
262. . . . . . . . . . . . . . . . . . . . . . . . . HealProcess 6 33%
   
50%
   
NA 80%
   
 
263. . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare To Zero   NA 50%
   
NA 100%
   
 
264. . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrease 1 50%
   
50%
   
NA 75%
   
 
265. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nomal   NA NA NA 0%
   
 
266. . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase 2 0%
   
NA NA 0%
   
 
267. . . . . . . . . . . . . . . . . . . . . . EdgeRising 1 NA 50%
   
0%
   
100%
   
 
268. . . . . . . . . . . . . . . . . . . . . . EdgeRising1 1 NA 50%
   
0%
   
100%
   
 
269. . . . . . . . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg 2 50%
   
NA NA 100%
   
 
270. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC2 2 100%
   
NA NA 100%
   
 
271. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC3 2 100%
   
NA NA 100%
   
 
272. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC4 2 100%
   
NA NA 100%
   
 
273. . . . . . . . . . . . . . . . . . . RunawayVoltTempCheck 4 50%
   
60%
   
0%
   
100%
   
 
274. . . . . . . . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg 2 50%
   
NA NA 100%
   
 
275. . . . . . . . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg1 2 50%
   
NA NA 100%
   
 
276. . . . . . . . . . . . . RunawayWarnAlarmCheck 128 32%
   
59%
   
17%
   
72%
   
 
277. . . . . . . . . . . . . . . . ArbRunawayWarnAlarm 4 50%
   
57%
   
14%
   
100%
   
 
278. . . . . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg 2 50%
   
NA NA 100%
   
 
279. . . . . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg1 2 50%
   
NA NA 100%
   
 
280. . . . . . . . . . . . . . . . BMSDelay 4 83%
   
75%
   
NA 100%
   
 
281. . . . . . . . . . . . . . . . . . . Unit Delay Resettable 2 75%
   
NA NA 100%
   
 
282. . . . . . . . . . . . . . . . CalcSOCPreCond 8 88%
   
76%
   
44%
   
100%
   
 
283. . . . . . . . . . . . . . . . . . . Turn Off Delay Time 4 75%
   
75%
   
50%
   
100%
   
 
284. . . . . . . . . . . . . . . . . . . . . . EdgeFalling1 1 NA 67%
   
50%
   
100%
   
 
285. . . . . . . . . . . . . . . . . . . Turn On Delay Time 4 100%
   
78%
   
50%
   
100%
   
 
286. . . . . . . . . . . . . . . . . . . . . . EdgeRising 1 NA 83%
   
50%
   
100%
   
 
287. . . . . . . . . . . . . . . . EdgeRising 1 NA 50%
   
0%
   
100%
   
 
288. . . . . . . . . . . . . . . . LongThmRnwyDet 36 8%
   
50%
   
0%
   
33%
   
 
289. . . . . . . . . . . . . . . . . . . EdgeRising1 1 NA 50%
   
0%
   
100%
   
 
290. . . . . . . . . . . . . . . . . . . LongThmRnwyWarnAlrmDet 4 50%
   
50%
   
NA 100%
   
 
291. . . . . . . . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg1 2 50%
   
NA NA 100%
   
 
292. . . . . . . . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg2 2 50%
   
NA NA 100%
   
 
293. . . . . . . . . . . . . . . . . . . OCVSOC_Calc 31 3%
   
0%
   
NA 5%
   
 
294. . . . . . . . . . . . . . . . . . . . . . 2D_Config_Word1 11 0%
   
NA NA 0%
   
 
295. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem   NA NA NA 0%
   
 
296. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem1   NA NA NA 0%
   
 
297. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem2   NA NA NA 0%
   
 
298. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem3   NA NA NA 0%
   
 
299. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem4   NA NA NA 0%
   
 
300. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem5   NA NA NA 0%
   
 
301. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem6   NA NA NA 0%
   
 
302. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem7   NA NA NA 0%
   
 
303. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem8   NA NA NA 0%
   
 
304. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem9   NA NA NA 0%
   
 
305. . . . . . . . . . . . . . . . . . . . . . 2D_Config_Word2 11 0%
   
NA NA 0%
   
 
306. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem   NA NA NA 0%
   
 
307. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem1   NA NA NA 0%
   
 
308. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem2   NA NA NA 0%
   
 
309. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem3   NA NA NA 0%
   
 
310. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem4   NA NA NA 0%
   
 
311. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem5   NA NA NA 0%
   
 
312. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem6   NA NA NA 0%
   
 
313. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem7   NA NA NA 0%
   
 
314. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem8   NA NA NA 0%
   
 
315. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem9   NA NA NA 0%
   
 
316. . . . . . . . . . . . . . . . . . . . . . MinOCVSOC_ForIterator 7 0%
   
0%
   
NA 8%
   
 
317. . . . . . . . . . . . . . . . . . . . . . . . . MinCellOCVSOCNumb_ForIterator 6 0%
   
0%
   
NA 9%
   
 
318. . . . . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC1 2 0%
   
NA NA 0%
   
 
319. . . . . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC2 2 0%
   
NA NA 0%
   
 
320. . . . . . . . . . . . . . . . MaxTempThmRnwyDet 13 67%
   
65%
   
25%
   
100%
   
 
321. . . . . . . . . . . . . . . . . . . BusbarTempDet 6 88%
   
83%
   
50%
   
100%
   
 
322. . . . . . . . . . . . . . . . . . . . . . BMSDelay 4 100%
   
100%
   
NA 100%
   
 
323. . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay Resettable 2 100%
   
NA NA 100%
   
 
324. . . . . . . . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg 2 50%
   
NA NA 100%
   
 
325. . . . . . . . . . . . . . . . . . . CellTempDet 7 50%
   
50%
   
0%
   
100%
   
 
326. . . . . . . . . . . . . . . . . . . . . . BMSDelay 4 50%
   
50%
   
NA 100%
   
 
327. . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay Resettable 2 50%
   
NA NA 100%
   
 
328. . . . . . . . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg 2 50%
   
NA NA 100%
   
 
329. . . . . . . . . . . . . . . . ReadNVMInitData 2 50%
   
NA NA 0%
   
 
330. . . . . . . . . . . . . . . . ShortThmRnwyDet 58 23%
   
48%
   
0%
   
70%
   
 
331. . . . . . . . . . . . . . . . . . . ArbShortSOCIDFit 5 38%
   
45%
   
0%
   
89%
   
 
332. . . . . . . . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg 2 50%
   
NA NA 100%
   
 
333. . . . . . . . . . . . . . . . . . . CalcCycleRunTime 6 50%
   
50%
   
NA 100%
   
 
334. . . . . . . . . . . . . . . . . . . . . . EdgeBi 1 NA 50%
   
NA 100%
   
 
335. . . . . . . . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg 2 50%
   
NA NA 100%
   
 
336. . . . . . . . . . . . . . . . . . . CalcRunTimeSum 3 50%
   
NA NA 100%
   
 
337. . . . . . . . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg 2 50%
   
NA NA 100%
   
 
338. . . . . . . . . . . . . . . . . . . CalcShortMinSOCID 4 33%
   
50%
   
0%
   
89%
   
 
339. . . . . . . . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg 2 50%
   
NA NA 100%
   
 
340. . . . . . . . . . . . . . . . . . . CalcShortSOCDiff 4 33%
   
50%
   
0%
   
89%
   
 
341. . . . . . . . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg 2 50%
   
NA NA 100%
   
 
342. . . . . . . . . . . . . . . . . . . EdgeRising 1 NA 50%
   
0%
   
100%
   
 
343. . . . . . . . . . . . . . . . . . . OCVSOC_Calc 31 3%
   
0%
   
NA 5%
   
 
344. . . . . . . . . . . . . . . . . . . . . . 2D_Config_Word1 11 0%
   
NA NA 0%
   
 
345. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem   NA NA NA 0%
   
 
346. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem1   NA NA NA 0%
   
 
347. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem2   NA NA NA 0%
   
 
348. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem3   NA NA NA 0%
   
 
349. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem4   NA NA NA 0%
   
 
350. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem5   NA NA NA 0%
   
 
351. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem6   NA NA NA 0%
   
 
352. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem7   NA NA NA 0%
   
 
353. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem8   NA NA NA 0%
   
 
354. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem9   NA NA NA 0%
   
 
355. . . . . . . . . . . . . . . . . . . . . . 2D_Config_Word2 11 0%
   
NA NA 0%
   
 
356. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem   NA NA NA 0%
   
 
357. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem1   NA NA NA 0%
   
 
358. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem2   NA NA NA 0%
   
 
359. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem3   NA NA NA 0%
   
 
360. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem4   NA NA NA 0%
   
 
361. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem5   NA NA NA 0%
   
 
362. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem6   NA NA NA 0%
   
 
363. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem7   NA NA NA 0%
   
 
364. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem8   NA NA NA 0%
   
 
365. . . . . . . . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem9   NA NA NA 0%
   
 
366. . . . . . . . . . . . . . . . . . . . . . MinOCVSOC_ForIterator 7 0%
   
0%
   
NA 8%
   
 
367. . . . . . . . . . . . . . . . . . . . . . . . . MinCellOCVSOCNumb_ForIterator 6 0%
   
0%
   
NA 9%
   
 
368. . . . . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC1 2 0%
   
NA NA 0%
   
 
369. . . . . . . . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC2 2 0%
   
NA NA 0%
   
 
370. . . . . . . . . . . . . . . . . . . ShortThmRnwyAlrmDet 2 50%
   
50%
   
0%
   
100%
   
 
371. . . . . . . . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg 2 50%
   
NA NA 100%
   
 
372. . . . . . . . . . . . . . . . . . . ShortThmRnwyWarnDet 2 50%
   
50%
   
NA 100%
   
 
373. . . . . . . . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg 2 50%
   
NA NA 100%
   
 
374. . . . . . . . . . . . . . . . WriteNVMData 2 100%
   
NA NA 100%
   
 
375. . . . . . . . . . . . . TPLWakeUpSet 5 50%
   
50%
   
NA 100%
   
 
376. . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg1 2 50%
   
NA NA 100%
   
 
377. . . . . . . . . . . . . . . . HDP_GbHDP_PackCrntSelfChck_flg2 2 50%
   
NA NA 100%
   
 

Details

1. Model "TRA"

Child Systems: TRA

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2948
Condition NA 61% (2597/4274) condition outcomes
Decision NA 60% (3407/5635) decision outcomes
MCDC NA 10% (14/147) conditions reversed the outcome
Execution NA 86% (1164/1348) objective outcomes

2. SubSystem block "TRA"

Justify or Exclude
Parent: /TRA
Child Systems: ThemRunAway_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2943
Condition NA 61% (2597/4274) condition outcomes
Decision NA 60% (3407/5635) decision outcomes
MCDC NA 10% (14/147) conditions reversed the outcome
Execution NA 86% (1164/1348) objective outcomes

3. SubSystem block "ThemRunAway_10ms"

Justify or Exclude
Parent: TRA/TRA
Child Systems: ThemRunAway_10ms_sys

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2943
Condition NA 61% (2597/4274) condition outcomes
Decision 100% (1/1) decision outcomes 60% (3407/5635) decision outcomes
MCDC NA 10% (14/147) conditions reversed the outcome
Execution NA 86% (1164/1348) objective outcomes

  Decisions analyzed
  Function call  100%
      executed 1601/1601

4. SubSystem block "ThemRunAway_10ms_sys"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms
Child Systems: RunawayFinishChk,  RunawayStateDet,  RunawayTempCheck,  RunawayWarnAlarmCheck,  TPLWakeUpSet

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2942
Condition NA 61% (2597/4274) condition outcomes
Decision NA 60% (3406/5634) decision outcomes
MCDC NA 10% (14/147) conditions reversed the outcome
Execution NA 86% (1164/1348) objective outcomes

5. SubSystem block "RunawayFinishChk"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys
Child Systems: BMSDelay,  HDP_GbHDP_PackCrntSelfChck_flg1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 7
Condition NA 50% (6/12) condition outcomes
Decision NA 60% (6/10) decision outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 100% (22/22) objective outcomes

   Logic block "Logical1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayFinishChk
Uncovered Links:  Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2 
1601 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TF) FF
      input port 2 (FT) FF


   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayFinishChk
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayFinishChk
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 
1601 

   RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayFinishChk
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 
1601 

   Full Coverage

Model Object Metric
S-Function block "Bitwise Logical Operator" Execution
S-Function block "Bitwise Logical Operator1" Execution
Constant block "Constant1" Execution
Constant block "Constant15" Execution
Constant block "Constant18" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant9" Execution

6. SubSystem block "BMSDelay"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayFinishChk
Child Systems: Unit Delay Resettable

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 4
Condition NA 50% (2/4) condition outcomes
Decision NA 67% (4/6) decision outcomes
Execution NA 100% (7/7) objective outcomes

   Logic block "Logical Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayFinishChk/BMSDelay
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayFinishChk/BMSDelay
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayFinishChk/BMSDelay
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
1601 

   Full Coverage

Model Object Metric
Sum block "Add" Execution
Constant block "Constant" Execution

7. SubSystem block "Unit Delay Resettable"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayFinishChk/BMSDelay

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 75% (3/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Switch block "Reset"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayFinishChk/BMSDelay/Unit Delay Resettable
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution

8. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayFinishChk

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayFinishChk/HDP_GbHDP_PackCrntSelfChck_flg1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

9. SubSystem block "RunawayStateDet"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys
Child Systems: LDP_GeLDP_CC2St_enum

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 5
Decision NA 63% (5/8) decision outcomes
Execution NA 100% (11/11) objective outcomes

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayStateDet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1410/1410
      true (output is from 1st input port) 0/1410

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayStateDet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1410/1410
      true (output is from 1st input port) 0/1410

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
DataTypeConversion block "Data Type Conversion2" Execution
Constant block "Constant1" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant5" Execution

10. SubSystem block "LDP_GeLDP_CC2St_enum"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayStateDet

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayStateDet/LDP_GeLDP_CC2St_enum
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

11. SubSystem block "RunawayTempCheck"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys
Child Systems: HDP_GbHDP_PackCrntSelfChck_flg,  RunawayBusbarTempCheck,  RunawayCellTempCheck,  RunawayVoltTempCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2797
Condition NA 61% (2483/4080) condition outcomes
Decision NA 61% (3344/5462) decision outcomes
MCDC NA 5% (5/93) conditions reversed the outcome
Execution NA 90% (878/974) objective outcomes

   Logic block "Logical1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 100% (4/4) condition outcomes
MCDC 9% (1/11) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 4 blocks
Decision/Condition True Out False Out
C1 || (((((((C2 && C3) && C4) && C5) || C6) || C7) || C8) || ((C9 && C10) && C11))
      C1 (Logical1 In1) (TFFFTFFFTFT) FFFFTFFFFFF
      C2 (Logical5 In1) (FTTTTFFFFFF) (FFTTTFFFFFF)
      C3 (Logical5 In2) (FTTTTFFFFFF) (FTFTTFFFFFF)
      C4 (Logical5 In3) (FTTTTFFFFFF) (FTTFTFFFFFF)
      C5 (Logical5 In4) (FTTTTFFFFFF) (FTTTFFFFFFF)
      C6 (Logical3 In2) (FFFFTTFFTFT) FFFFTFFFFFF
      C7 (Logical3 In3) (FFFFTFTFTFT) FFFFTFFFFFF
      C8 (Logical3 In4) (FFFFTFFTTFT) FFFFTFFFFFF
      C9 (Logical In1) FFFFTFFFTTT (FFFFTFFFFTT)
      C10 (Logical In2) FFFFTFFFTTT FFFFTFFFTFT
      C11 (Logical In3) FFFFTFFFTTT (FFFFTFFFTTF)


   Logic block "Logical3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 60% (6/10) condition outcomes
MCDC see Logical1
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2 
1601 
  input port 3 
1601 
  input port 4 
1601 
  input port 5  191  1410 

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay21" Execution

12. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/HDP_GbHDP_PackCrntSelfChck_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

13. SubSystem block "RunawayBusbarTempCheck"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck
Child Systems: BMSDelay2,  BusbarMaxTempDiag,  BusbarTempDiffDiag,  BusbarTempGradDiag

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1338
Condition NA 66% (971/1468) condition outcomes
Decision NA 63% (1657/2638) decision outcomes
MCDC NA 27% (4/15) conditions reversed the outcome
Execution NA 98% (311/317) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck

Metric Coverage
Cyclomatic Complexity 0
Condition 100% (6/6) condition outcomes
MCDC see Logical1
Execution 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Logic block "Logical2" Condition, Execution
Constant block "Constant1" Execution
Constant block "Constant2" Execution
UnitDelay block "Unit Delay1" Execution

14. SubSystem block "BMSDelay2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck
Child Systems: Unit Delay Resettable

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 4
Condition NA 100% (4/4) condition outcomes
Decision NA 100% (6/6) decision outcomes
Execution NA 100% (7/7) objective outcomes

   Full Coverage

Model Object Metric
Logic block "Logical Operator" Condition, Execution
Switch block "Switch" Decision, Execution
Sum block "Add" Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution

15. SubSystem block "Unit Delay Resettable"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BMSDelay2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 100% (4/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution
Switch block "Reset" Decision, Execution

16. SubSystem block "BusbarMaxTempDiag"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck
Child Systems: DebounceStartZero,  DebounceStartZero1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 28
Condition NA 88% (28/32) condition outcomes
Decision NA 75% (39/52) decision outcomes
MCDC NA 50% (1/2) conditions reversed the outcome
Execution NA 97% (76/78) objective outcomes

   Logic block "Logical1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 75% (3/4) condition outcomes
MCDC 50% (1/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  191  1410 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TF) FF
      input port 2 FT FF


   Full Coverage

Model Object Metric
RelationalOperator block "Comparison1" Condition, Execution
RelationalOperator block "Comparison6" Condition, Execution
Constant block "Constant1" Execution
Constant block "Constant10" Execution
Constant block "Constant11" Execution
Constant block "Constant12" Execution
Constant block "Constant16" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution
Constant block "Constant6" Execution
Constant block "Constant7" Execution
Constant block "Constant8" Execution
Constant block "Constant9" Execution

17. SubSystem block "DebounceStartZero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag
Child Systems: Compare To Zero,  FaultProcess,  HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 14
Condition NA 92% (11/12) condition outcomes
Decision NA 77% (20/26) decision outcomes
Execution NA 97% (31/32) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
UnitDelay block "Unit Delay" Execution

18. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 100% (2/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
RelationalOperator block "Compare" Condition, Execution

19. SubSystem block "FaultProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero
Child Systems: Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 75% (3/4) condition outcomes
Decision NA 75% (9/12) decision outcomes
Execution NA 93% (13/14) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
Switch block "Switch1" Decision, Execution
Switch block "Switch2" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

20. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero/FaultProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 50% (1/2) condition outcomes
Decision NA 50% (1/2) decision outcomes
Execution NA 75% (3/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 410/410
      true (output is from 1st input port) 0/410

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
410 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

21. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero/FaultProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero/FaultProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

22. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero/FaultProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 50% (2/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 50% (2/4) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input > lower limit  50%
      false 0/1191
      true 1191/1191
  input >= upper limit  50%
      false 1191/1191
      true 0/1191

   Full Coverage

Model Object Metric
Sum block "Add" Execution

23. SubSystem block "HealProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero
Child Systems: Compare To Zero,  Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 100% (6/6) condition outcomes
Decision NA 75% (9/12) decision outcomes
Execution NA 100% (15/15) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1140/1140
      true (output is from 1st input port) 0/1140

   Full Coverage

Model Object Metric
Switch block "Switch1" Decision, Execution
Switch block "Switch2" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay1" Execution
UnitDelay block "Unit Delay2" Execution

24. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 100% (2/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
RelationalOperator block "Compare" Condition, Execution

25. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero/HealProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 100% (2/2) condition outcomes
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (4/4) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution

26. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero/HealProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Sum block "Add" Execution

27. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 50% (2/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero/HealProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 50% (2/4) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input > lower limit  50%
      false 0/410
      true 410/410
  input >= upper limit  50%
      false 410/410
      true 0/410

   Full Coverage

Model Object Metric
Sum block "Add" Execution

28. SubSystem block "DebounceStartZero1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag
Child Systems: Compare To Zero,  FaultProcess,  HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 14
Condition NA 83% (10/12) condition outcomes
Decision NA 73% (19/26) decision outcomes
Execution NA 97% (31/32) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
UnitDelay block "Unit Delay" Execution

29. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 100% (2/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
RelationalOperator block "Compare" Condition, Execution

30. SubSystem block "FaultProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero1
Child Systems: Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 75% (3/4) condition outcomes
Decision NA 75% (9/12) decision outcomes
Execution NA 93% (13/14) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
Switch block "Switch1" Decision, Execution
Switch block "Switch2" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

31. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero1/FaultProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 50% (1/2) condition outcomes
Decision NA 50% (1/2) decision outcomes
Execution NA 75% (3/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero1/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 410/410
      true (output is from 1st input port) 0/410

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero1/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
410 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

32. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero1/FaultProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero1/FaultProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

33. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero1/FaultProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 50% (2/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero1/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 50% (2/4) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input > lower limit  50%
      false 0/1191
      true 1191/1191
  input >= upper limit  50%
      false 1191/1191
      true 0/1191

   Full Coverage

Model Object Metric
Sum block "Add" Execution

34. SubSystem block "HealProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero1
Child Systems: Compare To Zero,  Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 83% (5/6) condition outcomes
Decision NA 67% (8/12) decision outcomes
Execution NA 100% (15/15) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero1/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 190/190
      true (output is from 1st input port) 0/190

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero1/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero1/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
1601 

   Full Coverage

Model Object Metric
Switch block "Switch1" Decision, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay1" Execution
UnitDelay block "Unit Delay2" Execution

35. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero1/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 100% (2/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
RelationalOperator block "Compare" Condition, Execution

36. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero1/HealProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 100% (2/2) condition outcomes
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (4/4) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution

37. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero1/HealProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Sum block "Add" Execution

38. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero1/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 50% (2/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarMaxTempDiag/DebounceStartZero1/HealProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 50% (2/4) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input > lower limit  50%
      false 0/410
      true 410/410
  input >= upper limit  50%
      false 410/410
      true 0/410

   Full Coverage

Model Object Metric
Sum block "Add" Execution

39. SubSystem block "BusbarTempDiffDiag"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck
Child Systems: DebounceStartZero1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 14
Condition NA 93% (13/14) condition outcomes
Decision NA 77% (20/26) decision outcomes
Execution NA 97% (38/39) objective outcomes

   Full Coverage

Model Object Metric
Sum block "Sum1" Execution
RelationalOperator block "Comparison6" Condition, Execution
Constant block "Constant1" Execution
Constant block "Constant12" Execution
Constant block "Constant15" Execution
Constant block "Constant17" Execution
Constant block "Constant2" Execution

40. SubSystem block "DebounceStartZero1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempDiffDiag
Child Systems: Compare To Zero,  FaultProcess,  HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 14
Condition NA 92% (11/12) condition outcomes
Decision NA 77% (20/26) decision outcomes
Execution NA 97% (31/32) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
UnitDelay block "Unit Delay" Execution

41. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempDiffDiag/DebounceStartZero1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 100% (2/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
RelationalOperator block "Compare" Condition, Execution

42. SubSystem block "FaultProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempDiffDiag/DebounceStartZero1
Child Systems: Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 75% (3/4) condition outcomes
Decision NA 75% (9/12) decision outcomes
Execution NA 93% (13/14) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
Switch block "Switch1" Decision, Execution
Switch block "Switch2" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

43. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempDiffDiag/DebounceStartZero1/FaultProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 50% (1/2) condition outcomes
Decision NA 50% (1/2) decision outcomes
Execution NA 75% (3/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempDiffDiag/DebounceStartZero1/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 400/400
      true (output is from 1st input port) 0/400

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempDiffDiag/DebounceStartZero1/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
400 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

44. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempDiffDiag/DebounceStartZero1/FaultProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempDiffDiag/DebounceStartZero1/FaultProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

45. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempDiffDiag/DebounceStartZero1/FaultProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 50% (2/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempDiffDiag/DebounceStartZero1/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 50% (2/4) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input > lower limit  50%
      false 0/1201
      true 1201/1201
  input >= upper limit  50%
      false 1201/1201
      true 0/1201

   Full Coverage

Model Object Metric
Sum block "Add" Execution

46. SubSystem block "HealProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempDiffDiag/DebounceStartZero1
Child Systems: Compare To Zero,  Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 100% (6/6) condition outcomes
Decision NA 75% (9/12) decision outcomes
Execution NA 100% (15/15) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempDiffDiag/DebounceStartZero1/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1000/1000
      true (output is from 1st input port) 0/1000

   Full Coverage

Model Object Metric
Switch block "Switch1" Decision, Execution
Switch block "Switch2" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay1" Execution
UnitDelay block "Unit Delay2" Execution

47. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempDiffDiag/DebounceStartZero1/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 100% (2/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
RelationalOperator block "Compare" Condition, Execution

48. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempDiffDiag/DebounceStartZero1/HealProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 100% (2/2) condition outcomes
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (4/4) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution

49. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempDiffDiag/DebounceStartZero1/HealProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Sum block "Add" Execution

50. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempDiffDiag/DebounceStartZero1/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 50% (2/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempDiffDiag/DebounceStartZero1/HealProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 50% (2/4) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input > lower limit  50%
      false 0/400
      true 400/400
  input >= upper limit  50%
      false 400/400
      true 0/400

   Full Coverage

Model Object Metric
Sum block "Add" Execution

51. SubSystem block "BusbarTempGradDiag"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck
Child Systems: BMSDelay,  BusbarTempGradDiag,  CalcBusbarTempGrad

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 2 1292
Condition NA 65% (918/1410) condition outcomes
Decision 100% (2/2) decision outcomes 62% (1592/2554) decision outcomes
MCDC NA 23% (3/13) conditions reversed the outcome
Execution NA 98% (185/188) objective outcomes

  Decisions analyzed
  enable logical value  100%
      false 1468/1601
      true 133/1601

   Full Coverage

Model Object Metric
Constant block "Constant1" Execution
Constant block "Constant13" Execution
Constant block "Constant4" Execution

52. SubSystem block "BMSDelay"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag
Child Systems: Unit Delay Resettable

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 4
Condition NA 75% (3/4) condition outcomes
Decision NA 83% (5/6) decision outcomes
Execution NA 100% (7/7) objective outcomes

   Logic block "Logical Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BMSDelay
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
Sum block "Add" Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution

53. SubSystem block "Unit Delay Resettable"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BMSDelay

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 75% (3/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Switch block "Reset"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BMSDelay/Unit Delay Resettable
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 133/133
      true (output is from 1st input port) 0/133

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution

54. SubSystem block "BusbarTempGradDiag"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag
Child Systems: Counter Reset Enabled ,  Counter Reset Enabled 1,  DebounceStartZero,  DebounceStartZero1,  DebounceStartZero2,  EdgeRising,  EdgeRising2,  MaxBusbarTempGrad_ForIterator1,  MaxBusbarTempGrad_ForIterator2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 2 1276
Condition NA 65% (915/1406) condition outcomes
Decision 100% (2/2) decision outcomes 62% (1575/2536) decision outcomes
MCDC NA 23% (3/13) conditions reversed the outcome
Execution NA 98% (159/162) objective outcomes

  Decisions analyzed
  enable logical value  100%
      false 20/133
      true 113/133

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical1
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
113 
  input port 2 
113 

   Logic block "AND1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag

Metric Coverage
Cyclomatic Complexity 0
Condition 100% (4/4) condition outcomes
MCDC see Logical3
Execution 100% (1/1) objective outcomes

   Logic block "AND2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 75% (3/4) condition outcomes
MCDC 33% (1/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  30  83 
  input port 2 
113 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
(C1 && C2) || C3
      C1 (Logical5 In1) TTF FTF
      C2 (Logical5 In2) TTF (TFF)
      C3 (AND2 In2) (FTT) FFF


   Logic block "Logical1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
113 
  input port 2  113 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 3 blocks
Decision/Condition True Out False Out
(C1 || C2) && ~C3
      C1 (AND In1) (TFF) FFF
      C2 (AND In2) (FTF) FFF
      C3 (Logical2 In1) (TTF) (TTT)


   Logic block "Logical2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see Logical1
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
113 

   Logic block "Logical3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 75% (3/4) condition outcomes
MCDC 67% (2/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  101  12 
  input port 2  113 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 3 blocks
Decision/Condition True Out False Out
(C1 || C2) && ~C3
      C1 (AND1 In1) TFF FFF
      C2 (AND1 In2) FTF FFF
      C3 (Logical4 In1) FTF (TFT)


   Logic block "Logical4"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see Logical3
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
113 

   Logic block "Logical5"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag

Metric Coverage
Cyclomatic Complexity 0
Condition 100% (4/4) condition outcomes
MCDC see AND2
Execution 100% (1/1) objective outcomes

   RelationalOperator block "Comparison"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 51% (49/96) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) >= input2  19  94 
  input1(2) >= input2 
113 
  input1(3) >= input2 
113 
  input1(4) >= input2 
113 
  input1(5) >= input2 
113 
  input1(6) >= input2 
113 
  input1(7) >= input2 
113 
  input1(8) >= input2 
113 
  input1(9) >= input2 
113 
  input1(10) >= input2 
113 
  input1(11) >= input2 
113 
  input1(12) >= input2 
113 
  input1(13) >= input2 
113 
  input1(14) >= input2 
113 
  input1(15) >= input2 
113 
  input1(16) >= input2 
113 
  input1(17) >= input2 
113 
  input1(18) >= input2 
113 
  input1(19) >= input2 
113 
  input1(20) >= input2 
113 
  input1(21) >= input2 
113 
  input1(22) >= input2 
113 
  input1(23) >= input2 
113 
  input1(24) >= input2 
113 
  input1(25) >= input2 
113 
  input1(26) >= input2 
113 
  input1(27) >= input2 
113 
  input1(28) >= input2 
113 
  input1(29) >= input2 
113 
  input1(30) >= input2 
113 
  input1(31) >= input2 
113 
  input1(32) >= input2 
113 
  input1(33) >= input2 
113 
  input1(34) >= input2 
113 
  input1(35) >= input2 
113 
  input1(36) >= input2 
113 
  input1(37) >= input2 
113 
  input1(38) >= input2 
113 
  input1(39) >= input2 
113 
  input1(40) >= input2 
113 
  input1(41) >= input2 
113 
  input1(42) >= input2 
113 
  input1(43) >= input2 
113 
  input1(44) >= input2 
113 
  input1(45) >= input2 
113 
  input1(46) >= input2 
113 
  input1(47) >= input2 
113 
  input1(48) >= input2 
113 

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
113 

   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
113 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 51% (49/96) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) >= input2  19  94 
  input1(2) >= input2 
113 
  input1(3) >= input2 
113 
  input1(4) >= input2 
113 
  input1(5) >= input2 
113 
  input1(6) >= input2 
113 
  input1(7) >= input2 
113 
  input1(8) >= input2 
113 
  input1(9) >= input2 
113 
  input1(10) >= input2 
113 
  input1(11) >= input2 
113 
  input1(12) >= input2 
113 
  input1(13) >= input2 
113 
  input1(14) >= input2 
113 
  input1(15) >= input2 
113 
  input1(16) >= input2 
113 
  input1(17) >= input2 
113 
  input1(18) >= input2 
113 
  input1(19) >= input2 
113 
  input1(20) >= input2 
113 
  input1(21) >= input2 
113 
  input1(22) >= input2 
113 
  input1(23) >= input2 
113 
  input1(24) >= input2 
113 
  input1(25) >= input2 
113 
  input1(26) >= input2 
113 
  input1(27) >= input2 
113 
  input1(28) >= input2 
113 
  input1(29) >= input2 
113 
  input1(30) >= input2 
113 
  input1(31) >= input2 
113 
  input1(32) >= input2 
113 
  input1(33) >= input2 
113 
  input1(34) >= input2 
113 
  input1(35) >= input2 
113 
  input1(36) >= input2 
113 
  input1(37) >= input2 
113 
  input1(38) >= input2 
113 
  input1(39) >= input2 
113 
  input1(40) >= input2 
113 
  input1(41) >= input2 
113 
  input1(42) >= input2 
113 
  input1(43) >= input2 
113 
  input1(44) >= input2 
113 
  input1(45) >= input2 
113 
  input1(46) >= input2 
113 
  input1(47) >= input2 
113 
  input1(48) >= input2 
113 

   RelationalOperator block "Comparison5"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
113 

   Full Coverage

Model Object Metric
Product block "Product" Execution
Product block "Product1" Execution
RelationalOperator block "Comparison4" Condition, Execution
RelationalOperator block "Comparison6" Condition, Execution
Constant block "Constant10" Execution
Constant block "Constant11" Execution
Constant block "Constant12" Execution
Constant block "Constant14" Execution
Constant block "Constant15" Execution
Constant block "Constant16" Execution
Constant block "Constant17" Execution
Constant block "Constant18" Execution
Constant block "Constant19" Execution
Constant block "Constant2" Execution
Constant block "Constant20" Execution
Constant block "Constant21" Execution
Constant block "Constant22" Execution
Constant block "Constant23" Execution
Constant block "Constant24" Execution
Constant block "Constant3" Execution
Constant block "Constant5" Execution
Constant block "Constant6" Execution
Constant block "Constant7" Execution
Constant block "Constant8" Execution
Constant block "Constant9" Execution
UnitDelay block "Unit Delay5" Execution
UnitDelay block "Unit Delay6" Execution
UnitDelay block "Unit Delay7" Execution
UnitDelay block "Unit Delay8" Execution

55. SubSystem block "Counter Reset Enabled "

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 3
Decision NA 50% (2/4) decision outcomes
Execution NA 83% (5/6) objective outcomes

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/Counter Reset Enabled
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/Counter Reset Enabled
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   Sum block "Subtraction"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/Counter Reset Enabled
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant Value1" Execution
Constant block "Constant Value2" Execution
UnitDelay block "Unit Delay" Execution

56. SubSystem block "Counter Reset Enabled 1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 3
Decision NA 75% (3/4) decision outcomes
Execution NA 100% (6/6) objective outcomes

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/Counter Reset Enabled 1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   Full Coverage

Model Object Metric
Switch block "Switch2" Decision, Execution
Sum block "Subtraction" Execution
Constant block "Constant Value1" Execution
Constant block "Constant Value2" Execution
UnitDelay block "Unit Delay" Execution

57. SubSystem block "DebounceStartZero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag
Child Systems: Compare To Zero,  FaultProcess,  HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 14
Condition NA 83% (10/12) condition outcomes
Decision NA 73% (19/26) decision outcomes
Execution NA 94% (30/32) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
UnitDelay block "Unit Delay" Execution

58. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 100% (2/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
RelationalOperator block "Compare" Condition, Execution

59. SubSystem block "FaultProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero
Child Systems: Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 75% (3/4) condition outcomes
Decision NA 75% (9/12) decision outcomes
Execution NA 93% (13/14) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
Switch block "Switch1" Decision, Execution
Switch block "Switch2" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

60. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero/FaultProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 50% (1/2) condition outcomes
Decision NA 50% (1/2) decision outcomes
Execution NA 75% (3/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 63/63
      true (output is from 1st input port) 0/63

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
63 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

61. SubSystem block "Nomal"

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Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero/FaultProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero/FaultProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

62. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero/FaultProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 50% (2/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 50% (2/4) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input > lower limit  50%
      false 0/50
      true 50/50
  input >= upper limit  50%
      false 50/50
      true 0/50

   Full Coverage

Model Object Metric
Sum block "Add" Execution

63. SubSystem block "HealProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero
Child Systems: Compare To Zero,  Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 83% (5/6) condition outcomes
Decision NA 67% (8/12) decision outcomes
Execution NA 93% (14/15) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 29/29
      true (output is from 1st input port) 0/29

   Full Coverage

Model Object Metric
Switch block "Switch1" Decision, Execution
Switch block "Switch2" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay1" Execution
UnitDelay block "Unit Delay2" Execution

64. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 100% (2/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
RelationalOperator block "Compare" Condition, Execution

65. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero/HealProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 50% (1/2) condition outcomes
Decision NA 50% (1/2) decision outcomes
Execution NA 75% (3/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero/HealProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 50/50
      true (output is from 1st input port) 0/50

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero/HealProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
50 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

66. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero/HealProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero/HealProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

67. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 50% (2/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero/HealProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 50% (2/4) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input > lower limit  50%
      false 0/63
      true 63/63
  input >= upper limit  50%
      false 63/63
      true 0/63

   Full Coverage

Model Object Metric
Sum block "Add" Execution

68. SubSystem block "DebounceStartZero1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag
Child Systems: Compare To Zero,  FaultProcess,  HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 625
Condition NA 67% (388/576) condition outcomes
Decision NA 62% (774/1248) decision outcomes
Execution NA 100% (32/32) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 51% (49/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  100%
      false (output is from 3rd input port) 14/113
      true (output is from 1st input port) 99/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

69. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 51% (49/96) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 51% (49/96) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) == input2  99  14 
  input1(2) == input2  113 
  input1(3) == input2  113 
  input1(4) == input2  113 
  input1(5) == input2  113 
  input1(6) == input2  113 
  input1(7) == input2  113 
  input1(8) == input2  113 
  input1(9) == input2  113 
  input1(10) == input2  113 
  input1(11) == input2  113 
  input1(12) == input2  113 
  input1(13) == input2  113 
  input1(14) == input2  113 
  input1(15) == input2  113 
  input1(16) == input2  113 
  input1(17) == input2  113 
  input1(18) == input2  113 
  input1(19) == input2  113 
  input1(20) == input2  113 
  input1(21) == input2  113 
  input1(22) == input2  113 
  input1(23) == input2  113 
  input1(24) == input2  113 
  input1(25) == input2  113 
  input1(26) == input2  113 
  input1(27) == input2  113 
  input1(28) == input2  113 
  input1(29) == input2  113 
  input1(30) == input2  113 
  input1(31) == input2  113 
  input1(32) == input2  113 
  input1(33) == input2  113 
  input1(34) == input2  113 
  input1(35) == input2  113 
  input1(36) == input2  113 
  input1(37) == input2  113 
  input1(38) == input2  113 
  input1(39) == input2  113 
  input1(40) == input2  113 
  input1(41) == input2  113 
  input1(42) == input2  113 
  input1(43) == input2  113 
  input1(44) == input2  113 
  input1(45) == input2  113 
  input1(46) == input2  113 
  input1(47) == input2  113 
  input1(48) == input2  113 

70. SubSystem block "FaultProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1
Child Systems: Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 288
Condition NA 51% (98/192) condition outcomes
Decision NA 51% (292/576) decision outcomes
Execution NA 100% (14/14) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 51% (49/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  100%
      false (output is from 3rd input port) 112/113
      true (output is from 1st input port) 1/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 51% (49/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  100%
      false (output is from 3rd input port) 94/113
      true (output is from 1st input port) 19/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 51% (49/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  100%
      false (output is from 3rd input port) 112/113
      true (output is from 1st input port) 1/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 51% (49/96) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) > input2  112 
  input1(2) > input2 
113 
  input1(3) > input2 
113 
  input1(4) > input2 
113 
  input1(5) > input2 
113 
  input1(6) > input2 
113 
  input1(7) > input2 
113 
  input1(8) > input2 
113 
  input1(9) > input2 
113 
  input1(10) > input2 
113 
  input1(11) > input2 
113 
  input1(12) > input2 
113 
  input1(13) > input2 
113 
  input1(14) > input2 
113 
  input1(15) > input2 
113 
  input1(16) > input2 
113 
  input1(17) > input2 
113 
  input1(18) > input2 
113 
  input1(19) > input2 
113 
  input1(20) > input2 
113 
  input1(21) > input2 
113 
  input1(22) > input2 
113 
  input1(23) > input2 
113 
  input1(24) > input2 
113 
  input1(25) > input2 
113 
  input1(26) > input2 
113 
  input1(27) > input2 
113 
  input1(28) > input2 
113 
  input1(29) > input2 
113 
  input1(30) > input2 
113 
  input1(31) > input2 
113 
  input1(32) > input2 
113 
  input1(33) > input2 
113 
  input1(34) > input2 
113 
  input1(35) > input2 
113 
  input1(36) > input2 
113 
  input1(37) > input2 
113 
  input1(38) > input2 
113 
  input1(39) > input2 
113 
  input1(40) > input2 
113 
  input1(41) > input2 
113 
  input1(42) > input2 
113 
  input1(43) > input2 
113 
  input1(44) > input2 
113 
  input1(45) > input2 
113 
  input1(46) > input2 
113 
  input1(47) > input2 
113 
  input1(48) > input2 
113 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

71. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1/FaultProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 48
Condition NA 51% (49/96) condition outcomes
Decision NA 51% (49/96) decision outcomes
Execution NA 100% (4/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 51% (49/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  100%
      false (output is from 3rd input port) 86/113
      true (output is from 1st input port) 27/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 51% (49/96) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) >= input2  27  86 
  input1(2) >= input2 
113 
  input1(3) >= input2 
113 
  input1(4) >= input2 
113 
  input1(5) >= input2 
113 
  input1(6) >= input2 
113 
  input1(7) >= input2 
113 
  input1(8) >= input2 
113 
  input1(9) >= input2 
113 
  input1(10) >= input2 
113 
  input1(11) >= input2 
113 
  input1(12) >= input2 
113 
  input1(13) >= input2 
113 
  input1(14) >= input2 
113 
  input1(15) >= input2 
113 
  input1(16) >= input2 
113 
  input1(17) >= input2 
113 
  input1(18) >= input2 
113 
  input1(19) >= input2 
113 
  input1(20) >= input2 
113 
  input1(21) >= input2 
113 
  input1(22) >= input2 
113 
  input1(23) >= input2 
113 
  input1(24) >= input2 
113 
  input1(25) >= input2 
113 
  input1(26) >= input2 
113 
  input1(27) >= input2 
113 
  input1(28) >= input2 
113 
  input1(29) >= input2 
113 
  input1(30) >= input2 
113 
  input1(31) >= input2 
113 
  input1(32) >= input2 
113 
  input1(33) >= input2 
113 
  input1(34) >= input2 
113 
  input1(35) >= input2 
113 
  input1(36) >= input2 
113 
  input1(37) >= input2 
113 
  input1(38) >= input2 
113 
  input1(39) >= input2 
113 
  input1(40) >= input2 
113 
  input1(41) >= input2 
113 
  input1(42) >= input2 
113 
  input1(43) >= input2 
113 
  input1(44) >= input2 
113 
  input1(45) >= input2 
113 
  input1(46) >= input2 
113 
  input1(47) >= input2 
113 
  input1(48) >= input2 
113 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

72. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1/FaultProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Sum block "Add" Execution

73. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1/FaultProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 96
Decision NA 50% (96/192) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 96
Decision 50% (96/192) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input(1) > lower limit  50%
      false 0/113
      true 113/113
  input(1) >= upper limit  50%
      false 113/113
      true 0/113
  input(2) > lower limit  50%
      false 0/113
      true 113/113
  input(2) >= upper limit  50%
      false 113/113
      true 0/113
  input(3) > lower limit  50%
      false 0/113
      true 113/113
  input(3) >= upper limit  50%
      false 113/113
      true 0/113
  input(4) > lower limit  50%
      false 0/113
      true 113/113
  input(4) >= upper limit  50%
      false 113/113
      true 0/113
  input(5) > lower limit  50%
      false 0/113
      true 113/113
  input(5) >= upper limit  50%
      false 113/113
      true 0/113
  input(6) > lower limit  50%
      false 0/113
      true 113/113
  input(6) >= upper limit  50%
      false 113/113
      true 0/113
  input(7) > lower limit  50%
      false 0/113
      true 113/113
  input(7) >= upper limit  50%
      false 113/113
      true 0/113
  input(8) > lower limit  50%
      false 0/113
      true 113/113
  input(8) >= upper limit  50%
      false 113/113
      true 0/113
  input(9) > lower limit  50%
      false 0/113
      true 113/113
  input(9) >= upper limit  50%
      false 113/113
      true 0/113
  input(10) > lower limit  50%
      false 0/113
      true 113/113
  input(10) >= upper limit  50%
      false 113/113
      true 0/113
  input(11) > lower limit  50%
      false 0/113
      true 113/113
  input(11) >= upper limit  50%
      false 113/113
      true 0/113
  input(12) > lower limit  50%
      false 0/113
      true 113/113
  input(12) >= upper limit  50%
      false 113/113
      true 0/113
  input(13) > lower limit  50%
      false 0/113
      true 113/113
  input(13) >= upper limit  50%
      false 113/113
      true 0/113
  input(14) > lower limit  50%
      false 0/113
      true 113/113
  input(14) >= upper limit  50%
      false 113/113
      true 0/113
  input(15) > lower limit  50%
      false 0/113
      true 113/113
  input(15) >= upper limit  50%
      false 113/113
      true 0/113
  input(16) > lower limit  50%
      false 0/113
      true 113/113
  input(16) >= upper limit  50%
      false 113/113
      true 0/113
  input(17) > lower limit  50%
      false 0/113
      true 113/113
  input(17) >= upper limit  50%
      false 113/113
      true 0/113
  input(18) > lower limit  50%
      false 0/113
      true 113/113
  input(18) >= upper limit  50%
      false 113/113
      true 0/113
  input(19) > lower limit  50%
      false 0/113
      true 113/113
  input(19) >= upper limit  50%
      false 113/113
      true 0/113
  input(20) > lower limit  50%
      false 0/113
      true 113/113
  input(20) >= upper limit  50%
      false 113/113
      true 0/113
  input(21) > lower limit  50%
      false 0/113
      true 113/113
  input(21) >= upper limit  50%
      false 113/113
      true 0/113
  input(22) > lower limit  50%
      false 0/113
      true 113/113
  input(22) >= upper limit  50%
      false 113/113
      true 0/113
  input(23) > lower limit  50%
      false 0/113
      true 113/113
  input(23) >= upper limit  50%
      false 113/113
      true 0/113
  input(24) > lower limit  50%
      false 0/113
      true 113/113
  input(24) >= upper limit  50%
      false 113/113
      true 0/113
  input(25) > lower limit  50%
      false 0/113
      true 113/113
  input(25) >= upper limit  50%
      false 113/113
      true 0/113
  input(26) > lower limit  50%
      false 0/113
      true 113/113
  input(26) >= upper limit  50%
      false 113/113
      true 0/113
  input(27) > lower limit  50%
      false 0/113
      true 113/113
  input(27) >= upper limit  50%
      false 113/113
      true 0/113
  input(28) > lower limit  50%
      false 0/113
      true 113/113
  input(28) >= upper limit  50%
      false 113/113
      true 0/113
  input(29) > lower limit  50%
      false 0/113
      true 113/113
  input(29) >= upper limit  50%
      false 113/113
      true 0/113
  input(30) > lower limit  50%
      false 0/113
      true 113/113
  input(30) >= upper limit  50%
      false 113/113
      true 0/113
  input(31) > lower limit  50%
      false 0/113
      true 113/113
  input(31) >= upper limit  50%
      false 113/113
      true 0/113
  input(32) > lower limit  50%
      false 0/113
      true 113/113
  input(32) >= upper limit  50%
      false 113/113
      true 0/113
  input(33) > lower limit  50%
      false 0/113
      true 113/113
  input(33) >= upper limit  50%
      false 113/113
      true 0/113
  input(34) > lower limit  50%
      false 0/113
      true 113/113
  input(34) >= upper limit  50%
      false 113/113
      true 0/113
  input(35) > lower limit  50%
      false 0/113
      true 113/113
  input(35) >= upper limit  50%
      false 113/113
      true 0/113
  input(36) > lower limit  50%
      false 0/113
      true 113/113
  input(36) >= upper limit  50%
      false 113/113
      true 0/113
  input(37) > lower limit  50%
      false 0/113
      true 113/113
  input(37) >= upper limit  50%
      false 113/113
      true 0/113
  input(38) > lower limit  50%
      false 0/113
      true 113/113
  input(38) >= upper limit  50%
      false 113/113
      true 0/113
  input(39) > lower limit  50%
      false 0/113
      true 113/113
  input(39) >= upper limit  50%
      false 113/113
      true 0/113
  input(40) > lower limit  50%
      false 0/113
      true 113/113
  input(40) >= upper limit  50%
      false 113/113
      true 0/113
  input(41) > lower limit  50%
      false 0/113
      true 113/113
  input(41) >= upper limit  50%
      false 113/113
      true 0/113
  input(42) > lower limit  50%
      false 0/113
      true 113/113
  input(42) >= upper limit  50%
      false 113/113
      true 0/113
  input(43) > lower limit  50%
      false 0/113
      true 113/113
  input(43) >= upper limit  50%
      false 113/113
      true 0/113
  input(44) > lower limit  50%
      false 0/113
      true 113/113
  input(44) >= upper limit  50%
      false 113/113
      true 0/113
  input(45) > lower limit  50%
      false 0/113
      true 113/113
  input(45) >= upper limit  50%
      false 113/113
      true 0/113
  input(46) > lower limit  50%
      false 0/113
      true 113/113
  input(46) >= upper limit  50%
      false 113/113
      true 0/113
  input(47) > lower limit  50%
      false 0/113
      true 113/113
  input(47) >= upper limit  50%
      false 113/113
      true 0/113
  input(48) > lower limit  50%
      false 0/113
      true 113/113
  input(48) >= upper limit  50%
      false 113/113
      true 0/113

   Full Coverage

Model Object Metric
Sum block "Add" Execution

74. SubSystem block "HealProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1
Child Systems: Compare To Zero,  Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 288
Condition NA 84% (241/288) condition outcomes
Decision NA 75% (433/576) decision outcomes
Execution NA 100% (15/15) objective outcomes

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 51% (49/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  100%
      false (output is from 3rd input port) 19/113
      true (output is from 1st input port) 94/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
Switch block "Switch2" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay1" Execution
UnitDelay block "Unit Delay2" Execution

75. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 51% (49/96) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1/HealProcess/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 51% (49/96) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) == input2  94  19 
  input1(2) == input2  113 
  input1(3) == input2  113 
  input1(4) == input2  113 
  input1(5) == input2  113 
  input1(6) == input2  113 
  input1(7) == input2  113 
  input1(8) == input2  113 
  input1(9) == input2  113 
  input1(10) == input2  113 
  input1(11) == input2  113 
  input1(12) == input2  113 
  input1(13) == input2  113 
  input1(14) == input2  113 
  input1(15) == input2  113 
  input1(16) == input2  113 
  input1(17) == input2  113 
  input1(18) == input2  113 
  input1(19) == input2  113 
  input1(20) == input2  113 
  input1(21) == input2  113 
  input1(22) == input2  113 
  input1(23) == input2  113 
  input1(24) == input2  113 
  input1(25) == input2  113 
  input1(26) == input2  113 
  input1(27) == input2  113 
  input1(28) == input2  113 
  input1(29) == input2  113 
  input1(30) == input2  113 
  input1(31) == input2  113 
  input1(32) == input2  113 
  input1(33) == input2  113 
  input1(34) == input2  113 
  input1(35) == input2  113 
  input1(36) == input2  113 
  input1(37) == input2  113 
  input1(38) == input2  113 
  input1(39) == input2  113 
  input1(40) == input2  113 
  input1(41) == input2  113 
  input1(42) == input2  113 
  input1(43) == input2  113 
  input1(44) == input2  113 
  input1(45) == input2  113 
  input1(46) == input2  113 
  input1(47) == input2  113 
  input1(48) == input2  113 

76. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1/HealProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 48
Condition NA 100% (96/96) condition outcomes
Decision NA 100% (96/96) decision outcomes
Execution NA 100% (4/4) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution

77. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1/HealProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Sum block "Add" Execution

78. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 96
Decision NA 50% (96/192) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero1/HealProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 96
Decision 50% (96/192) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input(1) > lower limit  50%
      false 0/113
      true 113/113
  input(1) >= upper limit  50%
      false 113/113
      true 0/113
  input(2) > lower limit  50%
      false 0/113
      true 113/113
  input(2) >= upper limit  50%
      false 113/113
      true 0/113
  input(3) > lower limit  50%
      false 0/113
      true 113/113
  input(3) >= upper limit  50%
      false 113/113
      true 0/113
  input(4) > lower limit  50%
      false 0/113
      true 113/113
  input(4) >= upper limit  50%
      false 113/113
      true 0/113
  input(5) > lower limit  50%
      false 0/113
      true 113/113
  input(5) >= upper limit  50%
      false 113/113
      true 0/113
  input(6) > lower limit  50%
      false 0/113
      true 113/113
  input(6) >= upper limit  50%
      false 113/113
      true 0/113
  input(7) > lower limit  50%
      false 0/113
      true 113/113
  input(7) >= upper limit  50%
      false 113/113
      true 0/113
  input(8) > lower limit  50%
      false 0/113
      true 113/113
  input(8) >= upper limit  50%
      false 113/113
      true 0/113
  input(9) > lower limit  50%
      false 0/113
      true 113/113
  input(9) >= upper limit  50%
      false 113/113
      true 0/113
  input(10) > lower limit  50%
      false 0/113
      true 113/113
  input(10) >= upper limit  50%
      false 113/113
      true 0/113
  input(11) > lower limit  50%
      false 0/113
      true 113/113
  input(11) >= upper limit  50%
      false 113/113
      true 0/113
  input(12) > lower limit  50%
      false 0/113
      true 113/113
  input(12) >= upper limit  50%
      false 113/113
      true 0/113
  input(13) > lower limit  50%
      false 0/113
      true 113/113
  input(13) >= upper limit  50%
      false 113/113
      true 0/113
  input(14) > lower limit  50%
      false 0/113
      true 113/113
  input(14) >= upper limit  50%
      false 113/113
      true 0/113
  input(15) > lower limit  50%
      false 0/113
      true 113/113
  input(15) >= upper limit  50%
      false 113/113
      true 0/113
  input(16) > lower limit  50%
      false 0/113
      true 113/113
  input(16) >= upper limit  50%
      false 113/113
      true 0/113
  input(17) > lower limit  50%
      false 0/113
      true 113/113
  input(17) >= upper limit  50%
      false 113/113
      true 0/113
  input(18) > lower limit  50%
      false 0/113
      true 113/113
  input(18) >= upper limit  50%
      false 113/113
      true 0/113
  input(19) > lower limit  50%
      false 0/113
      true 113/113
  input(19) >= upper limit  50%
      false 113/113
      true 0/113
  input(20) > lower limit  50%
      false 0/113
      true 113/113
  input(20) >= upper limit  50%
      false 113/113
      true 0/113
  input(21) > lower limit  50%
      false 0/113
      true 113/113
  input(21) >= upper limit  50%
      false 113/113
      true 0/113
  input(22) > lower limit  50%
      false 0/113
      true 113/113
  input(22) >= upper limit  50%
      false 113/113
      true 0/113
  input(23) > lower limit  50%
      false 0/113
      true 113/113
  input(23) >= upper limit  50%
      false 113/113
      true 0/113
  input(24) > lower limit  50%
      false 0/113
      true 113/113
  input(24) >= upper limit  50%
      false 113/113
      true 0/113
  input(25) > lower limit  50%
      false 0/113
      true 113/113
  input(25) >= upper limit  50%
      false 113/113
      true 0/113
  input(26) > lower limit  50%
      false 0/113
      true 113/113
  input(26) >= upper limit  50%
      false 113/113
      true 0/113
  input(27) > lower limit  50%
      false 0/113
      true 113/113
  input(27) >= upper limit  50%
      false 113/113
      true 0/113
  input(28) > lower limit  50%
      false 0/113
      true 113/113
  input(28) >= upper limit  50%
      false 113/113
      true 0/113
  input(29) > lower limit  50%
      false 0/113
      true 113/113
  input(29) >= upper limit  50%
      false 113/113
      true 0/113
  input(30) > lower limit  50%
      false 0/113
      true 113/113
  input(30) >= upper limit  50%
      false 113/113
      true 0/113
  input(31) > lower limit  50%
      false 0/113
      true 113/113
  input(31) >= upper limit  50%
      false 113/113
      true 0/113
  input(32) > lower limit  50%
      false 0/113
      true 113/113
  input(32) >= upper limit  50%
      false 113/113
      true 0/113
  input(33) > lower limit  50%
      false 0/113
      true 113/113
  input(33) >= upper limit  50%
      false 113/113
      true 0/113
  input(34) > lower limit  50%
      false 0/113
      true 113/113
  input(34) >= upper limit  50%
      false 113/113
      true 0/113
  input(35) > lower limit  50%
      false 0/113
      true 113/113
  input(35) >= upper limit  50%
      false 113/113
      true 0/113
  input(36) > lower limit  50%
      false 0/113
      true 113/113
  input(36) >= upper limit  50%
      false 113/113
      true 0/113
  input(37) > lower limit  50%
      false 0/113
      true 113/113
  input(37) >= upper limit  50%
      false 113/113
      true 0/113
  input(38) > lower limit  50%
      false 0/113
      true 113/113
  input(38) >= upper limit  50%
      false 113/113
      true 0/113
  input(39) > lower limit  50%
      false 0/113
      true 113/113
  input(39) >= upper limit  50%
      false 113/113
      true 0/113
  input(40) > lower limit  50%
      false 0/113
      true 113/113
  input(40) >= upper limit  50%
      false 113/113
      true 0/113
  input(41) > lower limit  50%
      false 0/113
      true 113/113
  input(41) >= upper limit  50%
      false 113/113
      true 0/113
  input(42) > lower limit  50%
      false 0/113
      true 113/113
  input(42) >= upper limit  50%
      false 113/113
      true 0/113
  input(43) > lower limit  50%
      false 0/113
      true 113/113
  input(43) >= upper limit  50%
      false 113/113
      true 0/113
  input(44) > lower limit  50%
      false 0/113
      true 113/113
  input(44) >= upper limit  50%
      false 113/113
      true 0/113
  input(45) > lower limit  50%
      false 0/113
      true 113/113
  input(45) >= upper limit  50%
      false 113/113
      true 0/113
  input(46) > lower limit  50%
      false 0/113
      true 113/113
  input(46) >= upper limit  50%
      false 113/113
      true 0/113
  input(47) > lower limit  50%
      false 0/113
      true 113/113
  input(47) >= upper limit  50%
      false 113/113
      true 0/113
  input(48) > lower limit  50%
      false 0/113
      true 113/113
  input(48) >= upper limit  50%
      false 113/113
      true 0/113

   Full Coverage

Model Object Metric
Sum block "Add" Execution

79. SubSystem block "DebounceStartZero2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag
Child Systems: Compare To Zero,  FaultProcess,  HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 625
Condition NA 67% (386/576) condition outcomes
Decision NA 62% (771/1248) decision outcomes
Execution NA 100% (32/32) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 50% (48/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

80. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (48/96) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (48/96) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) == input2  113 
  input1(2) == input2  113 
  input1(3) == input2  113 
  input1(4) == input2  113 
  input1(5) == input2  113 
  input1(6) == input2  113 
  input1(7) == input2  113 
  input1(8) == input2  113 
  input1(9) == input2  113 
  input1(10) == input2  113 
  input1(11) == input2  113 
  input1(12) == input2  113 
  input1(13) == input2  113 
  input1(14) == input2  113 
  input1(15) == input2  113 
  input1(16) == input2  113 
  input1(17) == input2  113 
  input1(18) == input2  113 
  input1(19) == input2  113 
  input1(20) == input2  113 
  input1(21) == input2  113 
  input1(22) == input2  113 
  input1(23) == input2  113 
  input1(24) == input2  113 
  input1(25) == input2  113 
  input1(26) == input2  113 
  input1(27) == input2  113 
  input1(28) == input2  113 
  input1(29) == input2  113 
  input1(30) == input2  113 
  input1(31) == input2  113 
  input1(32) == input2  113 
  input1(33) == input2  113 
  input1(34) == input2  113 
  input1(35) == input2  113 
  input1(36) == input2  113 
  input1(37) == input2  113 
  input1(38) == input2  113 
  input1(39) == input2  113 
  input1(40) == input2  113 
  input1(41) == input2  113 
  input1(42) == input2  113 
  input1(43) == input2  113 
  input1(44) == input2  113 
  input1(45) == input2  113 
  input1(46) == input2  113 
  input1(47) == input2  113 
  input1(48) == input2  113 

81. SubSystem block "FaultProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2
Child Systems: Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 288
Condition NA 51% (97/192) condition outcomes
Decision NA 50% (290/576) decision outcomes
Execution NA 100% (14/14) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 50% (48/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 51% (49/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  100%
      false (output is from 3rd input port) 94/113
      true (output is from 1st input port) 19/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 50% (48/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (48/96) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) > input2 
113 
  input1(2) > input2 
113 
  input1(3) > input2 
113 
  input1(4) > input2 
113 
  input1(5) > input2 
113 
  input1(6) > input2 
113 
  input1(7) > input2 
113 
  input1(8) > input2 
113 
  input1(9) > input2 
113 
  input1(10) > input2 
113 
  input1(11) > input2 
113 
  input1(12) > input2 
113 
  input1(13) > input2 
113 
  input1(14) > input2 
113 
  input1(15) > input2 
113 
  input1(16) > input2 
113 
  input1(17) > input2 
113 
  input1(18) > input2 
113 
  input1(19) > input2 
113 
  input1(20) > input2 
113 
  input1(21) > input2 
113 
  input1(22) > input2 
113 
  input1(23) > input2 
113 
  input1(24) > input2 
113 
  input1(25) > input2 
113 
  input1(26) > input2 
113 
  input1(27) > input2 
113 
  input1(28) > input2 
113 
  input1(29) > input2 
113 
  input1(30) > input2 
113 
  input1(31) > input2 
113 
  input1(32) > input2 
113 
  input1(33) > input2 
113 
  input1(34) > input2 
113 
  input1(35) > input2 
113 
  input1(36) > input2 
113 
  input1(37) > input2 
113 
  input1(38) > input2 
113 
  input1(39) > input2 
113 
  input1(40) > input2 
113 
  input1(41) > input2 
113 
  input1(42) > input2 
113 
  input1(43) > input2 
113 
  input1(44) > input2 
113 
  input1(45) > input2 
113 
  input1(46) > input2 
113 
  input1(47) > input2 
113 
  input1(48) > input2 
113 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

82. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2/FaultProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 48
Condition NA 51% (49/96) condition outcomes
Decision NA 51% (49/96) decision outcomes
Execution NA 100% (4/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 51% (49/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  100%
      false (output is from 3rd input port) 77/113
      true (output is from 1st input port) 36/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 51% (49/96) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) >= input2  36  77 
  input1(2) >= input2 
113 
  input1(3) >= input2 
113 
  input1(4) >= input2 
113 
  input1(5) >= input2 
113 
  input1(6) >= input2 
113 
  input1(7) >= input2 
113 
  input1(8) >= input2 
113 
  input1(9) >= input2 
113 
  input1(10) >= input2 
113 
  input1(11) >= input2 
113 
  input1(12) >= input2 
113 
  input1(13) >= input2 
113 
  input1(14) >= input2 
113 
  input1(15) >= input2 
113 
  input1(16) >= input2 
113 
  input1(17) >= input2 
113 
  input1(18) >= input2 
113 
  input1(19) >= input2 
113 
  input1(20) >= input2 
113 
  input1(21) >= input2 
113 
  input1(22) >= input2 
113 
  input1(23) >= input2 
113 
  input1(24) >= input2 
113 
  input1(25) >= input2 
113 
  input1(26) >= input2 
113 
  input1(27) >= input2 
113 
  input1(28) >= input2 
113 
  input1(29) >= input2 
113 
  input1(30) >= input2 
113 
  input1(31) >= input2 
113 
  input1(32) >= input2 
113 
  input1(33) >= input2 
113 
  input1(34) >= input2 
113 
  input1(35) >= input2 
113 
  input1(36) >= input2 
113 
  input1(37) >= input2 
113 
  input1(38) >= input2 
113 
  input1(39) >= input2 
113 
  input1(40) >= input2 
113 
  input1(41) >= input2 
113 
  input1(42) >= input2 
113 
  input1(43) >= input2 
113 
  input1(44) >= input2 
113 
  input1(45) >= input2 
113 
  input1(46) >= input2 
113 
  input1(47) >= input2 
113 
  input1(48) >= input2 
113 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

83. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2/FaultProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Sum block "Add" Execution

84. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2/FaultProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 96
Decision NA 50% (96/192) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 96
Decision 50% (96/192) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input(1) > lower limit  50%
      false 0/113
      true 113/113
  input(1) >= upper limit  50%
      false 113/113
      true 0/113
  input(2) > lower limit  50%
      false 0/113
      true 113/113
  input(2) >= upper limit  50%
      false 113/113
      true 0/113
  input(3) > lower limit  50%
      false 0/113
      true 113/113
  input(3) >= upper limit  50%
      false 113/113
      true 0/113
  input(4) > lower limit  50%
      false 0/113
      true 113/113
  input(4) >= upper limit  50%
      false 113/113
      true 0/113
  input(5) > lower limit  50%
      false 0/113
      true 113/113
  input(5) >= upper limit  50%
      false 113/113
      true 0/113
  input(6) > lower limit  50%
      false 0/113
      true 113/113
  input(6) >= upper limit  50%
      false 113/113
      true 0/113
  input(7) > lower limit  50%
      false 0/113
      true 113/113
  input(7) >= upper limit  50%
      false 113/113
      true 0/113
  input(8) > lower limit  50%
      false 0/113
      true 113/113
  input(8) >= upper limit  50%
      false 113/113
      true 0/113
  input(9) > lower limit  50%
      false 0/113
      true 113/113
  input(9) >= upper limit  50%
      false 113/113
      true 0/113
  input(10) > lower limit  50%
      false 0/113
      true 113/113
  input(10) >= upper limit  50%
      false 113/113
      true 0/113
  input(11) > lower limit  50%
      false 0/113
      true 113/113
  input(11) >= upper limit  50%
      false 113/113
      true 0/113
  input(12) > lower limit  50%
      false 0/113
      true 113/113
  input(12) >= upper limit  50%
      false 113/113
      true 0/113
  input(13) > lower limit  50%
      false 0/113
      true 113/113
  input(13) >= upper limit  50%
      false 113/113
      true 0/113
  input(14) > lower limit  50%
      false 0/113
      true 113/113
  input(14) >= upper limit  50%
      false 113/113
      true 0/113
  input(15) > lower limit  50%
      false 0/113
      true 113/113
  input(15) >= upper limit  50%
      false 113/113
      true 0/113
  input(16) > lower limit  50%
      false 0/113
      true 113/113
  input(16) >= upper limit  50%
      false 113/113
      true 0/113
  input(17) > lower limit  50%
      false 0/113
      true 113/113
  input(17) >= upper limit  50%
      false 113/113
      true 0/113
  input(18) > lower limit  50%
      false 0/113
      true 113/113
  input(18) >= upper limit  50%
      false 113/113
      true 0/113
  input(19) > lower limit  50%
      false 0/113
      true 113/113
  input(19) >= upper limit  50%
      false 113/113
      true 0/113
  input(20) > lower limit  50%
      false 0/113
      true 113/113
  input(20) >= upper limit  50%
      false 113/113
      true 0/113
  input(21) > lower limit  50%
      false 0/113
      true 113/113
  input(21) >= upper limit  50%
      false 113/113
      true 0/113
  input(22) > lower limit  50%
      false 0/113
      true 113/113
  input(22) >= upper limit  50%
      false 113/113
      true 0/113
  input(23) > lower limit  50%
      false 0/113
      true 113/113
  input(23) >= upper limit  50%
      false 113/113
      true 0/113
  input(24) > lower limit  50%
      false 0/113
      true 113/113
  input(24) >= upper limit  50%
      false 113/113
      true 0/113
  input(25) > lower limit  50%
      false 0/113
      true 113/113
  input(25) >= upper limit  50%
      false 113/113
      true 0/113
  input(26) > lower limit  50%
      false 0/113
      true 113/113
  input(26) >= upper limit  50%
      false 113/113
      true 0/113
  input(27) > lower limit  50%
      false 0/113
      true 113/113
  input(27) >= upper limit  50%
      false 113/113
      true 0/113
  input(28) > lower limit  50%
      false 0/113
      true 113/113
  input(28) >= upper limit  50%
      false 113/113
      true 0/113
  input(29) > lower limit  50%
      false 0/113
      true 113/113
  input(29) >= upper limit  50%
      false 113/113
      true 0/113
  input(30) > lower limit  50%
      false 0/113
      true 113/113
  input(30) >= upper limit  50%
      false 113/113
      true 0/113
  input(31) > lower limit  50%
      false 0/113
      true 113/113
  input(31) >= upper limit  50%
      false 113/113
      true 0/113
  input(32) > lower limit  50%
      false 0/113
      true 113/113
  input(32) >= upper limit  50%
      false 113/113
      true 0/113
  input(33) > lower limit  50%
      false 0/113
      true 113/113
  input(33) >= upper limit  50%
      false 113/113
      true 0/113
  input(34) > lower limit  50%
      false 0/113
      true 113/113
  input(34) >= upper limit  50%
      false 113/113
      true 0/113
  input(35) > lower limit  50%
      false 0/113
      true 113/113
  input(35) >= upper limit  50%
      false 113/113
      true 0/113
  input(36) > lower limit  50%
      false 0/113
      true 113/113
  input(36) >= upper limit  50%
      false 113/113
      true 0/113
  input(37) > lower limit  50%
      false 0/113
      true 113/113
  input(37) >= upper limit  50%
      false 113/113
      true 0/113
  input(38) > lower limit  50%
      false 0/113
      true 113/113
  input(38) >= upper limit  50%
      false 113/113
      true 0/113
  input(39) > lower limit  50%
      false 0/113
      true 113/113
  input(39) >= upper limit  50%
      false 113/113
      true 0/113
  input(40) > lower limit  50%
      false 0/113
      true 113/113
  input(40) >= upper limit  50%
      false 113/113
      true 0/113
  input(41) > lower limit  50%
      false 0/113
      true 113/113
  input(41) >= upper limit  50%
      false 113/113
      true 0/113
  input(42) > lower limit  50%
      false 0/113
      true 113/113
  input(42) >= upper limit  50%
      false 113/113
      true 0/113
  input(43) > lower limit  50%
      false 0/113
      true 113/113
  input(43) >= upper limit  50%
      false 113/113
      true 0/113
  input(44) > lower limit  50%
      false 0/113
      true 113/113
  input(44) >= upper limit  50%
      false 113/113
      true 0/113
  input(45) > lower limit  50%
      false 0/113
      true 113/113
  input(45) >= upper limit  50%
      false 113/113
      true 0/113
  input(46) > lower limit  50%
      false 0/113
      true 113/113
  input(46) >= upper limit  50%
      false 113/113
      true 0/113
  input(47) > lower limit  50%
      false 0/113
      true 113/113
  input(47) >= upper limit  50%
      false 113/113
      true 0/113
  input(48) > lower limit  50%
      false 0/113
      true 113/113
  input(48) >= upper limit  50%
      false 113/113
      true 0/113

   Full Coverage

Model Object Metric
Sum block "Add" Execution

85. SubSystem block "HealProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2
Child Systems: Compare To Zero,  Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 288
Condition NA 84% (241/288) condition outcomes
Decision NA 75% (433/576) decision outcomes
Execution NA 100% (15/15) objective outcomes

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 51% (49/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  100%
      false (output is from 3rd input port) 19/113
      true (output is from 1st input port) 94/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
Switch block "Switch2" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay1" Execution
UnitDelay block "Unit Delay2" Execution

86. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 51% (49/96) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2/HealProcess/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 51% (49/96) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) == input2  94  19 
  input1(2) == input2  113 
  input1(3) == input2  113 
  input1(4) == input2  113 
  input1(5) == input2  113 
  input1(6) == input2  113 
  input1(7) == input2  113 
  input1(8) == input2  113 
  input1(9) == input2  113 
  input1(10) == input2  113 
  input1(11) == input2  113 
  input1(12) == input2  113 
  input1(13) == input2  113 
  input1(14) == input2  113 
  input1(15) == input2  113 
  input1(16) == input2  113 
  input1(17) == input2  113 
  input1(18) == input2  113 
  input1(19) == input2  113 
  input1(20) == input2  113 
  input1(21) == input2  113 
  input1(22) == input2  113 
  input1(23) == input2  113 
  input1(24) == input2  113 
  input1(25) == input2  113 
  input1(26) == input2  113 
  input1(27) == input2  113 
  input1(28) == input2  113 
  input1(29) == input2  113 
  input1(30) == input2  113 
  input1(31) == input2  113 
  input1(32) == input2  113 
  input1(33) == input2  113 
  input1(34) == input2  113 
  input1(35) == input2  113 
  input1(36) == input2  113 
  input1(37) == input2  113 
  input1(38) == input2  113 
  input1(39) == input2  113 
  input1(40) == input2  113 
  input1(41) == input2  113 
  input1(42) == input2  113 
  input1(43) == input2  113 
  input1(44) == input2  113 
  input1(45) == input2  113 
  input1(46) == input2  113 
  input1(47) == input2  113 
  input1(48) == input2  113 

87. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2/HealProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 48
Condition NA 100% (96/96) condition outcomes
Decision NA 100% (96/96) decision outcomes
Execution NA 100% (4/4) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution

88. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2/HealProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Sum block "Add" Execution

89. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 96
Decision NA 50% (96/192) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/DebounceStartZero2/HealProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 96
Decision 50% (96/192) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input(1) > lower limit  50%
      false 0/113
      true 113/113
  input(1) >= upper limit  50%
      false 113/113
      true 0/113
  input(2) > lower limit  50%
      false 0/113
      true 113/113
  input(2) >= upper limit  50%
      false 113/113
      true 0/113
  input(3) > lower limit  50%
      false 0/113
      true 113/113
  input(3) >= upper limit  50%
      false 113/113
      true 0/113
  input(4) > lower limit  50%
      false 0/113
      true 113/113
  input(4) >= upper limit  50%
      false 113/113
      true 0/113
  input(5) > lower limit  50%
      false 0/113
      true 113/113
  input(5) >= upper limit  50%
      false 113/113
      true 0/113
  input(6) > lower limit  50%
      false 0/113
      true 113/113
  input(6) >= upper limit  50%
      false 113/113
      true 0/113
  input(7) > lower limit  50%
      false 0/113
      true 113/113
  input(7) >= upper limit  50%
      false 113/113
      true 0/113
  input(8) > lower limit  50%
      false 0/113
      true 113/113
  input(8) >= upper limit  50%
      false 113/113
      true 0/113
  input(9) > lower limit  50%
      false 0/113
      true 113/113
  input(9) >= upper limit  50%
      false 113/113
      true 0/113
  input(10) > lower limit  50%
      false 0/113
      true 113/113
  input(10) >= upper limit  50%
      false 113/113
      true 0/113
  input(11) > lower limit  50%
      false 0/113
      true 113/113
  input(11) >= upper limit  50%
      false 113/113
      true 0/113
  input(12) > lower limit  50%
      false 0/113
      true 113/113
  input(12) >= upper limit  50%
      false 113/113
      true 0/113
  input(13) > lower limit  50%
      false 0/113
      true 113/113
  input(13) >= upper limit  50%
      false 113/113
      true 0/113
  input(14) > lower limit  50%
      false 0/113
      true 113/113
  input(14) >= upper limit  50%
      false 113/113
      true 0/113
  input(15) > lower limit  50%
      false 0/113
      true 113/113
  input(15) >= upper limit  50%
      false 113/113
      true 0/113
  input(16) > lower limit  50%
      false 0/113
      true 113/113
  input(16) >= upper limit  50%
      false 113/113
      true 0/113
  input(17) > lower limit  50%
      false 0/113
      true 113/113
  input(17) >= upper limit  50%
      false 113/113
      true 0/113
  input(18) > lower limit  50%
      false 0/113
      true 113/113
  input(18) >= upper limit  50%
      false 113/113
      true 0/113
  input(19) > lower limit  50%
      false 0/113
      true 113/113
  input(19) >= upper limit  50%
      false 113/113
      true 0/113
  input(20) > lower limit  50%
      false 0/113
      true 113/113
  input(20) >= upper limit  50%
      false 113/113
      true 0/113
  input(21) > lower limit  50%
      false 0/113
      true 113/113
  input(21) >= upper limit  50%
      false 113/113
      true 0/113
  input(22) > lower limit  50%
      false 0/113
      true 113/113
  input(22) >= upper limit  50%
      false 113/113
      true 0/113
  input(23) > lower limit  50%
      false 0/113
      true 113/113
  input(23) >= upper limit  50%
      false 113/113
      true 0/113
  input(24) > lower limit  50%
      false 0/113
      true 113/113
  input(24) >= upper limit  50%
      false 113/113
      true 0/113
  input(25) > lower limit  50%
      false 0/113
      true 113/113
  input(25) >= upper limit  50%
      false 113/113
      true 0/113
  input(26) > lower limit  50%
      false 0/113
      true 113/113
  input(26) >= upper limit  50%
      false 113/113
      true 0/113
  input(27) > lower limit  50%
      false 0/113
      true 113/113
  input(27) >= upper limit  50%
      false 113/113
      true 0/113
  input(28) > lower limit  50%
      false 0/113
      true 113/113
  input(28) >= upper limit  50%
      false 113/113
      true 0/113
  input(29) > lower limit  50%
      false 0/113
      true 113/113
  input(29) >= upper limit  50%
      false 113/113
      true 0/113
  input(30) > lower limit  50%
      false 0/113
      true 113/113
  input(30) >= upper limit  50%
      false 113/113
      true 0/113
  input(31) > lower limit  50%
      false 0/113
      true 113/113
  input(31) >= upper limit  50%
      false 113/113
      true 0/113
  input(32) > lower limit  50%
      false 0/113
      true 113/113
  input(32) >= upper limit  50%
      false 113/113
      true 0/113
  input(33) > lower limit  50%
      false 0/113
      true 113/113
  input(33) >= upper limit  50%
      false 113/113
      true 0/113
  input(34) > lower limit  50%
      false 0/113
      true 113/113
  input(34) >= upper limit  50%
      false 113/113
      true 0/113
  input(35) > lower limit  50%
      false 0/113
      true 113/113
  input(35) >= upper limit  50%
      false 113/113
      true 0/113
  input(36) > lower limit  50%
      false 0/113
      true 113/113
  input(36) >= upper limit  50%
      false 113/113
      true 0/113
  input(37) > lower limit  50%
      false 0/113
      true 113/113
  input(37) >= upper limit  50%
      false 113/113
      true 0/113
  input(38) > lower limit  50%
      false 0/113
      true 113/113
  input(38) >= upper limit  50%
      false 113/113
      true 0/113
  input(39) > lower limit  50%
      false 0/113
      true 113/113
  input(39) >= upper limit  50%
      false 113/113
      true 0/113
  input(40) > lower limit  50%
      false 0/113
      true 113/113
  input(40) >= upper limit  50%
      false 113/113
      true 0/113
  input(41) > lower limit  50%
      false 0/113
      true 113/113
  input(41) >= upper limit  50%
      false 113/113
      true 0/113
  input(42) > lower limit  50%
      false 0/113
      true 113/113
  input(42) >= upper limit  50%
      false 113/113
      true 0/113
  input(43) > lower limit  50%
      false 0/113
      true 113/113
  input(43) >= upper limit  50%
      false 113/113
      true 0/113
  input(44) > lower limit  50%
      false 0/113
      true 113/113
  input(44) >= upper limit  50%
      false 113/113
      true 0/113
  input(45) > lower limit  50%
      false 0/113
      true 113/113
  input(45) >= upper limit  50%
      false 113/113
      true 0/113
  input(46) > lower limit  50%
      false 0/113
      true 113/113
  input(46) >= upper limit  50%
      false 113/113
      true 0/113
  input(47) > lower limit  50%
      false 0/113
      true 113/113
  input(47) >= upper limit  50%
      false 113/113
      true 0/113
  input(48) > lower limit  50%
      false 0/113
      true 113/113
  input(48) >= upper limit  50%
      false 113/113
      true 0/113

   Full Coverage

Model Object Metric
Sum block "Add" Execution

90. SubSystem block "EdgeRising"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 1
Condition NA 50% (3/6) condition outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 100% (3/3) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/EdgeRising
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
113 
  input port 2  113 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
C1 && ~C2
      C1 (AND In1) (TF) FF
      C2 (OR1 In1) (TF) (TT)


   Logic block "OR1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/EdgeRising
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see AND
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
113 

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

91. SubSystem block "EdgeRising2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 1
Condition NA 50% (3/6) condition outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 100% (3/3) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/EdgeRising2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
113 
  input port 2  113 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
C1 && ~C2
      C1 (AND In1) (TF) FF
      C2 (OR1 In1) (TF) (TT)


   Logic block "OR1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag/EdgeRising2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see AND
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
113 

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

92. SubSystem block "MaxBusbarTempGrad_ForIterator1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Full Coverage

Model Object Metric
ForIterator block "MaxCellTempNumbIterator" Decision
Sum block "Sum1" Execution
Selector block "Selector1" Execution
UnitDelay block "Unit Delay9" Execution

93. SubSystem block "MaxBusbarTempGrad_ForIterator2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/BusbarTempGradDiag

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Full Coverage

Model Object Metric
ForIterator block "MaxCellTempNumbIterator" Decision
Sum block "Sum1" Execution
Selector block "Selector1" Execution
UnitDelay block "Unit Delay9" Execution

94. SubSystem block "CalcBusbarTempGrad"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag
Child Systems: Unit Delay External IC,  Unit Delay External IC1,  Unit Delay External IC2,  Unit Delay External IC3,  Unit Delay External IC4

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 10
Decision NA 100% (10/10) decision outcomes
Execution NA 100% (16/16) objective outcomes

   Full Coverage

Model Object Metric
Sum block "Sum1" Execution

95. SubSystem block "Unit Delay External IC"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/CalcBusbarTempGrad

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

96. SubSystem block "Unit Delay External IC1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/CalcBusbarTempGrad

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

97. SubSystem block "Unit Delay External IC2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/CalcBusbarTempGrad

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

98. SubSystem block "Unit Delay External IC3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/CalcBusbarTempGrad

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

99. SubSystem block "Unit Delay External IC4"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayBusbarTempCheck/BusbarTempGradDiag/CalcBusbarTempGrad

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

100. SubSystem block "RunawayCellTempCheck"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck
Child Systems: BMSDelay1,  CellMaxTempDiag,  CellTempDiffDiag,  CellTempGradDiag,  EdgeRising,  EdgeRising1,  HDP_GbHDP_PackCrntSelfChck_flg1,  MaxTempDiag1,  TempGradCalc

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1374
Condition NA 63% (947/1506) condition outcomes
Decision NA 60% (1622/2690) decision outcomes
MCDC NA 0% (0/21) conditions reversed the outcome
Execution NA 84% (331/392) objective outcomes

   Logic block "Logical1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  1601 
  input port 2 
1601 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 TF (FF)
      input port 2 (FT) (FF)


   Logic block "Logical5"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (4/8) condition outcomes
MCDC see Logical1
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2 
1601 
  input port 3 
1601 
  input port 4  1601 

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  1601 

   Full Coverage

Model Object Metric
Logic block "Logical6" Condition, Execution
Constant block "Constant13" Execution
Constant block "Constant16" Execution
UnitDelay block "Unit Delay9" Execution

101. SubSystem block "BMSDelay1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck
Child Systems: Unit Delay Resettable

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 4
Condition NA 100% (4/4) condition outcomes
Decision NA 100% (6/6) decision outcomes
Execution NA 100% (7/7) objective outcomes

   Full Coverage

Model Object Metric
Logic block "Logical Operator" Condition, Execution
Switch block "Switch" Decision, Execution
Sum block "Add" Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution

102. SubSystem block "Unit Delay Resettable"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/BMSDelay1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 100% (4/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution
Switch block "Reset" Decision, Execution

103. SubSystem block "CellMaxTempDiag"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck
Child Systems: DebounceStartZero,  DebounceStartZero1,  DebounceStartZero2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 42
Condition NA 50% (23/46) condition outcomes
Decision NA 38% (30/78) decision outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 82% (95/116) objective outcomes

   Logic block "Logical1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2 
1601 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TF) FF
      input port 2 (FT) FF


   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
1601 

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 
1601 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant1" Execution
Constant block "Constant10" Execution
Constant block "Constant11" Execution
Constant block "Constant12" Execution
Constant block "Constant13" Execution
Constant block "Constant14" Execution
Constant block "Constant15" Execution
Constant block "Constant16" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution
Constant block "Constant6" Execution
Constant block "Constant7" Execution
Constant block "Constant8" Execution
Constant block "Constant9" Execution

104. SubSystem block "DebounceStartZero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag
Child Systems: Compare To Zero,  FaultProcess,  HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 14
Condition NA 50% (6/12) condition outcomes
Decision NA 38% (10/26) decision outcomes
Execution NA 78% (25/32) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

105. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (1/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  1601 

106. SubSystem block "FaultProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero
Child Systems: Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 50% (2/4) condition outcomes
Decision NA 33% (4/12) decision outcomes
Execution NA 79% (11/14) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

107. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/FaultProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 50% (1/2) condition outcomes
Decision NA 50% (1/2) decision outcomes
Execution NA 75% (3/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

108. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/FaultProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/FaultProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

109. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/FaultProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 0% (0/4) decision outcomes
Execution NA 0% (0/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 0% (0/4) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  input > lower limit  0%
      false --
      true --
  input >= upper limit  0%
      false --
      true --

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

110. SubSystem block "HealProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero
Child Systems: Compare To Zero,  Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 50% (3/6) condition outcomes
Decision NA 42% (5/12) decision outcomes
Execution NA 73% (11/15) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
Switch block "Switch2" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay1" Execution
UnitDelay block "Unit Delay2" Execution

111. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (1/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/HealProcess/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  1601 

112. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/HealProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 0% (0/2) condition outcomes
Decision NA 0% (0/2) decision outcomes
Execution NA 25% (1/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/HealProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/HealProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 0% (0/2) condition outcomes
Execution 0% (0/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

113. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/HealProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/HealProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

114. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 50% (2/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero/HealProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 50% (2/4) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input > lower limit  50%
      false 0/1601
      true 1601/1601
  input >= upper limit  50%
      false 1601/1601
      true 0/1601

   Full Coverage

Model Object Metric
Sum block "Add" Execution

115. SubSystem block "DebounceStartZero1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag
Child Systems: Compare To Zero,  FaultProcess,  HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 14
Condition NA 50% (6/12) condition outcomes
Decision NA 38% (10/26) decision outcomes
Execution NA 78% (25/32) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

116. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (1/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  1601 

117. SubSystem block "FaultProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1
Child Systems: Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 50% (2/4) condition outcomes
Decision NA 33% (4/12) decision outcomes
Execution NA 79% (11/14) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

118. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/FaultProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 50% (1/2) condition outcomes
Decision NA 50% (1/2) decision outcomes
Execution NA 75% (3/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

119. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/FaultProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/FaultProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

120. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/FaultProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 0% (0/4) decision outcomes
Execution NA 0% (0/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 0% (0/4) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  input > lower limit  0%
      false --
      true --
  input >= upper limit  0%
      false --
      true --

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

121. SubSystem block "HealProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1
Child Systems: Compare To Zero,  Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 50% (3/6) condition outcomes
Decision NA 42% (5/12) decision outcomes
Execution NA 73% (11/15) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
Switch block "Switch2" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay1" Execution
UnitDelay block "Unit Delay2" Execution

122. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (1/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/HealProcess/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  1601 

123. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/HealProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 0% (0/2) condition outcomes
Decision NA 0% (0/2) decision outcomes
Execution NA 25% (1/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/HealProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/HealProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 0% (0/2) condition outcomes
Execution 0% (0/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

124. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/HealProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/HealProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

125. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 50% (2/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero1/HealProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 50% (2/4) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input > lower limit  50%
      false 0/1601
      true 1601/1601
  input >= upper limit  50%
      false 1601/1601
      true 0/1601

   Full Coverage

Model Object Metric
Sum block "Add" Execution

126. SubSystem block "DebounceStartZero2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag
Child Systems: Compare To Zero,  FaultProcess,  HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 14
Condition NA 50% (6/12) condition outcomes
Decision NA 38% (10/26) decision outcomes
Execution NA 78% (25/32) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

127. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (1/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  1601 

128. SubSystem block "FaultProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2
Child Systems: Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 50% (2/4) condition outcomes
Decision NA 33% (4/12) decision outcomes
Execution NA 79% (11/14) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

129. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/FaultProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 50% (1/2) condition outcomes
Decision NA 50% (1/2) decision outcomes
Execution NA 75% (3/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

130. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/FaultProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/FaultProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

131. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/FaultProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 0% (0/4) decision outcomes
Execution NA 0% (0/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 0% (0/4) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  input > lower limit  0%
      false --
      true --
  input >= upper limit  0%
      false --
      true --

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

132. SubSystem block "HealProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2
Child Systems: Compare To Zero,  Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 50% (3/6) condition outcomes
Decision NA 42% (5/12) decision outcomes
Execution NA 73% (11/15) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
Switch block "Switch2" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay1" Execution
UnitDelay block "Unit Delay2" Execution

133. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (1/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/HealProcess/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  1601 

134. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/HealProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 0% (0/2) condition outcomes
Decision NA 0% (0/2) decision outcomes
Execution NA 25% (1/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/HealProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/HealProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 0% (0/2) condition outcomes
Execution 0% (0/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

135. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/HealProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/HealProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

136. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 50% (2/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellMaxTempDiag/DebounceStartZero2/HealProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 50% (2/4) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input > lower limit  50%
      false 0/1601
      true 1601/1601
  input >= upper limit  50%
      false 1601/1601
      true 0/1601

   Full Coverage

Model Object Metric
Sum block "Add" Execution

137. SubSystem block "CellTempDiffDiag"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck
Child Systems: DebounceStartZero1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 14
Condition NA 50% (7/14) condition outcomes
Decision NA 38% (10/26) decision outcomes
Execution NA 82% (32/39) objective outcomes

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
1601 

   Full Coverage

Model Object Metric
Sum block "Sum1" Execution
Constant block "Constant1" Execution
Constant block "Constant12" Execution
Constant block "Constant15" Execution
Constant block "Constant17" Execution
Constant block "Constant2" Execution

138. SubSystem block "DebounceStartZero1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag
Child Systems: Compare To Zero,  FaultProcess,  HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 14
Condition NA 50% (6/12) condition outcomes
Decision NA 38% (10/26) decision outcomes
Execution NA 78% (25/32) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

139. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (1/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  1601 

140. SubSystem block "FaultProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1
Child Systems: Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 50% (2/4) condition outcomes
Decision NA 33% (4/12) decision outcomes
Execution NA 79% (11/14) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

141. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/FaultProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 50% (1/2) condition outcomes
Decision NA 50% (1/2) decision outcomes
Execution NA 75% (3/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

142. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/FaultProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/FaultProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

143. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/FaultProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 0% (0/4) decision outcomes
Execution NA 0% (0/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 0% (0/4) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  input > lower limit  0%
      false --
      true --
  input >= upper limit  0%
      false --
      true --

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

144. SubSystem block "HealProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1
Child Systems: Compare To Zero,  Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 50% (3/6) condition outcomes
Decision NA 42% (5/12) decision outcomes
Execution NA 73% (11/15) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
Switch block "Switch2" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay1" Execution
UnitDelay block "Unit Delay2" Execution

145. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (1/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/HealProcess/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  1601 

146. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/HealProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 0% (0/2) condition outcomes
Decision NA 0% (0/2) decision outcomes
Execution NA 25% (1/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/HealProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/HealProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 0% (0/2) condition outcomes
Execution 0% (0/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

147. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/HealProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/HealProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

148. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 50% (2/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempDiffDiag/DebounceStartZero1/HealProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 50% (2/4) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input > lower limit  50%
      false 0/1601
      true 1601/1601
  input >= upper limit  50%
      false 1601/1601
      true 0/1601

   Full Coverage

Model Object Metric
Sum block "Add" Execution

149. SubSystem block "CellTempGradDiag"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck
Child Systems: BMSDelay,  CalcTempGrad,  CellTempGradDiag

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 2 1292
Condition NA 64% (898/1410) condition outcomes
Decision 100% (2/2) decision outcomes 62% (1573/2554) decision outcomes
MCDC NA 0% (0/13) conditions reversed the outcome
Execution NA 95% (179/188) objective outcomes

  Decisions analyzed
  enable logical value  100%
      false 1468/1601
      true 133/1601

   Full Coverage

Model Object Metric
Constant block "Constant1" Execution
Constant block "Constant13" Execution
Constant block "Constant4" Execution

150. SubSystem block "BMSDelay"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag
Child Systems: Unit Delay Resettable

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 4
Condition NA 75% (3/4) condition outcomes
Decision NA 83% (5/6) decision outcomes
Execution NA 100% (7/7) objective outcomes

   Logic block "Logical Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/BMSDelay
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
Sum block "Add" Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution

151. SubSystem block "Unit Delay Resettable"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/BMSDelay

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 75% (3/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Switch block "Reset"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/BMSDelay/Unit Delay Resettable
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 133/133
      true (output is from 1st input port) 0/133

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution

152. SubSystem block "CalcTempGrad"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag
Child Systems: Unit Delay External IC,  Unit Delay External IC1,  Unit Delay External IC2,  Unit Delay External IC3,  Unit Delay External IC4

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 10
Decision NA 100% (10/10) decision outcomes
Execution NA 100% (16/16) objective outcomes

   Full Coverage

Model Object Metric
Sum block "Sum1" Execution

153. SubSystem block "Unit Delay External IC"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CalcTempGrad

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

154. SubSystem block "Unit Delay External IC1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CalcTempGrad

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

155. SubSystem block "Unit Delay External IC2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CalcTempGrad

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

156. SubSystem block "Unit Delay External IC3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CalcTempGrad

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

157. SubSystem block "Unit Delay External IC4"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CalcTempGrad

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

158. SubSystem block "CellTempGradDiag"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag
Child Systems: Counter Reset Enabled ,  Counter Reset Enabled 1,  DebounceStartZero,  DebounceStartZero1,  DebounceStartZero2,  EdgeRising,  EdgeRising2,  MaxCellTempGrad_ForIterator1,  MaxCellTempGrad_ForIterator2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 2 1276
Condition NA 64% (895/1406) condition outcomes
Decision 100% (2/2) decision outcomes 61% (1556/2536) decision outcomes
MCDC NA 0% (0/13) conditions reversed the outcome
Execution NA 94% (153/162) objective outcomes

  Decisions analyzed
  enable logical value  100%
      false 20/133
      true 113/133

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical1
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
113 
  input port 2 
113 

   Logic block "AND1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical3
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
113 
  input port 2 
113 

   Logic block "AND2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
113 
  input port 2 
113 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
(C1 && C2) || C3
      C1 (Logical5 In1) (TTF) (FTF)
      C2 (Logical5 In2) (TTF) (TFF)
      C3 (AND2 In2) (FFT) FFF


   Logic block "Logical1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
113 
  input port 2  113 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 3 blocks
Decision/Condition True Out False Out
(C1 || C2) && ~C3
      C1 (AND In1) (TFF) FFF
      C2 (AND In2) (FTF) FFF
      C3 (Logical2 In1) (TTF) (TTT)


   Logic block "Logical2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see Logical1
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
113 

   Logic block "Logical3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
113 
  input port 2  113 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 3 blocks
Decision/Condition True Out False Out
(C1 || C2) && ~C3
      C1 (AND1 In1) (TFF) FFF
      C2 (AND1 In2) (FTF) FFF
      C3 (Logical4 In1) (TTF) (TTT)


   Logic block "Logical4"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see Logical3
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
113 

   Logic block "Logical5"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see AND2
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
113 
  input port 2 
113 

   RelationalOperator block "Comparison"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (48/96) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) >= input2 
113 
  input1(2) >= input2 
113 
  input1(3) >= input2 
113 
  input1(4) >= input2 
113 
  input1(5) >= input2 
113 
  input1(6) >= input2 
113 
  input1(7) >= input2 
113 
  input1(8) >= input2 
113 
  input1(9) >= input2 
113 
  input1(10) >= input2 
113 
  input1(11) >= input2 
113 
  input1(12) >= input2 
113 
  input1(13) >= input2 
113 
  input1(14) >= input2 
113 
  input1(15) >= input2 
113 
  input1(16) >= input2 
113 
  input1(17) >= input2 
113 
  input1(18) >= input2 
113 
  input1(19) >= input2 
113 
  input1(20) >= input2 
113 
  input1(21) >= input2 
113 
  input1(22) >= input2 
113 
  input1(23) >= input2 
113 
  input1(24) >= input2 
113 
  input1(25) >= input2 
113 
  input1(26) >= input2 
113 
  input1(27) >= input2 
113 
  input1(28) >= input2 
113 
  input1(29) >= input2 
113 
  input1(30) >= input2 
113 
  input1(31) >= input2 
113 
  input1(32) >= input2 
113 
  input1(33) >= input2 
113 
  input1(34) >= input2 
113 
  input1(35) >= input2 
113 
  input1(36) >= input2 
113 
  input1(37) >= input2 
113 
  input1(38) >= input2 
113 
  input1(39) >= input2 
113 
  input1(40) >= input2 
113 
  input1(41) >= input2 
113 
  input1(42) >= input2 
113 
  input1(43) >= input2 
113 
  input1(44) >= input2 
113 
  input1(45) >= input2 
113 
  input1(46) >= input2 
113 
  input1(47) >= input2 
113 
  input1(48) >= input2 
113 

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
113 

   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
113 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (48/96) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) >= input2 
113 
  input1(2) >= input2 
113 
  input1(3) >= input2 
113 
  input1(4) >= input2 
113 
  input1(5) >= input2 
113 
  input1(6) >= input2 
113 
  input1(7) >= input2 
113 
  input1(8) >= input2 
113 
  input1(9) >= input2 
113 
  input1(10) >= input2 
113 
  input1(11) >= input2 
113 
  input1(12) >= input2 
113 
  input1(13) >= input2 
113 
  input1(14) >= input2 
113 
  input1(15) >= input2 
113 
  input1(16) >= input2 
113 
  input1(17) >= input2 
113 
  input1(18) >= input2 
113 
  input1(19) >= input2 
113 
  input1(20) >= input2 
113 
  input1(21) >= input2 
113 
  input1(22) >= input2 
113 
  input1(23) >= input2 
113 
  input1(24) >= input2 
113 
  input1(25) >= input2 
113 
  input1(26) >= input2 
113 
  input1(27) >= input2 
113 
  input1(28) >= input2 
113 
  input1(29) >= input2 
113 
  input1(30) >= input2 
113 
  input1(31) >= input2 
113 
  input1(32) >= input2 
113 
  input1(33) >= input2 
113 
  input1(34) >= input2 
113 
  input1(35) >= input2 
113 
  input1(36) >= input2 
113 
  input1(37) >= input2 
113 
  input1(38) >= input2 
113 
  input1(39) >= input2 
113 
  input1(40) >= input2 
113 
  input1(41) >= input2 
113 
  input1(42) >= input2 
113 
  input1(43) >= input2 
113 
  input1(44) >= input2 
113 
  input1(45) >= input2 
113 
  input1(46) >= input2 
113 
  input1(47) >= input2 
113 
  input1(48) >= input2 
113 

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
113 

   RelationalOperator block "Comparison5"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
113 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
113 

   Full Coverage

Model Object Metric
Product block "Product" Execution
Product block "Product1" Execution
Constant block "Constant10" Execution
Constant block "Constant11" Execution
Constant block "Constant12" Execution
Constant block "Constant14" Execution
Constant block "Constant15" Execution
Constant block "Constant16" Execution
Constant block "Constant17" Execution
Constant block "Constant18" Execution
Constant block "Constant19" Execution
Constant block "Constant2" Execution
Constant block "Constant20" Execution
Constant block "Constant21" Execution
Constant block "Constant22" Execution
Constant block "Constant23" Execution
Constant block "Constant24" Execution
Constant block "Constant3" Execution
Constant block "Constant5" Execution
Constant block "Constant6" Execution
Constant block "Constant7" Execution
Constant block "Constant8" Execution
Constant block "Constant9" Execution
UnitDelay block "Unit Delay5" Execution
UnitDelay block "Unit Delay6" Execution
UnitDelay block "Unit Delay7" Execution
UnitDelay block "Unit Delay8" Execution

159. SubSystem block "Counter Reset Enabled "

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 3
Decision NA 50% (2/4) decision outcomes
Execution NA 83% (5/6) objective outcomes

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/Counter Reset Enabled
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/Counter Reset Enabled
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   Sum block "Subtraction"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/Counter Reset Enabled
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant Value1" Execution
Constant block "Constant Value2" Execution
UnitDelay block "Unit Delay" Execution

160. SubSystem block "Counter Reset Enabled 1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 3
Decision NA 50% (2/4) decision outcomes
Execution NA 83% (5/6) objective outcomes

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/Counter Reset Enabled 1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/Counter Reset Enabled 1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   Sum block "Subtraction"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/Counter Reset Enabled 1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant Value1" Execution
Constant block "Constant Value2" Execution
UnitDelay block "Unit Delay" Execution

161. SubSystem block "DebounceStartZero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag
Child Systems: Compare To Zero,  FaultProcess,  HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 14
Condition NA 50% (6/12) condition outcomes
Decision NA 38% (10/26) decision outcomes
Execution NA 78% (25/32) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

162. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (1/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  113 

163. SubSystem block "FaultProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero
Child Systems: Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 50% (2/4) condition outcomes
Decision NA 33% (4/12) decision outcomes
Execution NA 79% (11/14) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
113 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

164. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/FaultProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 50% (1/2) condition outcomes
Decision NA 50% (1/2) decision outcomes
Execution NA 75% (3/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
113 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

165. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/FaultProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/FaultProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

166. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/FaultProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 0% (0/4) decision outcomes
Execution NA 0% (0/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 0% (0/4) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  input > lower limit  0%
      false --
      true --
  input >= upper limit  0%
      false --
      true --

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

167. SubSystem block "HealProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero
Child Systems: Compare To Zero,  Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 50% (3/6) condition outcomes
Decision NA 42% (5/12) decision outcomes
Execution NA 73% (11/15) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113

   Full Coverage

Model Object Metric
Switch block "Switch2" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay1" Execution
UnitDelay block "Unit Delay2" Execution

168. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (1/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/HealProcess/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  113 

169. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/HealProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 0% (0/2) condition outcomes
Decision NA 0% (0/2) decision outcomes
Execution NA 25% (1/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/HealProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/HealProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 0% (0/2) condition outcomes
Execution 0% (0/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

170. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/HealProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/HealProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

171. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 50% (2/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero/HealProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 50% (2/4) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input > lower limit  50%
      false 0/113
      true 113/113
  input >= upper limit  50%
      false 113/113
      true 0/113

   Full Coverage

Model Object Metric
Sum block "Add" Execution

172. SubSystem block "DebounceStartZero1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag
Child Systems: Compare To Zero,  FaultProcess,  HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 625
Condition NA 67% (384/576) condition outcomes
Decision NA 62% (768/1248) decision outcomes
Execution NA 100% (32/32) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 50% (48/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

173. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (48/96) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (48/96) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) == input2  113 
  input1(2) == input2  113 
  input1(3) == input2  113 
  input1(4) == input2  113 
  input1(5) == input2  113 
  input1(6) == input2  113 
  input1(7) == input2  113 
  input1(8) == input2  113 
  input1(9) == input2  113 
  input1(10) == input2  113 
  input1(11) == input2  113 
  input1(12) == input2  113 
  input1(13) == input2  113 
  input1(14) == input2  113 
  input1(15) == input2  113 
  input1(16) == input2  113 
  input1(17) == input2  113 
  input1(18) == input2  113 
  input1(19) == input2  113 
  input1(20) == input2  113 
  input1(21) == input2  113 
  input1(22) == input2  113 
  input1(23) == input2  113 
  input1(24) == input2  113 
  input1(25) == input2  113 
  input1(26) == input2  113 
  input1(27) == input2  113 
  input1(28) == input2  113 
  input1(29) == input2  113 
  input1(30) == input2  113 
  input1(31) == input2  113 
  input1(32) == input2  113 
  input1(33) == input2  113 
  input1(34) == input2  113 
  input1(35) == input2  113 
  input1(36) == input2  113 
  input1(37) == input2  113 
  input1(38) == input2  113 
  input1(39) == input2  113 
  input1(40) == input2  113 
  input1(41) == input2  113 
  input1(42) == input2  113 
  input1(43) == input2  113 
  input1(44) == input2  113 
  input1(45) == input2  113 
  input1(46) == input2  113 
  input1(47) == input2  113 
  input1(48) == input2  113 

174. SubSystem block "FaultProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1
Child Systems: Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 288
Condition NA 50% (96/192) condition outcomes
Decision NA 50% (288/576) decision outcomes
Execution NA 100% (14/14) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 50% (48/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 50% (48/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 50% (48/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (48/96) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) > input2 
113 
  input1(2) > input2 
113 
  input1(3) > input2 
113 
  input1(4) > input2 
113 
  input1(5) > input2 
113 
  input1(6) > input2 
113 
  input1(7) > input2 
113 
  input1(8) > input2 
113 
  input1(9) > input2 
113 
  input1(10) > input2 
113 
  input1(11) > input2 
113 
  input1(12) > input2 
113 
  input1(13) > input2 
113 
  input1(14) > input2 
113 
  input1(15) > input2 
113 
  input1(16) > input2 
113 
  input1(17) > input2 
113 
  input1(18) > input2 
113 
  input1(19) > input2 
113 
  input1(20) > input2 
113 
  input1(21) > input2 
113 
  input1(22) > input2 
113 
  input1(23) > input2 
113 
  input1(24) > input2 
113 
  input1(25) > input2 
113 
  input1(26) > input2 
113 
  input1(27) > input2 
113 
  input1(28) > input2 
113 
  input1(29) > input2 
113 
  input1(30) > input2 
113 
  input1(31) > input2 
113 
  input1(32) > input2 
113 
  input1(33) > input2 
113 
  input1(34) > input2 
113 
  input1(35) > input2 
113 
  input1(36) > input2 
113 
  input1(37) > input2 
113 
  input1(38) > input2 
113 
  input1(39) > input2 
113 
  input1(40) > input2 
113 
  input1(41) > input2 
113 
  input1(42) > input2 
113 
  input1(43) > input2 
113 
  input1(44) > input2 
113 
  input1(45) > input2 
113 
  input1(46) > input2 
113 
  input1(47) > input2 
113 
  input1(48) > input2 
113 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

175. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1/FaultProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 48
Condition NA 50% (48/96) condition outcomes
Decision NA 50% (48/96) decision outcomes
Execution NA 100% (4/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 50% (48/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (48/96) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) >= input2 
113 
  input1(2) >= input2 
113 
  input1(3) >= input2 
113 
  input1(4) >= input2 
113 
  input1(5) >= input2 
113 
  input1(6) >= input2 
113 
  input1(7) >= input2 
113 
  input1(8) >= input2 
113 
  input1(9) >= input2 
113 
  input1(10) >= input2 
113 
  input1(11) >= input2 
113 
  input1(12) >= input2 
113 
  input1(13) >= input2 
113 
  input1(14) >= input2 
113 
  input1(15) >= input2 
113 
  input1(16) >= input2 
113 
  input1(17) >= input2 
113 
  input1(18) >= input2 
113 
  input1(19) >= input2 
113 
  input1(20) >= input2 
113 
  input1(21) >= input2 
113 
  input1(22) >= input2 
113 
  input1(23) >= input2 
113 
  input1(24) >= input2 
113 
  input1(25) >= input2 
113 
  input1(26) >= input2 
113 
  input1(27) >= input2 
113 
  input1(28) >= input2 
113 
  input1(29) >= input2 
113 
  input1(30) >= input2 
113 
  input1(31) >= input2 
113 
  input1(32) >= input2 
113 
  input1(33) >= input2 
113 
  input1(34) >= input2 
113 
  input1(35) >= input2 
113 
  input1(36) >= input2 
113 
  input1(37) >= input2 
113 
  input1(38) >= input2 
113 
  input1(39) >= input2 
113 
  input1(40) >= input2 
113 
  input1(41) >= input2 
113 
  input1(42) >= input2 
113 
  input1(43) >= input2 
113 
  input1(44) >= input2 
113 
  input1(45) >= input2 
113 
  input1(46) >= input2 
113 
  input1(47) >= input2 
113 
  input1(48) >= input2 
113 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

176. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1/FaultProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Sum block "Add" Execution

177. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1/FaultProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 96
Decision NA 50% (96/192) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 96
Decision 50% (96/192) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input(1) > lower limit  50%
      false 0/113
      true 113/113
  input(1) >= upper limit  50%
      false 113/113
      true 0/113
  input(2) > lower limit  50%
      false 0/113
      true 113/113
  input(2) >= upper limit  50%
      false 113/113
      true 0/113
  input(3) > lower limit  50%
      false 0/113
      true 113/113
  input(3) >= upper limit  50%
      false 113/113
      true 0/113
  input(4) > lower limit  50%
      false 0/113
      true 113/113
  input(4) >= upper limit  50%
      false 113/113
      true 0/113
  input(5) > lower limit  50%
      false 0/113
      true 113/113
  input(5) >= upper limit  50%
      false 113/113
      true 0/113
  input(6) > lower limit  50%
      false 0/113
      true 113/113
  input(6) >= upper limit  50%
      false 113/113
      true 0/113
  input(7) > lower limit  50%
      false 0/113
      true 113/113
  input(7) >= upper limit  50%
      false 113/113
      true 0/113
  input(8) > lower limit  50%
      false 0/113
      true 113/113
  input(8) >= upper limit  50%
      false 113/113
      true 0/113
  input(9) > lower limit  50%
      false 0/113
      true 113/113
  input(9) >= upper limit  50%
      false 113/113
      true 0/113
  input(10) > lower limit  50%
      false 0/113
      true 113/113
  input(10) >= upper limit  50%
      false 113/113
      true 0/113
  input(11) > lower limit  50%
      false 0/113
      true 113/113
  input(11) >= upper limit  50%
      false 113/113
      true 0/113
  input(12) > lower limit  50%
      false 0/113
      true 113/113
  input(12) >= upper limit  50%
      false 113/113
      true 0/113
  input(13) > lower limit  50%
      false 0/113
      true 113/113
  input(13) >= upper limit  50%
      false 113/113
      true 0/113
  input(14) > lower limit  50%
      false 0/113
      true 113/113
  input(14) >= upper limit  50%
      false 113/113
      true 0/113
  input(15) > lower limit  50%
      false 0/113
      true 113/113
  input(15) >= upper limit  50%
      false 113/113
      true 0/113
  input(16) > lower limit  50%
      false 0/113
      true 113/113
  input(16) >= upper limit  50%
      false 113/113
      true 0/113
  input(17) > lower limit  50%
      false 0/113
      true 113/113
  input(17) >= upper limit  50%
      false 113/113
      true 0/113
  input(18) > lower limit  50%
      false 0/113
      true 113/113
  input(18) >= upper limit  50%
      false 113/113
      true 0/113
  input(19) > lower limit  50%
      false 0/113
      true 113/113
  input(19) >= upper limit  50%
      false 113/113
      true 0/113
  input(20) > lower limit  50%
      false 0/113
      true 113/113
  input(20) >= upper limit  50%
      false 113/113
      true 0/113
  input(21) > lower limit  50%
      false 0/113
      true 113/113
  input(21) >= upper limit  50%
      false 113/113
      true 0/113
  input(22) > lower limit  50%
      false 0/113
      true 113/113
  input(22) >= upper limit  50%
      false 113/113
      true 0/113
  input(23) > lower limit  50%
      false 0/113
      true 113/113
  input(23) >= upper limit  50%
      false 113/113
      true 0/113
  input(24) > lower limit  50%
      false 0/113
      true 113/113
  input(24) >= upper limit  50%
      false 113/113
      true 0/113
  input(25) > lower limit  50%
      false 0/113
      true 113/113
  input(25) >= upper limit  50%
      false 113/113
      true 0/113
  input(26) > lower limit  50%
      false 0/113
      true 113/113
  input(26) >= upper limit  50%
      false 113/113
      true 0/113
  input(27) > lower limit  50%
      false 0/113
      true 113/113
  input(27) >= upper limit  50%
      false 113/113
      true 0/113
  input(28) > lower limit  50%
      false 0/113
      true 113/113
  input(28) >= upper limit  50%
      false 113/113
      true 0/113
  input(29) > lower limit  50%
      false 0/113
      true 113/113
  input(29) >= upper limit  50%
      false 113/113
      true 0/113
  input(30) > lower limit  50%
      false 0/113
      true 113/113
  input(30) >= upper limit  50%
      false 113/113
      true 0/113
  input(31) > lower limit  50%
      false 0/113
      true 113/113
  input(31) >= upper limit  50%
      false 113/113
      true 0/113
  input(32) > lower limit  50%
      false 0/113
      true 113/113
  input(32) >= upper limit  50%
      false 113/113
      true 0/113
  input(33) > lower limit  50%
      false 0/113
      true 113/113
  input(33) >= upper limit  50%
      false 113/113
      true 0/113
  input(34) > lower limit  50%
      false 0/113
      true 113/113
  input(34) >= upper limit  50%
      false 113/113
      true 0/113
  input(35) > lower limit  50%
      false 0/113
      true 113/113
  input(35) >= upper limit  50%
      false 113/113
      true 0/113
  input(36) > lower limit  50%
      false 0/113
      true 113/113
  input(36) >= upper limit  50%
      false 113/113
      true 0/113
  input(37) > lower limit  50%
      false 0/113
      true 113/113
  input(37) >= upper limit  50%
      false 113/113
      true 0/113
  input(38) > lower limit  50%
      false 0/113
      true 113/113
  input(38) >= upper limit  50%
      false 113/113
      true 0/113
  input(39) > lower limit  50%
      false 0/113
      true 113/113
  input(39) >= upper limit  50%
      false 113/113
      true 0/113
  input(40) > lower limit  50%
      false 0/113
      true 113/113
  input(40) >= upper limit  50%
      false 113/113
      true 0/113
  input(41) > lower limit  50%
      false 0/113
      true 113/113
  input(41) >= upper limit  50%
      false 113/113
      true 0/113
  input(42) > lower limit  50%
      false 0/113
      true 113/113
  input(42) >= upper limit  50%
      false 113/113
      true 0/113
  input(43) > lower limit  50%
      false 0/113
      true 113/113
  input(43) >= upper limit  50%
      false 113/113
      true 0/113
  input(44) > lower limit  50%
      false 0/113
      true 113/113
  input(44) >= upper limit  50%
      false 113/113
      true 0/113
  input(45) > lower limit  50%
      false 0/113
      true 113/113
  input(45) >= upper limit  50%
      false 113/113
      true 0/113
  input(46) > lower limit  50%
      false 0/113
      true 113/113
  input(46) >= upper limit  50%
      false 113/113
      true 0/113
  input(47) > lower limit  50%
      false 0/113
      true 113/113
  input(47) >= upper limit  50%
      false 113/113
      true 0/113
  input(48) > lower limit  50%
      false 0/113
      true 113/113
  input(48) >= upper limit  50%
      false 113/113
      true 0/113

   Full Coverage

Model Object Metric
Sum block "Add" Execution

178. SubSystem block "HealProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1
Child Systems: Compare To Zero,  Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 288
Condition NA 83% (240/288) condition outcomes
Decision NA 75% (432/576) decision outcomes
Execution NA 100% (15/15) objective outcomes

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 50% (48/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
Switch block "Switch2" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay1" Execution
UnitDelay block "Unit Delay2" Execution

179. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (48/96) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1/HealProcess/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (48/96) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) == input2  113 
  input1(2) == input2  113 
  input1(3) == input2  113 
  input1(4) == input2  113 
  input1(5) == input2  113 
  input1(6) == input2  113 
  input1(7) == input2  113 
  input1(8) == input2  113 
  input1(9) == input2  113 
  input1(10) == input2  113 
  input1(11) == input2  113 
  input1(12) == input2  113 
  input1(13) == input2  113 
  input1(14) == input2  113 
  input1(15) == input2  113 
  input1(16) == input2  113 
  input1(17) == input2  113 
  input1(18) == input2  113 
  input1(19) == input2  113 
  input1(20) == input2  113 
  input1(21) == input2  113 
  input1(22) == input2  113 
  input1(23) == input2  113 
  input1(24) == input2  113 
  input1(25) == input2  113 
  input1(26) == input2  113 
  input1(27) == input2  113 
  input1(28) == input2  113 
  input1(29) == input2  113 
  input1(30) == input2  113 
  input1(31) == input2  113 
  input1(32) == input2  113 
  input1(33) == input2  113 
  input1(34) == input2  113 
  input1(35) == input2  113 
  input1(36) == input2  113 
  input1(37) == input2  113 
  input1(38) == input2  113 
  input1(39) == input2  113 
  input1(40) == input2  113 
  input1(41) == input2  113 
  input1(42) == input2  113 
  input1(43) == input2  113 
  input1(44) == input2  113 
  input1(45) == input2  113 
  input1(46) == input2  113 
  input1(47) == input2  113 
  input1(48) == input2  113 

180. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1/HealProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 48
Condition NA 100% (96/96) condition outcomes
Decision NA 100% (96/96) decision outcomes
Execution NA 100% (4/4) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution

181. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1/HealProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Sum block "Add" Execution

182. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 96
Decision NA 50% (96/192) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero1/HealProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 96
Decision 50% (96/192) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input(1) > lower limit  50%
      false 0/113
      true 113/113
  input(1) >= upper limit  50%
      false 113/113
      true 0/113
  input(2) > lower limit  50%
      false 0/113
      true 113/113
  input(2) >= upper limit  50%
      false 113/113
      true 0/113
  input(3) > lower limit  50%
      false 0/113
      true 113/113
  input(3) >= upper limit  50%
      false 113/113
      true 0/113
  input(4) > lower limit  50%
      false 0/113
      true 113/113
  input(4) >= upper limit  50%
      false 113/113
      true 0/113
  input(5) > lower limit  50%
      false 0/113
      true 113/113
  input(5) >= upper limit  50%
      false 113/113
      true 0/113
  input(6) > lower limit  50%
      false 0/113
      true 113/113
  input(6) >= upper limit  50%
      false 113/113
      true 0/113
  input(7) > lower limit  50%
      false 0/113
      true 113/113
  input(7) >= upper limit  50%
      false 113/113
      true 0/113
  input(8) > lower limit  50%
      false 0/113
      true 113/113
  input(8) >= upper limit  50%
      false 113/113
      true 0/113
  input(9) > lower limit  50%
      false 0/113
      true 113/113
  input(9) >= upper limit  50%
      false 113/113
      true 0/113
  input(10) > lower limit  50%
      false 0/113
      true 113/113
  input(10) >= upper limit  50%
      false 113/113
      true 0/113
  input(11) > lower limit  50%
      false 0/113
      true 113/113
  input(11) >= upper limit  50%
      false 113/113
      true 0/113
  input(12) > lower limit  50%
      false 0/113
      true 113/113
  input(12) >= upper limit  50%
      false 113/113
      true 0/113
  input(13) > lower limit  50%
      false 0/113
      true 113/113
  input(13) >= upper limit  50%
      false 113/113
      true 0/113
  input(14) > lower limit  50%
      false 0/113
      true 113/113
  input(14) >= upper limit  50%
      false 113/113
      true 0/113
  input(15) > lower limit  50%
      false 0/113
      true 113/113
  input(15) >= upper limit  50%
      false 113/113
      true 0/113
  input(16) > lower limit  50%
      false 0/113
      true 113/113
  input(16) >= upper limit  50%
      false 113/113
      true 0/113
  input(17) > lower limit  50%
      false 0/113
      true 113/113
  input(17) >= upper limit  50%
      false 113/113
      true 0/113
  input(18) > lower limit  50%
      false 0/113
      true 113/113
  input(18) >= upper limit  50%
      false 113/113
      true 0/113
  input(19) > lower limit  50%
      false 0/113
      true 113/113
  input(19) >= upper limit  50%
      false 113/113
      true 0/113
  input(20) > lower limit  50%
      false 0/113
      true 113/113
  input(20) >= upper limit  50%
      false 113/113
      true 0/113
  input(21) > lower limit  50%
      false 0/113
      true 113/113
  input(21) >= upper limit  50%
      false 113/113
      true 0/113
  input(22) > lower limit  50%
      false 0/113
      true 113/113
  input(22) >= upper limit  50%
      false 113/113
      true 0/113
  input(23) > lower limit  50%
      false 0/113
      true 113/113
  input(23) >= upper limit  50%
      false 113/113
      true 0/113
  input(24) > lower limit  50%
      false 0/113
      true 113/113
  input(24) >= upper limit  50%
      false 113/113
      true 0/113
  input(25) > lower limit  50%
      false 0/113
      true 113/113
  input(25) >= upper limit  50%
      false 113/113
      true 0/113
  input(26) > lower limit  50%
      false 0/113
      true 113/113
  input(26) >= upper limit  50%
      false 113/113
      true 0/113
  input(27) > lower limit  50%
      false 0/113
      true 113/113
  input(27) >= upper limit  50%
      false 113/113
      true 0/113
  input(28) > lower limit  50%
      false 0/113
      true 113/113
  input(28) >= upper limit  50%
      false 113/113
      true 0/113
  input(29) > lower limit  50%
      false 0/113
      true 113/113
  input(29) >= upper limit  50%
      false 113/113
      true 0/113
  input(30) > lower limit  50%
      false 0/113
      true 113/113
  input(30) >= upper limit  50%
      false 113/113
      true 0/113
  input(31) > lower limit  50%
      false 0/113
      true 113/113
  input(31) >= upper limit  50%
      false 113/113
      true 0/113
  input(32) > lower limit  50%
      false 0/113
      true 113/113
  input(32) >= upper limit  50%
      false 113/113
      true 0/113
  input(33) > lower limit  50%
      false 0/113
      true 113/113
  input(33) >= upper limit  50%
      false 113/113
      true 0/113
  input(34) > lower limit  50%
      false 0/113
      true 113/113
  input(34) >= upper limit  50%
      false 113/113
      true 0/113
  input(35) > lower limit  50%
      false 0/113
      true 113/113
  input(35) >= upper limit  50%
      false 113/113
      true 0/113
  input(36) > lower limit  50%
      false 0/113
      true 113/113
  input(36) >= upper limit  50%
      false 113/113
      true 0/113
  input(37) > lower limit  50%
      false 0/113
      true 113/113
  input(37) >= upper limit  50%
      false 113/113
      true 0/113
  input(38) > lower limit  50%
      false 0/113
      true 113/113
  input(38) >= upper limit  50%
      false 113/113
      true 0/113
  input(39) > lower limit  50%
      false 0/113
      true 113/113
  input(39) >= upper limit  50%
      false 113/113
      true 0/113
  input(40) > lower limit  50%
      false 0/113
      true 113/113
  input(40) >= upper limit  50%
      false 113/113
      true 0/113
  input(41) > lower limit  50%
      false 0/113
      true 113/113
  input(41) >= upper limit  50%
      false 113/113
      true 0/113
  input(42) > lower limit  50%
      false 0/113
      true 113/113
  input(42) >= upper limit  50%
      false 113/113
      true 0/113
  input(43) > lower limit  50%
      false 0/113
      true 113/113
  input(43) >= upper limit  50%
      false 113/113
      true 0/113
  input(44) > lower limit  50%
      false 0/113
      true 113/113
  input(44) >= upper limit  50%
      false 113/113
      true 0/113
  input(45) > lower limit  50%
      false 0/113
      true 113/113
  input(45) >= upper limit  50%
      false 113/113
      true 0/113
  input(46) > lower limit  50%
      false 0/113
      true 113/113
  input(46) >= upper limit  50%
      false 113/113
      true 0/113
  input(47) > lower limit  50%
      false 0/113
      true 113/113
  input(47) >= upper limit  50%
      false 113/113
      true 0/113
  input(48) > lower limit  50%
      false 0/113
      true 113/113
  input(48) >= upper limit  50%
      false 113/113
      true 0/113

   Full Coverage

Model Object Metric
Sum block "Add" Execution

183. SubSystem block "DebounceStartZero2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag
Child Systems: Compare To Zero,  FaultProcess,  HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 625
Condition NA 67% (384/576) condition outcomes
Decision NA 62% (768/1248) decision outcomes
Execution NA 100% (32/32) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 50% (48/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

184. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (48/96) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (48/96) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) == input2  113 
  input1(2) == input2  113 
  input1(3) == input2  113 
  input1(4) == input2  113 
  input1(5) == input2  113 
  input1(6) == input2  113 
  input1(7) == input2  113 
  input1(8) == input2  113 
  input1(9) == input2  113 
  input1(10) == input2  113 
  input1(11) == input2  113 
  input1(12) == input2  113 
  input1(13) == input2  113 
  input1(14) == input2  113 
  input1(15) == input2  113 
  input1(16) == input2  113 
  input1(17) == input2  113 
  input1(18) == input2  113 
  input1(19) == input2  113 
  input1(20) == input2  113 
  input1(21) == input2  113 
  input1(22) == input2  113 
  input1(23) == input2  113 
  input1(24) == input2  113 
  input1(25) == input2  113 
  input1(26) == input2  113 
  input1(27) == input2  113 
  input1(28) == input2  113 
  input1(29) == input2  113 
  input1(30) == input2  113 
  input1(31) == input2  113 
  input1(32) == input2  113 
  input1(33) == input2  113 
  input1(34) == input2  113 
  input1(35) == input2  113 
  input1(36) == input2  113 
  input1(37) == input2  113 
  input1(38) == input2  113 
  input1(39) == input2  113 
  input1(40) == input2  113 
  input1(41) == input2  113 
  input1(42) == input2  113 
  input1(43) == input2  113 
  input1(44) == input2  113 
  input1(45) == input2  113 
  input1(46) == input2  113 
  input1(47) == input2  113 
  input1(48) == input2  113 

185. SubSystem block "FaultProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2
Child Systems: Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 288
Condition NA 50% (96/192) condition outcomes
Decision NA 50% (288/576) decision outcomes
Execution NA 100% (14/14) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 50% (48/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 50% (48/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 50% (48/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (48/96) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) > input2 
113 
  input1(2) > input2 
113 
  input1(3) > input2 
113 
  input1(4) > input2 
113 
  input1(5) > input2 
113 
  input1(6) > input2 
113 
  input1(7) > input2 
113 
  input1(8) > input2 
113 
  input1(9) > input2 
113 
  input1(10) > input2 
113 
  input1(11) > input2 
113 
  input1(12) > input2 
113 
  input1(13) > input2 
113 
  input1(14) > input2 
113 
  input1(15) > input2 
113 
  input1(16) > input2 
113 
  input1(17) > input2 
113 
  input1(18) > input2 
113 
  input1(19) > input2 
113 
  input1(20) > input2 
113 
  input1(21) > input2 
113 
  input1(22) > input2 
113 
  input1(23) > input2 
113 
  input1(24) > input2 
113 
  input1(25) > input2 
113 
  input1(26) > input2 
113 
  input1(27) > input2 
113 
  input1(28) > input2 
113 
  input1(29) > input2 
113 
  input1(30) > input2 
113 
  input1(31) > input2 
113 
  input1(32) > input2 
113 
  input1(33) > input2 
113 
  input1(34) > input2 
113 
  input1(35) > input2 
113 
  input1(36) > input2 
113 
  input1(37) > input2 
113 
  input1(38) > input2 
113 
  input1(39) > input2 
113 
  input1(40) > input2 
113 
  input1(41) > input2 
113 
  input1(42) > input2 
113 
  input1(43) > input2 
113 
  input1(44) > input2 
113 
  input1(45) > input2 
113 
  input1(46) > input2 
113 
  input1(47) > input2 
113 
  input1(48) > input2 
113 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

186. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2/FaultProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 48
Condition NA 50% (48/96) condition outcomes
Decision NA 50% (48/96) decision outcomes
Execution NA 100% (4/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 50% (48/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 113/113
      true (output is from 1st input port) 0/113

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (48/96) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) >= input2 
113 
  input1(2) >= input2 
113 
  input1(3) >= input2 
113 
  input1(4) >= input2 
113 
  input1(5) >= input2 
113 
  input1(6) >= input2 
113 
  input1(7) >= input2 
113 
  input1(8) >= input2 
113 
  input1(9) >= input2 
113 
  input1(10) >= input2 
113 
  input1(11) >= input2 
113 
  input1(12) >= input2 
113 
  input1(13) >= input2 
113 
  input1(14) >= input2 
113 
  input1(15) >= input2 
113 
  input1(16) >= input2 
113 
  input1(17) >= input2 
113 
  input1(18) >= input2 
113 
  input1(19) >= input2 
113 
  input1(20) >= input2 
113 
  input1(21) >= input2 
113 
  input1(22) >= input2 
113 
  input1(23) >= input2 
113 
  input1(24) >= input2 
113 
  input1(25) >= input2 
113 
  input1(26) >= input2 
113 
  input1(27) >= input2 
113 
  input1(28) >= input2 
113 
  input1(29) >= input2 
113 
  input1(30) >= input2 
113 
  input1(31) >= input2 
113 
  input1(32) >= input2 
113 
  input1(33) >= input2 
113 
  input1(34) >= input2 
113 
  input1(35) >= input2 
113 
  input1(36) >= input2 
113 
  input1(37) >= input2 
113 
  input1(38) >= input2 
113 
  input1(39) >= input2 
113 
  input1(40) >= input2 
113 
  input1(41) >= input2 
113 
  input1(42) >= input2 
113 
  input1(43) >= input2 
113 
  input1(44) >= input2 
113 
  input1(45) >= input2 
113 
  input1(46) >= input2 
113 
  input1(47) >= input2 
113 
  input1(48) >= input2 
113 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

187. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2/FaultProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Sum block "Add" Execution

188. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2/FaultProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 96
Decision NA 50% (96/192) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 96
Decision 50% (96/192) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input(1) > lower limit  50%
      false 0/113
      true 113/113
  input(1) >= upper limit  50%
      false 113/113
      true 0/113
  input(2) > lower limit  50%
      false 0/113
      true 113/113
  input(2) >= upper limit  50%
      false 113/113
      true 0/113
  input(3) > lower limit  50%
      false 0/113
      true 113/113
  input(3) >= upper limit  50%
      false 113/113
      true 0/113
  input(4) > lower limit  50%
      false 0/113
      true 113/113
  input(4) >= upper limit  50%
      false 113/113
      true 0/113
  input(5) > lower limit  50%
      false 0/113
      true 113/113
  input(5) >= upper limit  50%
      false 113/113
      true 0/113
  input(6) > lower limit  50%
      false 0/113
      true 113/113
  input(6) >= upper limit  50%
      false 113/113
      true 0/113
  input(7) > lower limit  50%
      false 0/113
      true 113/113
  input(7) >= upper limit  50%
      false 113/113
      true 0/113
  input(8) > lower limit  50%
      false 0/113
      true 113/113
  input(8) >= upper limit  50%
      false 113/113
      true 0/113
  input(9) > lower limit  50%
      false 0/113
      true 113/113
  input(9) >= upper limit  50%
      false 113/113
      true 0/113
  input(10) > lower limit  50%
      false 0/113
      true 113/113
  input(10) >= upper limit  50%
      false 113/113
      true 0/113
  input(11) > lower limit  50%
      false 0/113
      true 113/113
  input(11) >= upper limit  50%
      false 113/113
      true 0/113
  input(12) > lower limit  50%
      false 0/113
      true 113/113
  input(12) >= upper limit  50%
      false 113/113
      true 0/113
  input(13) > lower limit  50%
      false 0/113
      true 113/113
  input(13) >= upper limit  50%
      false 113/113
      true 0/113
  input(14) > lower limit  50%
      false 0/113
      true 113/113
  input(14) >= upper limit  50%
      false 113/113
      true 0/113
  input(15) > lower limit  50%
      false 0/113
      true 113/113
  input(15) >= upper limit  50%
      false 113/113
      true 0/113
  input(16) > lower limit  50%
      false 0/113
      true 113/113
  input(16) >= upper limit  50%
      false 113/113
      true 0/113
  input(17) > lower limit  50%
      false 0/113
      true 113/113
  input(17) >= upper limit  50%
      false 113/113
      true 0/113
  input(18) > lower limit  50%
      false 0/113
      true 113/113
  input(18) >= upper limit  50%
      false 113/113
      true 0/113
  input(19) > lower limit  50%
      false 0/113
      true 113/113
  input(19) >= upper limit  50%
      false 113/113
      true 0/113
  input(20) > lower limit  50%
      false 0/113
      true 113/113
  input(20) >= upper limit  50%
      false 113/113
      true 0/113
  input(21) > lower limit  50%
      false 0/113
      true 113/113
  input(21) >= upper limit  50%
      false 113/113
      true 0/113
  input(22) > lower limit  50%
      false 0/113
      true 113/113
  input(22) >= upper limit  50%
      false 113/113
      true 0/113
  input(23) > lower limit  50%
      false 0/113
      true 113/113
  input(23) >= upper limit  50%
      false 113/113
      true 0/113
  input(24) > lower limit  50%
      false 0/113
      true 113/113
  input(24) >= upper limit  50%
      false 113/113
      true 0/113
  input(25) > lower limit  50%
      false 0/113
      true 113/113
  input(25) >= upper limit  50%
      false 113/113
      true 0/113
  input(26) > lower limit  50%
      false 0/113
      true 113/113
  input(26) >= upper limit  50%
      false 113/113
      true 0/113
  input(27) > lower limit  50%
      false 0/113
      true 113/113
  input(27) >= upper limit  50%
      false 113/113
      true 0/113
  input(28) > lower limit  50%
      false 0/113
      true 113/113
  input(28) >= upper limit  50%
      false 113/113
      true 0/113
  input(29) > lower limit  50%
      false 0/113
      true 113/113
  input(29) >= upper limit  50%
      false 113/113
      true 0/113
  input(30) > lower limit  50%
      false 0/113
      true 113/113
  input(30) >= upper limit  50%
      false 113/113
      true 0/113
  input(31) > lower limit  50%
      false 0/113
      true 113/113
  input(31) >= upper limit  50%
      false 113/113
      true 0/113
  input(32) > lower limit  50%
      false 0/113
      true 113/113
  input(32) >= upper limit  50%
      false 113/113
      true 0/113
  input(33) > lower limit  50%
      false 0/113
      true 113/113
  input(33) >= upper limit  50%
      false 113/113
      true 0/113
  input(34) > lower limit  50%
      false 0/113
      true 113/113
  input(34) >= upper limit  50%
      false 113/113
      true 0/113
  input(35) > lower limit  50%
      false 0/113
      true 113/113
  input(35) >= upper limit  50%
      false 113/113
      true 0/113
  input(36) > lower limit  50%
      false 0/113
      true 113/113
  input(36) >= upper limit  50%
      false 113/113
      true 0/113
  input(37) > lower limit  50%
      false 0/113
      true 113/113
  input(37) >= upper limit  50%
      false 113/113
      true 0/113
  input(38) > lower limit  50%
      false 0/113
      true 113/113
  input(38) >= upper limit  50%
      false 113/113
      true 0/113
  input(39) > lower limit  50%
      false 0/113
      true 113/113
  input(39) >= upper limit  50%
      false 113/113
      true 0/113
  input(40) > lower limit  50%
      false 0/113
      true 113/113
  input(40) >= upper limit  50%
      false 113/113
      true 0/113
  input(41) > lower limit  50%
      false 0/113
      true 113/113
  input(41) >= upper limit  50%
      false 113/113
      true 0/113
  input(42) > lower limit  50%
      false 0/113
      true 113/113
  input(42) >= upper limit  50%
      false 113/113
      true 0/113
  input(43) > lower limit  50%
      false 0/113
      true 113/113
  input(43) >= upper limit  50%
      false 113/113
      true 0/113
  input(44) > lower limit  50%
      false 0/113
      true 113/113
  input(44) >= upper limit  50%
      false 113/113
      true 0/113
  input(45) > lower limit  50%
      false 0/113
      true 113/113
  input(45) >= upper limit  50%
      false 113/113
      true 0/113
  input(46) > lower limit  50%
      false 0/113
      true 113/113
  input(46) >= upper limit  50%
      false 113/113
      true 0/113
  input(47) > lower limit  50%
      false 0/113
      true 113/113
  input(47) >= upper limit  50%
      false 113/113
      true 0/113
  input(48) > lower limit  50%
      false 0/113
      true 113/113
  input(48) >= upper limit  50%
      false 113/113
      true 0/113

   Full Coverage

Model Object Metric
Sum block "Add" Execution

189. SubSystem block "HealProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2
Child Systems: Compare To Zero,  Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 288
Condition NA 83% (240/288) condition outcomes
Decision NA 75% (432/576) decision outcomes
Execution NA 100% (15/15) objective outcomes

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 48
Decision 50% (48/96) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(2)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(3)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(4)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(5)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(6)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(7)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(8)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(9)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(10)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(11)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(12)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(13)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(14)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(15)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(16)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(17)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(18)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(19)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(20)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(21)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(22)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(23)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(24)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(25)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(26)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(27)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(28)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(29)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(30)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(31)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(32)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(33)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(34)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(35)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(36)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(37)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(38)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(39)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(40)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(41)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(42)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(43)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(44)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(45)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(46)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(47)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113
  logical trigger input(48)  50%
      false (output is from 3rd input port) 0/113
      true (output is from 1st input port) 113/113

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
Switch block "Switch2" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay1" Execution
UnitDelay block "Unit Delay2" Execution

190. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (48/96) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2/HealProcess/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (48/96) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) == input2  113 
  input1(2) == input2  113 
  input1(3) == input2  113 
  input1(4) == input2  113 
  input1(5) == input2  113 
  input1(6) == input2  113 
  input1(7) == input2  113 
  input1(8) == input2  113 
  input1(9) == input2  113 
  input1(10) == input2  113 
  input1(11) == input2  113 
  input1(12) == input2  113 
  input1(13) == input2  113 
  input1(14) == input2  113 
  input1(15) == input2  113 
  input1(16) == input2  113 
  input1(17) == input2  113 
  input1(18) == input2  113 
  input1(19) == input2  113 
  input1(20) == input2  113 
  input1(21) == input2  113 
  input1(22) == input2  113 
  input1(23) == input2  113 
  input1(24) == input2  113 
  input1(25) == input2  113 
  input1(26) == input2  113 
  input1(27) == input2  113 
  input1(28) == input2  113 
  input1(29) == input2  113 
  input1(30) == input2  113 
  input1(31) == input2  113 
  input1(32) == input2  113 
  input1(33) == input2  113 
  input1(34) == input2  113 
  input1(35) == input2  113 
  input1(36) == input2  113 
  input1(37) == input2  113 
  input1(38) == input2  113 
  input1(39) == input2  113 
  input1(40) == input2  113 
  input1(41) == input2  113 
  input1(42) == input2  113 
  input1(43) == input2  113 
  input1(44) == input2  113 
  input1(45) == input2  113 
  input1(46) == input2  113 
  input1(47) == input2  113 
  input1(48) == input2  113 

191. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2/HealProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 48
Condition NA 100% (96/96) condition outcomes
Decision NA 100% (96/96) decision outcomes
Execution NA 100% (4/4) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution

192. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2/HealProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Sum block "Add" Execution

193. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 96
Decision NA 50% (96/192) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/DebounceStartZero2/HealProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 96
Decision 50% (96/192) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input(1) > lower limit  50%
      false 0/113
      true 113/113
  input(1) >= upper limit  50%
      false 113/113
      true 0/113
  input(2) > lower limit  50%
      false 0/113
      true 113/113
  input(2) >= upper limit  50%
      false 113/113
      true 0/113
  input(3) > lower limit  50%
      false 0/113
      true 113/113
  input(3) >= upper limit  50%
      false 113/113
      true 0/113
  input(4) > lower limit  50%
      false 0/113
      true 113/113
  input(4) >= upper limit  50%
      false 113/113
      true 0/113
  input(5) > lower limit  50%
      false 0/113
      true 113/113
  input(5) >= upper limit  50%
      false 113/113
      true 0/113
  input(6) > lower limit  50%
      false 0/113
      true 113/113
  input(6) >= upper limit  50%
      false 113/113
      true 0/113
  input(7) > lower limit  50%
      false 0/113
      true 113/113
  input(7) >= upper limit  50%
      false 113/113
      true 0/113
  input(8) > lower limit  50%
      false 0/113
      true 113/113
  input(8) >= upper limit  50%
      false 113/113
      true 0/113
  input(9) > lower limit  50%
      false 0/113
      true 113/113
  input(9) >= upper limit  50%
      false 113/113
      true 0/113
  input(10) > lower limit  50%
      false 0/113
      true 113/113
  input(10) >= upper limit  50%
      false 113/113
      true 0/113
  input(11) > lower limit  50%
      false 0/113
      true 113/113
  input(11) >= upper limit  50%
      false 113/113
      true 0/113
  input(12) > lower limit  50%
      false 0/113
      true 113/113
  input(12) >= upper limit  50%
      false 113/113
      true 0/113
  input(13) > lower limit  50%
      false 0/113
      true 113/113
  input(13) >= upper limit  50%
      false 113/113
      true 0/113
  input(14) > lower limit  50%
      false 0/113
      true 113/113
  input(14) >= upper limit  50%
      false 113/113
      true 0/113
  input(15) > lower limit  50%
      false 0/113
      true 113/113
  input(15) >= upper limit  50%
      false 113/113
      true 0/113
  input(16) > lower limit  50%
      false 0/113
      true 113/113
  input(16) >= upper limit  50%
      false 113/113
      true 0/113
  input(17) > lower limit  50%
      false 0/113
      true 113/113
  input(17) >= upper limit  50%
      false 113/113
      true 0/113
  input(18) > lower limit  50%
      false 0/113
      true 113/113
  input(18) >= upper limit  50%
      false 113/113
      true 0/113
  input(19) > lower limit  50%
      false 0/113
      true 113/113
  input(19) >= upper limit  50%
      false 113/113
      true 0/113
  input(20) > lower limit  50%
      false 0/113
      true 113/113
  input(20) >= upper limit  50%
      false 113/113
      true 0/113
  input(21) > lower limit  50%
      false 0/113
      true 113/113
  input(21) >= upper limit  50%
      false 113/113
      true 0/113
  input(22) > lower limit  50%
      false 0/113
      true 113/113
  input(22) >= upper limit  50%
      false 113/113
      true 0/113
  input(23) > lower limit  50%
      false 0/113
      true 113/113
  input(23) >= upper limit  50%
      false 113/113
      true 0/113
  input(24) > lower limit  50%
      false 0/113
      true 113/113
  input(24) >= upper limit  50%
      false 113/113
      true 0/113
  input(25) > lower limit  50%
      false 0/113
      true 113/113
  input(25) >= upper limit  50%
      false 113/113
      true 0/113
  input(26) > lower limit  50%
      false 0/113
      true 113/113
  input(26) >= upper limit  50%
      false 113/113
      true 0/113
  input(27) > lower limit  50%
      false 0/113
      true 113/113
  input(27) >= upper limit  50%
      false 113/113
      true 0/113
  input(28) > lower limit  50%
      false 0/113
      true 113/113
  input(28) >= upper limit  50%
      false 113/113
      true 0/113
  input(29) > lower limit  50%
      false 0/113
      true 113/113
  input(29) >= upper limit  50%
      false 113/113
      true 0/113
  input(30) > lower limit  50%
      false 0/113
      true 113/113
  input(30) >= upper limit  50%
      false 113/113
      true 0/113
  input(31) > lower limit  50%
      false 0/113
      true 113/113
  input(31) >= upper limit  50%
      false 113/113
      true 0/113
  input(32) > lower limit  50%
      false 0/113
      true 113/113
  input(32) >= upper limit  50%
      false 113/113
      true 0/113
  input(33) > lower limit  50%
      false 0/113
      true 113/113
  input(33) >= upper limit  50%
      false 113/113
      true 0/113
  input(34) > lower limit  50%
      false 0/113
      true 113/113
  input(34) >= upper limit  50%
      false 113/113
      true 0/113
  input(35) > lower limit  50%
      false 0/113
      true 113/113
  input(35) >= upper limit  50%
      false 113/113
      true 0/113
  input(36) > lower limit  50%
      false 0/113
      true 113/113
  input(36) >= upper limit  50%
      false 113/113
      true 0/113
  input(37) > lower limit  50%
      false 0/113
      true 113/113
  input(37) >= upper limit  50%
      false 113/113
      true 0/113
  input(38) > lower limit  50%
      false 0/113
      true 113/113
  input(38) >= upper limit  50%
      false 113/113
      true 0/113
  input(39) > lower limit  50%
      false 0/113
      true 113/113
  input(39) >= upper limit  50%
      false 113/113
      true 0/113
  input(40) > lower limit  50%
      false 0/113
      true 113/113
  input(40) >= upper limit  50%
      false 113/113
      true 0/113
  input(41) > lower limit  50%
      false 0/113
      true 113/113
  input(41) >= upper limit  50%
      false 113/113
      true 0/113
  input(42) > lower limit  50%
      false 0/113
      true 113/113
  input(42) >= upper limit  50%
      false 113/113
      true 0/113
  input(43) > lower limit  50%
      false 0/113
      true 113/113
  input(43) >= upper limit  50%
      false 113/113
      true 0/113
  input(44) > lower limit  50%
      false 0/113
      true 113/113
  input(44) >= upper limit  50%
      false 113/113
      true 0/113
  input(45) > lower limit  50%
      false 0/113
      true 113/113
  input(45) >= upper limit  50%
      false 113/113
      true 0/113
  input(46) > lower limit  50%
      false 0/113
      true 113/113
  input(46) >= upper limit  50%
      false 113/113
      true 0/113
  input(47) > lower limit  50%
      false 0/113
      true 113/113
  input(47) >= upper limit  50%
      false 113/113
      true 0/113
  input(48) > lower limit  50%
      false 0/113
      true 113/113
  input(48) >= upper limit  50%
      false 113/113
      true 0/113

   Full Coverage

Model Object Metric
Sum block "Add" Execution

194. SubSystem block "EdgeRising"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 1
Condition NA 50% (3/6) condition outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 100% (3/3) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/EdgeRising
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
113 
  input port 2  113 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
C1 && ~C2
      C1 (AND In1) (TF) FF
      C2 (OR1 In1) (TF) (TT)


   Logic block "OR1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/EdgeRising
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see AND
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
113 

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

195. SubSystem block "EdgeRising2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 1
Condition NA 50% (3/6) condition outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 100% (3/3) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/EdgeRising2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
113 
  input port 2  113 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
C1 && ~C2
      C1 (AND In1) (TF) FF
      C2 (OR1 In1) (TF) (TT)


   Logic block "OR1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag/EdgeRising2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see AND
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
113 

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

196. SubSystem block "MaxCellTempGrad_ForIterator1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Full Coverage

Model Object Metric
ForIterator block "MaxCellTempNumbIterator" Decision
Sum block "Sum1" Execution
Selector block "Selector1" Execution
UnitDelay block "Unit Delay9" Execution

197. SubSystem block "MaxCellTempGrad_ForIterator2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/CellTempGradDiag/CellTempGradDiag

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Full Coverage

Model Object Metric
ForIterator block "MaxCellTempNumbIterator" Decision
Sum block "Sum1" Execution
Selector block "Selector1" Execution
UnitDelay block "Unit Delay9" Execution

198. SubSystem block "EdgeRising"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 1
Condition NA 50% (3/6) condition outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 100% (3/3) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/EdgeRising
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  1601 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
C1 && ~C2
      C1 (AND In1) (TF) FF
      C2 (OR1 In1) (TF) (TT)


   Logic block "OR1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/EdgeRising
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see AND
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

199. SubSystem block "EdgeRising1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 1
Condition NA 50% (3/6) condition outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 100% (3/3) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/EdgeRising1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  1601 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
C1 && ~C2
      C1 (AND In1) (TF) FF
      C2 (OR1 In1) (TF) (TT)


   Logic block "OR1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/EdgeRising1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see AND
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

200. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/HDP_GbHDP_PackCrntSelfChck_flg1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

201. SubSystem block "MaxTempDiag1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck
Child Systems: MinCellTemp_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 2 9
Condition NA 0% (0/2) condition outcomes
Decision 50% (1/2) decision outcomes 8% (1/12) decision outcomes
Execution NA 8% (1/13) objective outcomes

  Decisions analyzed
  enable logical value  50%
      false 1601/1601
      true 0/1601

202. SubSystem block "MinCellTemp_ForIterator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/MaxTempDiag1
Child Systems: MaxCellTemp_ForIterator

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 7
Condition NA 0% (0/2) condition outcomes
Decision NA 0% (0/10) decision outcomes
Execution NA 8% (1/13) objective outcomes

   ForIterator block "MaxCellTempNumbIterator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/MaxTempDiag1/MinCellTemp_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes

  Decisions analyzed
  loop condition  0%
      false --
      true --

   DataTypeConversion block "Data Type Conversion"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/MaxTempDiag1/MinCellTemp_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   Selector block "Selector1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/MaxTempDiag1/MinCellTemp_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

203. SubSystem block "MaxCellTemp_ForIterator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/MaxTempDiag1/MinCellTemp_ForIterator
Child Systems: Unit Delay External IC,  Unit Delay External IC2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 0% (0/2) condition outcomes
Decision NA 0% (0/8) decision outcomes
Execution NA 9% (1/11) objective outcomes

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/MaxTempDiag1/MinCellTemp_ForIterator/MaxCellTemp_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Switch block "Switch3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/MaxTempDiag1/MinCellTemp_ForIterator/MaxCellTemp_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/MaxTempDiag1/MinCellTemp_ForIterator/MaxCellTemp_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 0% (0/2) condition outcomes
Execution 0% (0/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   UnitDelay block "Unit Delay3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/MaxTempDiag1/MinCellTemp_ForIterator/MaxCellTemp_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant3" Execution

204. SubSystem block "Unit Delay External IC"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/MaxTempDiag1/MinCellTemp_ForIterator/MaxCellTemp_ForIterator

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 0% (0/3) objective outcomes

   Switch block "Init"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/MaxTempDiag1/MinCellTemp_ForIterator/MaxCellTemp_ForIterator/Unit Delay External IC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   UnitDelay block "Unit Delay"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/MaxTempDiag1/MinCellTemp_ForIterator/MaxCellTemp_ForIterator/Unit Delay External IC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/MaxTempDiag1/MinCellTemp_ForIterator/MaxCellTemp_ForIterator/Unit Delay External IC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

205. SubSystem block "Unit Delay External IC2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/MaxTempDiag1/MinCellTemp_ForIterator/MaxCellTemp_ForIterator

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 0% (0/3) objective outcomes

   Switch block "Init"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/MaxTempDiag1/MinCellTemp_ForIterator/MaxCellTemp_ForIterator/Unit Delay External IC2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   UnitDelay block "Unit Delay"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/MaxTempDiag1/MinCellTemp_ForIterator/MaxCellTemp_ForIterator/Unit Delay External IC2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/MaxTempDiag1/MinCellTemp_ForIterator/MaxCellTemp_ForIterator/Unit Delay External IC2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

206. SubSystem block "TempGradCalc"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck
Child Systems: MaxCellTempGrad_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 2 9
Condition NA 0% (0/2) condition outcomes
Decision 50% (1/2) decision outcomes 8% (1/12) decision outcomes
Execution NA 8% (1/13) objective outcomes

  Decisions analyzed
  enable logical value  50%
      false 1601/1601
      true 0/1601

207. SubSystem block "MaxCellTempGrad_ForIterator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/TempGradCalc
Child Systems: MaxCellTemp_ForIterator

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 7
Condition NA 0% (0/2) condition outcomes
Decision NA 0% (0/10) decision outcomes
Execution NA 8% (1/13) objective outcomes

   ForIterator block "MaxCellTempNumbIterator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/TempGradCalc/MaxCellTempGrad_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes

  Decisions analyzed
  loop condition  0%
      false --
      true --

   DataTypeConversion block "Data Type Conversion"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/TempGradCalc/MaxCellTempGrad_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   Selector block "Selector1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/TempGradCalc/MaxCellTempGrad_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

208. SubSystem block "MaxCellTemp_ForIterator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/TempGradCalc/MaxCellTempGrad_ForIterator
Child Systems: Unit Delay External IC,  Unit Delay External IC2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 0% (0/2) condition outcomes
Decision NA 0% (0/8) decision outcomes
Execution NA 9% (1/11) objective outcomes

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/TempGradCalc/MaxCellTempGrad_ForIterator/MaxCellTemp_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Switch block "Switch3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/TempGradCalc/MaxCellTempGrad_ForIterator/MaxCellTemp_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/TempGradCalc/MaxCellTempGrad_ForIterator/MaxCellTemp_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 0% (0/2) condition outcomes
Execution 0% (0/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   UnitDelay block "Unit Delay3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/TempGradCalc/MaxCellTempGrad_ForIterator/MaxCellTemp_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant3" Execution

209. SubSystem block "Unit Delay External IC"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/TempGradCalc/MaxCellTempGrad_ForIterator/MaxCellTemp_ForIterator

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 0% (0/3) objective outcomes

   Switch block "Init"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/TempGradCalc/MaxCellTempGrad_ForIterator/MaxCellTemp_ForIterator/Unit Delay External IC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   UnitDelay block "Unit Delay"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/TempGradCalc/MaxCellTempGrad_ForIterator/MaxCellTemp_ForIterator/Unit Delay External IC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/TempGradCalc/MaxCellTempGrad_ForIterator/MaxCellTemp_ForIterator/Unit Delay External IC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

210. SubSystem block "Unit Delay External IC2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/TempGradCalc/MaxCellTempGrad_ForIterator/MaxCellTemp_ForIterator

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 0% (0/3) objective outcomes

   Switch block "Init"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/TempGradCalc/MaxCellTempGrad_ForIterator/MaxCellTemp_ForIterator/Unit Delay External IC2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   UnitDelay block "Unit Delay"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/TempGradCalc/MaxCellTempGrad_ForIterator/MaxCellTemp_ForIterator/Unit Delay External IC2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayCellTempCheck/TempGradCalc/MaxCellTempGrad_ForIterator/MaxCellTemp_ForIterator/Unit Delay External IC2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

211. SubSystem block "RunawayVoltTempCheck"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck
Child Systems: RunawayVoltCheck,  RunawayVoltGradCheck,  RunawayVoltTempCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 83
Condition NA 51% (555/1092) condition outcomes
Decision NA 48% (64/132) decision outcomes
MCDC NA 0% (0/46) conditions reversed the outcome
Execution NA 89% (230/259) objective outcomes

212. SubSystem block "RunawayVoltCheck"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck
Child Systems: Counter Reset Enabled ,  DebounceStartZero1,  DebounceStartZero2,  EdgeRising,  EdgeRising1,  EdgeRising2,  MaxCellVolt_ForIterator,  MinCellVolt_ForIterator

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 36
Condition NA 50% (255/510) condition outcomes
Decision NA 43% (26/60) decision outcomes
MCDC NA 0% (0/10) conditions reversed the outcome
Execution NA 87% (98/113) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical2
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2 
1601 

   Logic block "Logical1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical2
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2 
1601 

   Logic block "Logical2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/4) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  1601 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 4 blocks
Decision/Condition True Out False Out
(C1 || (C2 || C3)) && ~C4
      C1 (AND In1) (TFFF) FFFF
      C2 (Logical1 In1) (FTFF) FFFF
      C3 (Logical1 In2) (FFTF) FFFF
      C4 (Logical3 In1) (TTTF) (TTTT)


   Logic block "Logical3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see Logical2
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 

   RelationalOperator block "Comparison"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
1601 

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (112/224) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) >= input2 
1601 
  input1(2) >= input2 
1601 
  input1(3) >= input2 
1601 
  input1(4) >= input2 
1601 
  input1(5) >= input2 
1601 
  input1(6) >= input2 
1601 
  input1(7) >= input2 
1601 
  input1(8) >= input2 
1601 
  input1(9) >= input2 
1601 
  input1(10) >= input2 
1601 
  input1(11) >= input2 
1601 
  input1(12) >= input2 
1601 
  input1(13) >= input2 
1601 
  input1(14) >= input2 
1601 
  input1(15) >= input2 
1601 
  input1(16) >= input2 
1601 
  input1(17) >= input2 
1601 
  input1(18) >= input2 
1601 
  input1(19) >= input2 
1601 
  input1(20) >= input2 
1601 
  input1(21) >= input2 
1601 
  input1(22) >= input2 
1601 
  input1(23) >= input2 
1601 
  input1(24) >= input2 
1601 
  input1(25) >= input2 
1601 
  input1(26) >= input2 
1601 
  input1(27) >= input2 
1601 
  input1(28) >= input2 
1601 
  input1(29) >= input2 
1601 
  input1(30) >= input2 
1601 
  input1(31) >= input2 
1601 
  input1(32) >= input2 
1601 
  input1(33) >= input2 
1601 
  input1(34) >= input2 
1601 
  input1(35) >= input2 
1601 
  input1(36) >= input2 
1601 
  input1(37) >= input2 
1601 
  input1(38) >= input2 
1601 
  input1(39) >= input2 
1601 
  input1(40) >= input2 
1601 
  input1(41) >= input2 
1601 
  input1(42) >= input2 
1601 
  input1(43) >= input2 
1601 
  input1(44) >= input2 
1601 
  input1(45) >= input2 
1601 
  input1(46) >= input2 
1601 
  input1(47) >= input2 
1601 
  input1(48) >= input2 
1601 
  input1(49) >= input2 
1601 
  input1(50) >= input2 
1601 
  input1(51) >= input2 
1601 
  input1(52) >= input2 
1601 
  input1(53) >= input2 
1601 
  input1(54) >= input2 
1601 
  input1(55) >= input2 
1601 
  input1(56) >= input2 
1601 
  input1(57) >= input2 
1601 
  input1(58) >= input2 
1601 
  input1(59) >= input2 
1601 
  input1(60) >= input2 
1601 
  input1(61) >= input2 
1601 
  input1(62) >= input2 
1601 
  input1(63) >= input2 
1601 
  input1(64) >= input2 
1601 
  input1(65) >= input2 
1601 
  input1(66) >= input2 
1601 
  input1(67) >= input2 
1601 
  input1(68) >= input2 
1601 
  input1(69) >= input2 
1601 
  input1(70) >= input2 
1601 
  input1(71) >= input2 
1601 
  input1(72) >= input2 
1601 
  input1(73) >= input2 
1601 
  input1(74) >= input2 
1601 
  input1(75) >= input2 
1601 
  input1(76) >= input2 
1601 
  input1(77) >= input2 
1601 
  input1(78) >= input2 
1601 
  input1(79) >= input2 
1601 
  input1(80) >= input2 
1601 
  input1(81) >= input2 
1601 
  input1(82) >= input2 
1601 
  input1(83) >= input2 
1601 
  input1(84) >= input2 
1601 
  input1(85) >= input2 
1601 
  input1(86) >= input2 
1601 
  input1(87) >= input2 
1601 
  input1(88) >= input2 
1601 
  input1(89) >= input2 
1601 
  input1(90) >= input2 
1601 
  input1(91) >= input2 
1601 
  input1(92) >= input2 
1601 
  input1(93) >= input2 
1601 
  input1(94) >= input2 
1601 
  input1(95) >= input2 
1601 
  input1(96) >= input2 
1601 
  input1(97) >= input2 
1601 
  input1(98) >= input2 
1601 
  input1(99) >= input2 
1601 
  input1(100) >= input2 
1601 
  input1(101) >= input2 
1601 
  input1(102) >= input2 
1601 
  input1(103) >= input2 
1601 
  input1(104) >= input2 
1601 
  input1(105) >= input2 
1601 
  input1(106) >= input2 
1601 
  input1(107) >= input2 
1601 
  input1(108) >= input2 
1601 
  input1(109) >= input2 
1601 
  input1(110) >= input2 
1601 
  input1(111) >= input2 
1601 
  input1(112) >= input2 
1601 

   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
1601 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (112/224) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) <= input2 
1601 
  input1(2) <= input2 
1601 
  input1(3) <= input2 
1601 
  input1(4) <= input2 
1601 
  input1(5) <= input2 
1601 
  input1(6) <= input2 
1601 
  input1(7) <= input2 
1601 
  input1(8) <= input2 
1601 
  input1(9) <= input2 
1601 
  input1(10) <= input2 
1601 
  input1(11) <= input2 
1601 
  input1(12) <= input2 
1601 
  input1(13) <= input2 
1601 
  input1(14) <= input2 
1601 
  input1(15) <= input2 
1601 
  input1(16) <= input2 
1601 
  input1(17) <= input2 
1601 
  input1(18) <= input2 
1601 
  input1(19) <= input2 
1601 
  input1(20) <= input2 
1601 
  input1(21) <= input2 
1601 
  input1(22) <= input2 
1601 
  input1(23) <= input2 
1601 
  input1(24) <= input2 
1601 
  input1(25) <= input2 
1601 
  input1(26) <= input2 
1601 
  input1(27) <= input2 
1601 
  input1(28) <= input2 
1601 
  input1(29) <= input2 
1601 
  input1(30) <= input2 
1601 
  input1(31) <= input2 
1601 
  input1(32) <= input2 
1601 
  input1(33) <= input2 
1601 
  input1(34) <= input2 
1601 
  input1(35) <= input2 
1601 
  input1(36) <= input2 
1601 
  input1(37) <= input2 
1601 
  input1(38) <= input2 
1601 
  input1(39) <= input2 
1601 
  input1(40) <= input2 
1601 
  input1(41) <= input2 
1601 
  input1(42) <= input2 
1601 
  input1(43) <= input2 
1601 
  input1(44) <= input2 
1601 
  input1(45) <= input2 
1601 
  input1(46) <= input2 
1601 
  input1(47) <= input2 
1601 
  input1(48) <= input2 
1601 
  input1(49) <= input2 
1601 
  input1(50) <= input2 
1601 
  input1(51) <= input2 
1601 
  input1(52) <= input2 
1601 
  input1(53) <= input2 
1601 
  input1(54) <= input2 
1601 
  input1(55) <= input2 
1601 
  input1(56) <= input2 
1601 
  input1(57) <= input2 
1601 
  input1(58) <= input2 
1601 
  input1(59) <= input2 
1601 
  input1(60) <= input2 
1601 
  input1(61) <= input2 
1601 
  input1(62) <= input2 
1601 
  input1(63) <= input2 
1601 
  input1(64) <= input2 
1601 
  input1(65) <= input2 
1601 
  input1(66) <= input2 
1601 
  input1(67) <= input2 
1601 
  input1(68) <= input2 
1601 
  input1(69) <= input2 
1601 
  input1(70) <= input2 
1601 
  input1(71) <= input2 
1601 
  input1(72) <= input2 
1601 
  input1(73) <= input2 
1601 
  input1(74) <= input2 
1601 
  input1(75) <= input2 
1601 
  input1(76) <= input2 
1601 
  input1(77) <= input2 
1601 
  input1(78) <= input2 
1601 
  input1(79) <= input2 
1601 
  input1(80) <= input2 
1601 
  input1(81) <= input2 
1601 
  input1(82) <= input2 
1601 
  input1(83) <= input2 
1601 
  input1(84) <= input2 
1601 
  input1(85) <= input2 
1601 
  input1(86) <= input2 
1601 
  input1(87) <= input2 
1601 
  input1(88) <= input2 
1601 
  input1(89) <= input2 
1601 
  input1(90) <= input2 
1601 
  input1(91) <= input2 
1601 
  input1(92) <= input2 
1601 
  input1(93) <= input2 
1601 
  input1(94) <= input2 
1601 
  input1(95) <= input2 
1601 
  input1(96) <= input2 
1601 
  input1(97) <= input2 
1601 
  input1(98) <= input2 
1601 
  input1(99) <= input2 
1601 
  input1(100) <= input2 
1601 
  input1(101) <= input2 
1601 
  input1(102) <= input2 
1601 
  input1(103) <= input2 
1601 
  input1(104) <= input2 
1601 
  input1(105) <= input2 
1601 
  input1(106) <= input2 
1601 
  input1(107) <= input2 
1601 
  input1(108) <= input2 
1601 
  input1(109) <= input2 
1601 
  input1(110) <= input2 
1601 
  input1(111) <= input2 
1601 
  input1(112) <= input2 
1601 

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
1601 

   Full Coverage

Model Object Metric
Product block "Product1" Execution
Constant block "Constant1" Execution
Constant block "Constant10" Execution
Constant block "Constant11" Execution
Constant block "Constant12" Execution
Constant block "Constant13" Execution
Constant block "Constant14" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution
Constant block "Constant6" Execution
Constant block "Constant7" Execution
Constant block "Constant8" Execution
Constant block "Constant9" Execution
UnitDelay block "Unit Delay5" Execution
UnitDelay block "Unit Delay6" Execution

213. SubSystem block "Counter Reset Enabled "

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 3
Decision NA 50% (2/4) decision outcomes
Execution NA 83% (5/6) objective outcomes

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/Counter Reset Enabled
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/Counter Reset Enabled
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Sum block "Subtraction"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/Counter Reset Enabled
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant Value1" Execution
Constant block "Constant Value2" Execution
UnitDelay block "Unit Delay" Execution

214. SubSystem block "DebounceStartZero1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck
Child Systems: Compare To Zero,  FaultProcess,  HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 14
Condition NA 50% (6/12) condition outcomes
Decision NA 38% (10/26) decision outcomes
Execution NA 78% (25/32) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

215. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (1/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  1601 

216. SubSystem block "FaultProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1
Child Systems: Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 50% (2/4) condition outcomes
Decision NA 33% (4/12) decision outcomes
Execution NA 79% (11/14) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

217. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/FaultProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 50% (1/2) condition outcomes
Decision NA 50% (1/2) decision outcomes
Execution NA 75% (3/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

218. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/FaultProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/FaultProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

219. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/FaultProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 0% (0/4) decision outcomes
Execution NA 0% (0/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 0% (0/4) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  input > lower limit  0%
      false --
      true --
  input >= upper limit  0%
      false --
      true --

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

220. SubSystem block "HealProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1
Child Systems: Compare To Zero,  Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 50% (3/6) condition outcomes
Decision NA 42% (5/12) decision outcomes
Execution NA 73% (11/15) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
Switch block "Switch2" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay1" Execution
UnitDelay block "Unit Delay2" Execution

221. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (1/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/HealProcess/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  1601 

222. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/HealProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 0% (0/2) condition outcomes
Decision NA 0% (0/2) decision outcomes
Execution NA 25% (1/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/HealProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/HealProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 0% (0/2) condition outcomes
Execution 0% (0/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

223. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/HealProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/HealProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

224. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 50% (2/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero1/HealProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 50% (2/4) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input > lower limit  50%
      false 0/1601
      true 1601/1601
  input >= upper limit  50%
      false 1601/1601
      true 0/1601

   Full Coverage

Model Object Metric
Sum block "Add" Execution

225. SubSystem block "DebounceStartZero2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck
Child Systems: Compare To Zero,  FaultProcess,  HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 14
Condition NA 50% (6/12) condition outcomes
Decision NA 38% (10/26) decision outcomes
Execution NA 78% (25/32) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

226. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (1/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  1601 

227. SubSystem block "FaultProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2
Child Systems: Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 50% (2/4) condition outcomes
Decision NA 33% (4/12) decision outcomes
Execution NA 79% (11/14) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

228. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/FaultProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 50% (1/2) condition outcomes
Decision NA 50% (1/2) decision outcomes
Execution NA 75% (3/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

229. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/FaultProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/FaultProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

230. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/FaultProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 0% (0/4) decision outcomes
Execution NA 0% (0/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 0% (0/4) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  input > lower limit  0%
      false --
      true --
  input >= upper limit  0%
      false --
      true --

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

231. SubSystem block "HealProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2
Child Systems: Compare To Zero,  Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 50% (3/6) condition outcomes
Decision NA 42% (5/12) decision outcomes
Execution NA 73% (11/15) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
Switch block "Switch2" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay1" Execution
UnitDelay block "Unit Delay2" Execution

232. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (1/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/HealProcess/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  1601 

233. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/HealProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 0% (0/2) condition outcomes
Decision NA 0% (0/2) decision outcomes
Execution NA 25% (1/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/HealProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/HealProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 0% (0/2) condition outcomes
Execution 0% (0/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

234. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/HealProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/HealProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

235. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 50% (2/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/DebounceStartZero2/HealProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 50% (2/4) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input > lower limit  50%
      false 0/1601
      true 1601/1601
  input >= upper limit  50%
      false 1601/1601
      true 0/1601

   Full Coverage

Model Object Metric
Sum block "Add" Execution

236. SubSystem block "EdgeRising"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 1
Condition NA 50% (3/6) condition outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 100% (3/3) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/EdgeRising
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  1601 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
C1 && ~C2
      C1 (AND In1) (TF) FF
      C2 (OR1 In1) (TF) (TT)


   Logic block "OR1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/EdgeRising
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see AND
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

237. SubSystem block "EdgeRising1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 1
Condition NA 50% (3/6) condition outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 100% (3/3) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/EdgeRising1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  1601 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
C1 && ~C2
      C1 (AND In1) (TF) FF
      C2 (OR1 In1) (TF) (TT)


   Logic block "OR1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/EdgeRising1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see AND
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

238. SubSystem block "EdgeRising2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 1
Condition NA 50% (3/6) condition outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 100% (3/3) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/EdgeRising2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  1601 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
C1 && ~C2
      C1 (AND In1) (TF) FF
      C2 (OR1 In1) (TF) (TT)


   Logic block "OR1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck/EdgeRising2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see AND
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

239. SubSystem block "MaxCellVolt_ForIterator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (4/4) objective outcomes

   Full Coverage

Model Object Metric
ForIterator block "MaxCellVoltNumbIterator" Decision
DataTypeConversion block "Data Type Conversion1" Execution
Sum block "Add" Execution
Selector block "Selector" Execution
UnitDelay block "Unit Delay" Execution

240. SubSystem block "MinCellVolt_ForIterator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (4/4) objective outcomes

   Full Coverage

Model Object Metric
ForIterator block "MaxCellVoltNumbIterator" Decision
DataTypeConversion block "Data Type Conversion1" Execution
Sum block "Add" Execution
Selector block "Selector" Execution
UnitDelay block "Unit Delay" Execution

241. SubSystem block "RunawayVoltGradCheck"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck
Child Systems: CellVoltGrad_ForIterator,  CellVoltGrad_ForIterator1,  Counter Reset Enabled ,  DebounceStartZero1,  DebounceStartZero2,  EdgeRising,  EdgeRising1,  HDP_GbHDP_PackCrntSelfChck_flg,  Unit Delay External IC2,  Unit Delay External IC3,  Unit Delay External IC4

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 43
Condition NA 50% (259/514) condition outcomes
Decision NA 53% (36/68) decision outcomes
MCDC NA 0% (0/12) conditions reversed the outcome
Execution NA 89% (114/128) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical2
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2 
1601 

   Logic block "Logical"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  1601 
  input port 2 
1601 
  input port 3  1601 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) TFT
      input port 3 (TTT) (TTF)


   Logic block "Logical1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 75% (3/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  1101  500 
  input port 2 
1601 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TT) (FT)
      input port 2 (TT) TF


   Logic block "Logical2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  1601 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 3 blocks
Decision/Condition True Out False Out
(C1 || C2) && ~C3
      C1 (AND In1) (TFF) FFF
      C2 (AND In2) (FTF) FFF
      C3 (Logical3 In1) (TTF) (TTT)


   Logic block "Logical3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see Logical2
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (112/224) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) >= input2 
1601 
  input1(2) >= input2 
1601 
  input1(3) >= input2 
1601 
  input1(4) >= input2 
1601 
  input1(5) >= input2 
1601 
  input1(6) >= input2 
1601 
  input1(7) >= input2 
1601 
  input1(8) >= input2 
1601 
  input1(9) >= input2 
1601 
  input1(10) >= input2 
1601 
  input1(11) >= input2 
1601 
  input1(12) >= input2 
1601 
  input1(13) >= input2 
1601 
  input1(14) >= input2 
1601 
  input1(15) >= input2 
1601 
  input1(16) >= input2 
1601 
  input1(17) >= input2 
1601 
  input1(18) >= input2 
1601 
  input1(19) >= input2 
1601 
  input1(20) >= input2 
1601 
  input1(21) >= input2 
1601 
  input1(22) >= input2 
1601 
  input1(23) >= input2 
1601 
  input1(24) >= input2 
1601 
  input1(25) >= input2 
1601 
  input1(26) >= input2 
1601 
  input1(27) >= input2 
1601 
  input1(28) >= input2 
1601 
  input1(29) >= input2 
1601 
  input1(30) >= input2 
1601 
  input1(31) >= input2 
1601 
  input1(32) >= input2 
1601 
  input1(33) >= input2 
1601 
  input1(34) >= input2 
1601 
  input1(35) >= input2 
1601 
  input1(36) >= input2 
1601 
  input1(37) >= input2 
1601 
  input1(38) >= input2 
1601 
  input1(39) >= input2 
1601 
  input1(40) >= input2 
1601 
  input1(41) >= input2 
1601 
  input1(42) >= input2 
1601 
  input1(43) >= input2 
1601 
  input1(44) >= input2 
1601 
  input1(45) >= input2 
1601 
  input1(46) >= input2 
1601 
  input1(47) >= input2 
1601 
  input1(48) >= input2 
1601 
  input1(49) >= input2 
1601 
  input1(50) >= input2 
1601 
  input1(51) >= input2 
1601 
  input1(52) >= input2 
1601 
  input1(53) >= input2 
1601 
  input1(54) >= input2 
1601 
  input1(55) >= input2 
1601 
  input1(56) >= input2 
1601 
  input1(57) >= input2 
1601 
  input1(58) >= input2 
1601 
  input1(59) >= input2 
1601 
  input1(60) >= input2 
1601 
  input1(61) >= input2 
1601 
  input1(62) >= input2 
1601 
  input1(63) >= input2 
1601 
  input1(64) >= input2 
1601 
  input1(65) >= input2 
1601 
  input1(66) >= input2 
1601 
  input1(67) >= input2 
1601 
  input1(68) >= input2 
1601 
  input1(69) >= input2 
1601 
  input1(70) >= input2 
1601 
  input1(71) >= input2 
1601 
  input1(72) >= input2 
1601 
  input1(73) >= input2 
1601 
  input1(74) >= input2 
1601 
  input1(75) >= input2 
1601 
  input1(76) >= input2 
1601 
  input1(77) >= input2 
1601 
  input1(78) >= input2 
1601 
  input1(79) >= input2 
1601 
  input1(80) >= input2 
1601 
  input1(81) >= input2 
1601 
  input1(82) >= input2 
1601 
  input1(83) >= input2 
1601 
  input1(84) >= input2 
1601 
  input1(85) >= input2 
1601 
  input1(86) >= input2 
1601 
  input1(87) >= input2 
1601 
  input1(88) >= input2 
1601 
  input1(89) >= input2 
1601 
  input1(90) >= input2 
1601 
  input1(91) >= input2 
1601 
  input1(92) >= input2 
1601 
  input1(93) >= input2 
1601 
  input1(94) >= input2 
1601 
  input1(95) >= input2 
1601 
  input1(96) >= input2 
1601 
  input1(97) >= input2 
1601 
  input1(98) >= input2 
1601 
  input1(99) >= input2 
1601 
  input1(100) >= input2 
1601 
  input1(101) >= input2 
1601 
  input1(102) >= input2 
1601 
  input1(103) >= input2 
1601 
  input1(104) >= input2 
1601 
  input1(105) >= input2 
1601 
  input1(106) >= input2 
1601 
  input1(107) >= input2 
1601 
  input1(108) >= input2 
1601 
  input1(109) >= input2 
1601 
  input1(110) >= input2 
1601 
  input1(111) >= input2 
1601 
  input1(112) >= input2 
1601 

   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2  1601 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2  1601 

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
1601 

   RelationalOperator block "Comparison5"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
1601 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (112/224) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) == input2 
1601 
  input1(2) == input2 
1601 
  input1(3) == input2 
1601 
  input1(4) == input2 
1601 
  input1(5) == input2 
1601 
  input1(6) == input2 
1601 
  input1(7) == input2 
1601 
  input1(8) == input2 
1601 
  input1(9) == input2 
1601 
  input1(10) == input2 
1601 
  input1(11) == input2 
1601 
  input1(12) == input2 
1601 
  input1(13) == input2 
1601 
  input1(14) == input2 
1601 
  input1(15) == input2 
1601 
  input1(16) == input2 
1601 
  input1(17) == input2 
1601 
  input1(18) == input2 
1601 
  input1(19) == input2 
1601 
  input1(20) == input2 
1601 
  input1(21) == input2 
1601 
  input1(22) == input2 
1601 
  input1(23) == input2 
1601 
  input1(24) == input2 
1601 
  input1(25) == input2 
1601 
  input1(26) == input2 
1601 
  input1(27) == input2 
1601 
  input1(28) == input2 
1601 
  input1(29) == input2 
1601 
  input1(30) == input2 
1601 
  input1(31) == input2 
1601 
  input1(32) == input2 
1601 
  input1(33) == input2 
1601 
  input1(34) == input2 
1601 
  input1(35) == input2 
1601 
  input1(36) == input2 
1601 
  input1(37) == input2 
1601 
  input1(38) == input2 
1601 
  input1(39) == input2 
1601 
  input1(40) == input2 
1601 
  input1(41) == input2 
1601 
  input1(42) == input2 
1601 
  input1(43) == input2 
1601 
  input1(44) == input2 
1601 
  input1(45) == input2 
1601 
  input1(46) == input2 
1601 
  input1(47) == input2 
1601 
  input1(48) == input2 
1601 
  input1(49) == input2 
1601 
  input1(50) == input2 
1601 
  input1(51) == input2 
1601 
  input1(52) == input2 
1601 
  input1(53) == input2 
1601 
  input1(54) == input2 
1601 
  input1(55) == input2 
1601 
  input1(56) == input2 
1601 
  input1(57) == input2 
1601 
  input1(58) == input2 
1601 
  input1(59) == input2 
1601 
  input1(60) == input2 
1601 
  input1(61) == input2 
1601 
  input1(62) == input2 
1601 
  input1(63) == input2 
1601 
  input1(64) == input2 
1601 
  input1(65) == input2 
1601 
  input1(66) == input2 
1601 
  input1(67) == input2 
1601 
  input1(68) == input2 
1601 
  input1(69) == input2 
1601 
  input1(70) == input2 
1601 
  input1(71) == input2 
1601 
  input1(72) == input2 
1601 
  input1(73) == input2 
1601 
  input1(74) == input2 
1601 
  input1(75) == input2 
1601 
  input1(76) == input2 
1601 
  input1(77) == input2 
1601 
  input1(78) == input2 
1601 
  input1(79) == input2 
1601 
  input1(80) == input2 
1601 
  input1(81) == input2 
1601 
  input1(82) == input2 
1601 
  input1(83) == input2 
1601 
  input1(84) == input2 
1601 
  input1(85) == input2 
1601 
  input1(86) == input2 
1601 
  input1(87) == input2 
1601 
  input1(88) == input2 
1601 
  input1(89) == input2 
1601 
  input1(90) == input2 
1601 
  input1(91) == input2 
1601 
  input1(92) == input2 
1601 
  input1(93) == input2 
1601 
  input1(94) == input2 
1601 
  input1(95) == input2 
1601 
  input1(96) == input2 
1601 
  input1(97) == input2 
1601 
  input1(98) == input2 
1601 
  input1(99) == input2 
1601 
  input1(100) == input2 
1601 
  input1(101) == input2 
1601 
  input1(102) == input2 
1601 
  input1(103) == input2 
1601 
  input1(104) == input2 
1601 
  input1(105) == input2 
1601 
  input1(106) == input2 
1601 
  input1(107) == input2 
1601 
  input1(108) == input2 
1601 
  input1(109) == input2 
1601 
  input1(110) == input2 
1601 
  input1(111) == input2 
1601 
  input1(112) == input2 
1601 

   RelationalOperator block "Comparison7"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  1601 

   Full Coverage

Model Object Metric
Product block "Product1" Execution
Sum block "Sum1" Execution
Constant block "Constant1" Execution
Constant block "Constant10" Execution
Constant block "Constant11" Execution
Constant block "Constant12" Execution
Constant block "Constant13" Execution
Constant block "Constant14" Execution
Constant block "Constant15" Execution
Constant block "Constant16" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution
Constant block "Constant6" Execution
Constant block "Constant7" Execution
Constant block "Constant8" Execution
Constant block "Constant9" Execution
UnitDelay block "Unit Delay5" Execution
UnitDelay block "Unit Delay6" Execution

242. SubSystem block "CellVoltGrad_ForIterator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (4/4) objective outcomes

   Full Coverage

Model Object Metric
ForIterator block "MaxCellVoltNumbIterator" Decision
DataTypeConversion block "Data Type Conversion1" Execution
Sum block "Add" Execution
Selector block "Selector" Execution
UnitDelay block "Unit Delay" Execution

243. SubSystem block "CellVoltGrad_ForIterator1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (4/4) objective outcomes

   Full Coverage

Model Object Metric
ForIterator block "MaxCellVoltNumbIterator" Decision
DataTypeConversion block "Data Type Conversion1" Execution
Sum block "Add" Execution
Selector block "Selector" Execution
UnitDelay block "Unit Delay" Execution

244. SubSystem block "Counter Reset Enabled "

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 3
Decision NA 50% (2/4) decision outcomes
Execution NA 83% (5/6) objective outcomes

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/Counter Reset Enabled
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/Counter Reset Enabled
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Sum block "Subtraction"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/Counter Reset Enabled
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant Value1" Execution
Constant block "Constant Value2" Execution
UnitDelay block "Unit Delay" Execution

245. SubSystem block "DebounceStartZero1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck
Child Systems: Compare To Zero,  FaultProcess,  HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 14
Condition NA 50% (6/12) condition outcomes
Decision NA 38% (10/26) decision outcomes
Execution NA 78% (25/32) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

246. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (1/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  1601 

247. SubSystem block "FaultProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1
Child Systems: Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 50% (2/4) condition outcomes
Decision NA 33% (4/12) decision outcomes
Execution NA 79% (11/14) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

248. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/FaultProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 50% (1/2) condition outcomes
Decision NA 50% (1/2) decision outcomes
Execution NA 75% (3/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

249. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/FaultProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/FaultProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

250. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/FaultProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 0% (0/4) decision outcomes
Execution NA 0% (0/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 0% (0/4) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  input > lower limit  0%
      false --
      true --
  input >= upper limit  0%
      false --
      true --

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

251. SubSystem block "HealProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1
Child Systems: Compare To Zero,  Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 50% (3/6) condition outcomes
Decision NA 42% (5/12) decision outcomes
Execution NA 73% (11/15) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
Switch block "Switch2" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay1" Execution
UnitDelay block "Unit Delay2" Execution

252. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (1/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/HealProcess/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  1601 

253. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/HealProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 0% (0/2) condition outcomes
Decision NA 0% (0/2) decision outcomes
Execution NA 25% (1/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/HealProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/HealProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 0% (0/2) condition outcomes
Execution 0% (0/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

254. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/HealProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/HealProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

255. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 50% (2/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero1/HealProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 50% (2/4) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input > lower limit  50%
      false 0/1601
      true 1601/1601
  input >= upper limit  50%
      false 1601/1601
      true 0/1601

   Full Coverage

Model Object Metric
Sum block "Add" Execution

256. SubSystem block "DebounceStartZero2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck
Child Systems: Compare To Zero,  FaultProcess,  HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 14
Condition NA 58% (7/12) condition outcomes
Decision NA 50% (13/26) decision outcomes
Execution NA 81% (26/32) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
UnitDelay block "Unit Delay" Execution

257. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 100% (2/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
RelationalOperator block "Compare" Condition, Execution

258. SubSystem block "FaultProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2
Child Systems: Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 50% (2/4) condition outcomes
Decision NA 58% (7/12) decision outcomes
Execution NA 79% (11/14) objective outcomes

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/FaultProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
Switch block "Switch2" Decision, Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

259. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/FaultProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 0% (0/2) condition outcomes
Decision NA 0% (0/2) decision outcomes
Execution NA 25% (1/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/FaultProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 0% (0/2) condition outcomes
Execution 0% (0/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

260. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/FaultProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/FaultProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

261. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/FaultProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 50% (2/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/FaultProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 50% (2/4) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input > lower limit  50%
      false 0/1601
      true 1601/1601
  input >= upper limit  50%
      false 1601/1601
      true 0/1601

   Full Coverage

Model Object Metric
Sum block "Add" Execution

262. SubSystem block "HealProcess"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2
Child Systems: Compare To Zero,  Decrease,  Increase

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 50% (3/6) condition outcomes
Decision NA 33% (4/12) decision outcomes
Execution NA 80% (12/15) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1100/1100
      true (output is from 1st input port) 0/1100

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/HealProcess
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution
UnitDelay block "Unit Delay1" Execution
UnitDelay block "Unit Delay2" Execution

263. SubSystem block "Compare To Zero"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (1/2) condition outcomes
Execution NA 100% (1/1) objective outcomes

   RelationalOperator block "Compare"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/HealProcess/Compare To Zero
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 
1601 

264. SubSystem block "Decrease"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/HealProcess
Child Systems: Nomal

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 1
Condition NA 50% (1/2) condition outcomes
Decision NA 50% (1/2) decision outcomes
Execution NA 75% (3/4) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/HealProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/HealProcess/Decrease
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant" Execution

265. SubSystem block "Nomal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/HealProcess/Decrease

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/HealProcess/Decrease/Nomal
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

266. SubSystem block "Increase"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/HealProcess

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 0% (0/4) decision outcomes
Execution NA 0% (0/2) objective outcomes

   Saturate block "Saturation"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/HealProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 2
Decision 0% (0/4) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  input > lower limit  0%
      false --
      true --
  input >= upper limit  0%
      false --
      true --

   Sum block "Add"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/DebounceStartZero2/HealProcess/Increase
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

267. SubSystem block "EdgeRising"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 1
Condition NA 50% (3/6) condition outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 100% (3/3) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/EdgeRising
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  1601 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
C1 && ~C2
      C1 (AND In1) (TF) FF
      C2 (OR1 In1) (TF) (TT)


   Logic block "OR1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/EdgeRising
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see AND
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

268. SubSystem block "EdgeRising1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 1
Condition NA 50% (3/6) condition outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 100% (3/3) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/EdgeRising1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  1601 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
C1 && ~C2
      C1 (AND In1) (TF) FF
      C2 (OR1 In1) (TF) (TT)


   Logic block "OR1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/EdgeRising1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see AND
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

269. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck/HDP_GbHDP_PackCrntSelfChck_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

270. SubSystem block "Unit Delay External IC2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

271. SubSystem block "Unit Delay External IC3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

272. SubSystem block "Unit Delay External IC4"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltGradCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 100% (2/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution
UnitDelay block "Unit Delay" Execution
UnitDelay block "Unit Delay1" Execution

273. SubSystem block "RunawayVoltTempCheck"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck
Child Systems: HDP_GbHDP_PackCrntSelfChck_flg,  HDP_GbHDP_PackCrntSelfChck_flg1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 4
Condition NA 60% (41/68) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/24) conditions reversed the outcome
Execution NA 100% (18/18) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltTempCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical6
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2 
1601 

   Logic block "Logical1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltTempCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical6
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2 
1601 

   Logic block "Logical10"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltTempCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 83% (5/6) condition outcomes
MCDC see Logical11
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  355  1246 
  input port 3  1001  600 

   Logic block "Logical11"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltTempCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (4/8) condition outcomes
MCDC 0% (0/12) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2 
1601 
  input port 3 
1601 
  input port 4 
1601 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 5 blocks
Decision/Condition True Out False Out
((((C1 && C2) && C3) || ((C4 && C5) && C6)) || ((C7 && C8) && C9)) || ((C10 && C11) && C12)
      C1 (Logical7 In1) (TTTFFFFFFFFF) (FTTFFFFFFFFF)
      C2 (Logical7 In2) (TTTFFFFFFFFF) (TFTFFFFFFFFF)
      C3 (Logical7 In3) (TTTFFFFFFFFF) (TTFFFFFFFFFF)
      C4 (Logical8 In1) (FFFTTTFFFFFF) (FFFFTTFFFFFF)
      C5 (Logical8 In2) (FFFTTTFFFFFF) (FFFTFTFFFFFF)
      C6 (Logical8 In3) (FFFTTTFFFFFF) (FFFTTFFFFFFF)
      C7 (Logical9 In1) (FFFFFFTTTFFF) (FFFFFFFTTFFF)
      C8 (Logical9 In2) (FFFFFFTTTFTT) FFFFFFTFTFTT
      C9 (Logical9 In3) (FFFFFFTTTFFF) (FFFFFFTTFFFF)
      C10 (Logical10 In1) (FFFFFFTFTTTT) FFFFFFTFFFTT
      C11 (Logical10 In2) (FFFFFFFFFTTT) (FFFFFFFFFTFT)
      C12 (Logical10 In3) (FFFFFFFFFTTT) (FFFFFFFFFTTF)


   Logic block "Logical2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltTempCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical6
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2 
1601 

   Logic block "Logical3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltTempCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 75% (3/4) condition outcomes
MCDC see Logical6
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  355  1246 

   Logic block "Logical4"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltTempCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 75% (3/4) condition outcomes
MCDC see Logical6
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  191  1410 

   Logic block "Logical5"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltTempCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 75% (3/4) condition outcomes
MCDC see Logical6
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  1001  600 

   Logic block "Logical6"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltTempCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (6/12) condition outcomes
MCDC 0% (0/12) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2 
1601 
  input port 3 
1601 
  input port 4 
1601 
  input port 5 
1601 
  input port 6 
1601 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 7 blocks
Decision/Condition True Out False Out
(((((C1 && C2) || (C3 && C4)) || (C5 && C6)) || (C7 && C8)) || (C9 && C10)) || (C11 && C12)
      C1 (Logical In1) (TTFFFFFFFFFF) (FTFFFFFFFFFF)
      C2 (Logical In2) (TTFFFFFFFFFF) (TFFFFFFFFFFF)
      C3 (Logical1 In1) (FFTTFFFFFFFF) (FFFTFFFFFFFF)
      C4 (Logical1 In2) (FFTTFFFFFFFF) (FFTFFFFFFFFF)
      C5 (Logical2 In1) (FFFFTTFFFFFF) (FFFFFTFFFFFF)
      C6 (Logical2 In2) (FFFFTTFFFFFF) (FFFFTFFFFFFF)
      C7 (Logical3 In1) (FFFFFFTTFTFT) FFFFFFFTFFFT
      C8 (Logical3 In2) (FFFFFFTTFFFF) (FFFFFFTFFFFF)
      C9 (Logical4 In1) (FFFFFFFTTTFT) FFFFFFFTFTFT
      C10 (Logical4 In2) (FFFFFFFFTTFF) (FFFFFFFFTFFF)
      C11 (Logical5 In1) (FFFFFFFTFTTT) FFFFFFFFFFFT
      C12 (Logical5 In2) (FFFFFFFFFFTT) (FFFFFFFFFFTF)


   Logic block "Logical7"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltTempCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC see Logical11
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2 
1601 
  input port 3 
1601 

   Logic block "Logical8"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltTempCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC see Logical11
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2 
1601 
  input port 3 
1601 

   Logic block "Logical9"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltTempCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 83% (5/6) condition outcomes
MCDC see Logical11
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  355  1246 
  input port 2 
1601 
  input port 3  191  1410 

274. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltTempCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltTempCheck/HDP_GbHDP_PackCrntSelfChck_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

275. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltTempCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayTempCheck/RunawayVoltTempCheck/RunawayVoltTempCheck/HDP_GbHDP_PackCrntSelfChck_flg1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

276. SubSystem block "RunawayWarnAlarmCheck"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys
Child Systems: ArbRunawayWarnAlarm,  BMSDelay,  CalcSOCPreCond,  EdgeRising,  LongThmRnwyDet,  MaxTempThmRnwyDet,  ReadNVMInitData,  ShortThmRnwyDet,  WriteNVMData

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 128
Condition NA 59% (107/180) condition outcomes
Decision NA 32% (48/148) decision outcomes
MCDC NA 17% (9/52) conditions reversed the outcome
Execution NA 72% (228/316) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant15" Execution
Constant block "Constant18" Execution
Constant block "Constant9" Execution

277. SubSystem block "ArbRunawayWarnAlarm"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck
Child Systems: HDP_GbHDP_PackCrntSelfChck_flg,  HDP_GbHDP_PackCrntSelfChck_flg1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 4
Condition NA 57% (8/14) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 14% (1/7) conditions reversed the outcome
Execution NA 100% (9/9) objective outcomes

   Logic block "Logical1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ArbRunawayWarnAlarm
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2 
1601 
  input port 3 
1601 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TFF) FFF
      input port 2 (FTF) FFF
      input port 3 (FFT) FFF


   Logic block "Logical2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ArbRunawayWarnAlarm
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 63% (5/8) condition outcomes
MCDC 25% (1/4) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2 
1601 
  input port 3 
1601 
  input port 4  191  1410 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TFFF) FFFF
      input port 2 (FTFF) FFFF
      input port 3 (FFTF) FFFF
      input port 4 FFFT FFFF


   Full Coverage

Model Object Metric
Constant block "Constant" Execution

278. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ArbRunawayWarnAlarm

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ArbRunawayWarnAlarm/HDP_GbHDP_PackCrntSelfChck_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

279. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ArbRunawayWarnAlarm

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ArbRunawayWarnAlarm/HDP_GbHDP_PackCrntSelfChck_flg1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

280. SubSystem block "BMSDelay"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck
Child Systems: Unit Delay Resettable

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 4
Condition NA 75% (3/4) condition outcomes
Decision NA 83% (5/6) decision outcomes
Execution NA 100% (7/7) objective outcomes

   Logic block "Logical Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/BMSDelay
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
Sum block "Add" Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution

281. SubSystem block "Unit Delay Resettable"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/BMSDelay

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 75% (3/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Switch block "Reset"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/BMSDelay/Unit Delay Resettable
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution

282. SubSystem block "CalcSOCPreCond"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck
Child Systems: Turn Off Delay Time,  Turn On Delay Time

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 8
Condition NA 76% (35/46) condition outcomes
Decision NA 88% (7/8) decision outcomes
MCDC NA 44% (7/16) conditions reversed the outcome
Execution NA 100% (40/40) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/CalcSOCPreCond
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 75% (3/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  1600 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TT) FT
      input port 2 (TT) (TF)


   Logic block "Logical2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/CalcSOCPreCond
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2 
1601 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TF) FF
      input port 2 (FT) FF


   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/CalcSOCPreCond
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 
1601 

   Full Coverage

Model Object Metric
Logic block "Logical1" Condition, MCDC, Execution
DataTypeConversion block "Data Type Conversion" Execution
DataTypeConversion block "Data Type Conversion1" Execution
DataTypeConversion block "Data Type Conversion2" Execution
DataTypeConversion block "Data Type Conversion3" Execution
RelationalOperator block "Relational Operator1" Condition, Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution
UnitDelay block "Unit Delay1" Execution
UnitDelay block "Unit Delay21" Execution

283. SubSystem block "Turn Off Delay Time"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/CalcSOCPreCond
Child Systems: EdgeFalling1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 4
Condition NA 75% (9/12) condition outcomes
Decision NA 75% (3/4) decision outcomes
MCDC NA 50% (2/4) conditions reversed the outcome
Execution NA 100% (11/11) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/CalcSOCPreCond/Turn Off Delay Time
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 75% (3/4) condition outcomes
MCDC 50% (1/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  400  1201 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TF) FF
      input port 2 FT FF


   MinMax block "Minimum"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/CalcSOCPreCond/Turn Off Delay Time
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  Logic to determine output  50%
      input 1 is the maximum 1600/1600
      input 2 is the maximum 0/1600

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
Sum block "Summation" Execution
RelationalOperator block "Greater Than" Condition, Execution
Constant block "Constant Value1" Execution
Constant block "Constant Value2" Execution
UnitDelay block "Unit Delay" Execution

284. SubSystem block "EdgeFalling1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/CalcSOCPreCond/Turn Off Delay Time

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 1
Condition NA 67% (4/6) condition outcomes
MCDC NA 50% (1/2) conditions reversed the outcome
Execution NA 100% (3/3) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/CalcSOCPreCond/Turn Off Delay Time/EdgeFalling1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 75% (3/4) condition outcomes
MCDC 50% (1/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  1601 
  input port 2  1600 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
~C1 && C2
      C1 (OR1 In1) FT (TT)
      C2 (AND In2) FT FF


   Logic block "OR1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/CalcSOCPreCond/Turn Off Delay Time/EdgeFalling1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see AND
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

285. SubSystem block "Turn On Delay Time"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/CalcSOCPreCond
Child Systems: EdgeRising

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 4
Condition NA 78% (14/18) condition outcomes
Decision NA 100% (4/4) decision outcomes
MCDC NA 50% (3/6) conditions reversed the outcome
Execution NA 100% (12/12) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/CalcSOCPreCond/Turn On Delay Time
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 75% (3/4) condition outcomes
MCDC 50% (1/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  1601 
  input port 2  1501  100 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 TT (FT)
      input port 2 TT TF


   Logic block "OR"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/CalcSOCPreCond/Turn On Delay Time
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 75% (3/4) condition outcomes
MCDC 50% (1/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  1600 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
~C1 || C2
      C1 (OR1 In1) (FF) TF
      C2 (OR In2) TT TF


   Logic block "OR1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/CalcSOCPreCond/Turn On Delay Time
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see OR
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  1601 

   Full Coverage

Model Object Metric
MinMax block "Minimum" Decision, Execution
Switch block "Switch1" Decision, Execution
Sum block "Summation" Execution
RelationalOperator block "Greater Than" Condition, Execution
Constant block "Constant Value1" Execution
UnitDelay block "Unit Delay" Execution

286. SubSystem block "EdgeRising"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/CalcSOCPreCond/Turn On Delay Time

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 1
Condition NA 83% (5/6) condition outcomes
MCDC NA 50% (1/2) conditions reversed the outcome
Execution NA 100% (3/3) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/CalcSOCPreCond/Turn On Delay Time/EdgeRising
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 75% (3/4) condition outcomes
MCDC 50% (1/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  1601 
  input port 2  1600 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
C1 && ~C2
      C1 (AND In1) TF (FF)
      C2 (OR1 In1) TF TT


   Logic block "OR1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/CalcSOCPreCond/Turn On Delay Time/EdgeRising

Metric Coverage
Cyclomatic Complexity 0
Condition 100% (2/2) condition outcomes
MCDC see AND
Execution 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

287. SubSystem block "EdgeRising"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 1
Condition NA 50% (3/6) condition outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 100% (3/3) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/EdgeRising
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  1601 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
C1 && ~C2
      C1 (AND In1) (TF) FF
      C2 (OR1 In1) (TF) (TT)


   Logic block "OR1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/EdgeRising
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see AND
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

288. SubSystem block "LongThmRnwyDet"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck
Child Systems: EdgeRising1,  LongThmRnwyWarnAlrmDet,  OCVSOC_Calc

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 36
Condition NA 50% (9/18) condition outcomes
Decision NA 8% (3/38) decision outcomes
MCDC NA 0% (0/4) conditions reversed the outcome
Execution NA 33% (18/55) objective outcomes

   Logic block "Logical1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 75% (3/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  300  1301 
  input port 2 
1601 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TT) (FT)
      input port 2 (TT) TF


   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant1" Execution

289. SubSystem block "EdgeRising1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 1
Condition NA 50% (3/6) condition outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 100% (3/3) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/EdgeRising1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  1601 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
C1 && ~C2
      C1 (AND In1) (TF) FF
      C2 (OR1 In1) (TF) (TT)


   Logic block "OR1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/EdgeRising1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see AND
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

290. SubSystem block "LongThmRnwyWarnAlrmDet"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet
Child Systems: HDP_GbHDP_PackCrntSelfChck_flg1,  HDP_GbHDP_PackCrntSelfChck_flg2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 4
Condition NA 50% (2/4) condition outcomes
Decision NA 50% (2/4) decision outcomes
Execution NA 100% (10/10) objective outcomes

   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/LongThmRnwyWarnAlrmDet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 
1601 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/LongThmRnwyWarnAlrmDet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant1" Execution
Constant block "Constant3" Execution

291. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/LongThmRnwyWarnAlrmDet

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/LongThmRnwyWarnAlrmDet/HDP_GbHDP_PackCrntSelfChck_flg1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

292. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/LongThmRnwyWarnAlrmDet

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/LongThmRnwyWarnAlrmDet/HDP_GbHDP_PackCrntSelfChck_flg2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

293. SubSystem block "OCVSOC_Calc"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet
Child Systems: 2D_Config_Word1,  2D_Config_Word2,  MinOCVSOC_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 2 31
Condition NA 0% (0/2) condition outcomes
Decision 50% (1/2) decision outcomes 3% (1/34) decision outcomes
Execution NA 5% (2/39) objective outcomes

  Decisions analyzed
  enable logical value  50%
      false 1601/1601
      true 0/1601

   Sum block "Sum1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant1" Execution

294. SubSystem block "2D_Config_Word1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc
Child Systems: Switch Case Action Subsystem,  Switch Case Action Subsystem1,  Switch Case Action Subsystem2,  Switch Case Action Subsystem3,  Switch Case Action Subsystem4,  Switch Case Action Subsystem5,  Switch Case Action Subsystem6,  Switch Case Action Subsystem7,  Switch Case Action Subsystem8,  Switch Case Action Subsystem9

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 11
Decision NA 0% (0/11) decision outcomes
Execution NA 0% (0/12) objective outcomes

   SwitchCase block "Switch Case"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 10
Decision 0% (0/11) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  truncated input  0%
      = Enum_UDSCapSel_Default --
      = Enum_UDSCapSel_CATL153Ah --
      = Enum_UDSCapSel_CATL180Ah --
      = Enum_UDSCapSel_CATL177Ah --
      = Enum_UDSCapSel_CATL203Ah --
      = Enum_UDSCapSel_CATL51Ah --
      = Enum_UDSCapSel_CATL132Ah --
      = Enum_UDSCapSel_XWD75Ah --
      = Enum_UDSCapSel_TFE177Ah --
      = Enum_UDSCapSel_CATLCTP248Ah --
      = implicit-default --

   DataTypeConversion block "Data Type Conversion"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

295. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1/Switch Case Action Subsystem
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

296. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1/Switch Case Action Subsystem1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

297. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1/Switch Case Action Subsystem2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

298. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1/Switch Case Action Subsystem3
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

299. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1/Switch Case Action Subsystem4
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

300. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1/Switch Case Action Subsystem5
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

301. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1/Switch Case Action Subsystem6
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

302. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1/Switch Case Action Subsystem7
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

303. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1/Switch Case Action Subsystem8
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

304. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word1/Switch Case Action Subsystem9
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

305. SubSystem block "2D_Config_Word2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc
Child Systems: Switch Case Action Subsystem,  Switch Case Action Subsystem1,  Switch Case Action Subsystem2,  Switch Case Action Subsystem3,  Switch Case Action Subsystem4,  Switch Case Action Subsystem5,  Switch Case Action Subsystem6,  Switch Case Action Subsystem7,  Switch Case Action Subsystem8,  Switch Case Action Subsystem9

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 11
Decision NA 0% (0/11) decision outcomes
Execution NA 0% (0/12) objective outcomes

   SwitchCase block "Switch Case"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 10
Decision 0% (0/11) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  truncated input  0%
      = Enum_UDSCapSel_Default --
      = Enum_UDSCapSel_CATL153Ah --
      = Enum_UDSCapSel_CATL180Ah --
      = Enum_UDSCapSel_CATL177Ah --
      = Enum_UDSCapSel_CATL203Ah --
      = Enum_UDSCapSel_CATL51Ah --
      = Enum_UDSCapSel_CATL132Ah --
      = Enum_UDSCapSel_XWD75Ah --
      = Enum_UDSCapSel_TFE177Ah --
      = Enum_UDSCapSel_CATLCTP248Ah --
      = implicit-default --

   DataTypeConversion block "Data Type Conversion"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

306. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2/Switch Case Action Subsystem
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

307. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2/Switch Case Action Subsystem1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

308. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2/Switch Case Action Subsystem2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

309. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2/Switch Case Action Subsystem3
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

310. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2/Switch Case Action Subsystem4
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

311. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2/Switch Case Action Subsystem5
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

312. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2/Switch Case Action Subsystem6
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

313. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2/Switch Case Action Subsystem7
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

314. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2/Switch Case Action Subsystem8
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

315. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/2D_Config_Word2/Switch Case Action Subsystem9
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

316. SubSystem block "MinOCVSOC_ForIterator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc
Child Systems: MinCellOCVSOCNumb_ForIterator

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 7
Condition NA 0% (0/2) condition outcomes
Decision NA 0% (0/10) decision outcomes
Execution NA 8% (1/13) objective outcomes

   ForIterator block "MaxCellVoltNumbIterator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes

  Decisions analyzed
  loop condition  0%
      false --
      true --

   DataTypeConversion block "Data Type Conversion"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   Selector block "Selector"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

317. SubSystem block "MinCellOCVSOCNumb_ForIterator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator
Child Systems: Unit Delay External IC1,  Unit Delay External IC2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 0% (0/2) condition outcomes
Decision NA 0% (0/8) decision outcomes
Execution NA 9% (1/11) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 0% (0/2) condition outcomes
Execution 0% (0/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant3" Execution

318. SubSystem block "Unit Delay External IC1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 0% (0/3) objective outcomes

   Switch block "Init"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator/Unit Delay External IC1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   UnitDelay block "Unit Delay"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator/Unit Delay External IC1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator/Unit Delay External IC1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

319. SubSystem block "Unit Delay External IC2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 0% (0/3) objective outcomes

   Switch block "Init"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator/Unit Delay External IC2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   UnitDelay block "Unit Delay"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator/Unit Delay External IC2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/LongThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator/Unit Delay External IC2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

320. SubSystem block "MaxTempThmRnwyDet"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck
Child Systems: BusbarTempDet,  CellTempDet

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 13
Condition NA 65% (17/26) condition outcomes
Decision NA 67% (12/18) decision outcomes
MCDC NA 25% (1/4) conditions reversed the outcome
Execution NA 100% (41/41) objective outcomes

321. SubSystem block "BusbarTempDet"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet
Child Systems: BMSDelay,  HDP_GbHDP_PackCrntSelfChck_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 83% (10/12) condition outcomes
Decision NA 88% (7/8) decision outcomes
MCDC NA 50% (1/2) conditions reversed the outcome
Execution NA 100% (17/17) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet/BusbarTempDet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 75% (3/4) condition outcomes
MCDC 50% (1/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  1601 
  input port 2  1191  410 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 TT (FT)
      input port 2 TT TF


   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet/BusbarTempDet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2  1601 

   Full Coverage

Model Object Metric
RelationalOperator block "Comparison" Condition, Execution
Constant block "Constant1" Execution
Constant block "Constant15" Execution
Constant block "Constant18" Execution
Constant block "Constant2" Execution

322. SubSystem block "BMSDelay"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet/BusbarTempDet
Child Systems: Unit Delay Resettable

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 4
Condition NA 100% (4/4) condition outcomes
Decision NA 100% (6/6) decision outcomes
Execution NA 100% (7/7) objective outcomes

   Full Coverage

Model Object Metric
Logic block "Logical Operator" Condition, Execution
Switch block "Switch" Decision, Execution
Sum block "Add" Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution

323. SubSystem block "Unit Delay Resettable"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet/BusbarTempDet/BMSDelay

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 100% (4/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution
Switch block "Reset" Decision, Execution

324. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet/BusbarTempDet

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet/BusbarTempDet/HDP_GbHDP_PackCrntSelfChck_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

325. SubSystem block "CellTempDet"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet
Child Systems: BMSDelay,  HDP_GbHDP_PackCrntSelfChck_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 7
Condition NA 50% (7/14) condition outcomes
Decision NA 50% (5/10) decision outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 100% (24/24) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet/CellTempDet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  1601 
  input port 2 
1601 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TT) (FT)
      input port 2 (TT) TF


   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet/CellTempDet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Comparison"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet/CellTempDet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
1601 

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet/CellTempDet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2  1601 

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet/CellTempDet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 
1601 

   Full Coverage

Model Object Metric
DataTypeConversion block "Data Type Conversion" Execution
Sum block "Sum" Execution
Constant block "Constant1" Execution
Constant block "Constant15" Execution
Constant block "Constant18" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution

326. SubSystem block "BMSDelay"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet/CellTempDet
Child Systems: Unit Delay Resettable

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 4
Condition NA 50% (2/4) condition outcomes
Decision NA 50% (3/6) decision outcomes
Execution NA 100% (7/7) objective outcomes

   Logic block "Logical Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet/CellTempDet/BMSDelay
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet/CellTempDet/BMSDelay
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet/CellTempDet/BMSDelay
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
1601 

   Full Coverage

Model Object Metric
Sum block "Add" Execution
Constant block "Constant" Execution

327. SubSystem block "Unit Delay Resettable"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet/CellTempDet/BMSDelay

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 50% (2/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Switch block "Init"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet/CellTempDet/BMSDelay/Unit Delay Resettable
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Switch block "Reset"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet/CellTempDet/BMSDelay/Unit Delay Resettable
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

328. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet/CellTempDet

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/MaxTempThmRnwyDet/CellTempDet/HDP_GbHDP_PackCrntSelfChck_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

329. SubSystem block "ReadNVMInitData"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 2 2
Decision 50% (1/2) decision outcomes 50% (1/2) decision outcomes
Execution NA 0% (0/10) objective outcomes

  Decisions analyzed
  enable logical value  50%
      false 1601/1601
      true 0/1601

   DataTypeConversion block "Data Type Conversion"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ReadNVMInitData
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataTypeConversion block "Data Type Conversion1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ReadNVMInitData
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataTypeConversion block "Data Type Conversion2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ReadNVMInitData
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataTypeConversion block "Data Type Conversion3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ReadNVMInitData
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataTypeConversion block "Data Type Conversion5"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ReadNVMInitData
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ReadNVMInitData
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ReadNVMInitData
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ReadNVMInitData
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ReadNVMInitData
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read5"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ReadNVMInitData
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

330. SubSystem block "ShortThmRnwyDet"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck
Child Systems: ArbShortSOCIDFit,  CalcCycleRunTime,  CalcRunTimeSum,  CalcShortMinSOCID,  CalcShortSOCDiff,  EdgeRising,  OCVSOC_Calc,  ShortThmRnwyAlrmDet,  ShortThmRnwyWarnDet

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 58
Condition NA 48% (32/66) condition outcomes
Decision NA 23% (16/70) decision outcomes
MCDC NA 0% (0/19) conditions reversed the outcome
Execution NA 70% (97/138) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 75% (3/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  300  1301 
  input port 2 
1601 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TT) (FT)
      input port 2 (TT) TF


   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution

331. SubSystem block "ArbShortSOCIDFit"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet
Child Systems: HDP_GbHDP_PackCrntSelfChck_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 5
Condition NA 45% (10/22) condition outcomes
Decision NA 38% (3/8) decision outcomes
MCDC NA 0% (0/8) conditions reversed the outcome
Execution NA 89% (16/18) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ArbShortSOCIDFit
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  1601 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TT) FT
      input port 2 (TT) (TF)


   Logic block "Logical1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ArbShortSOCIDFit
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2 
1601 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TF) FF
      input port 2 (FT) FF


   Logic block "Logical2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ArbShortSOCIDFit
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  1601 
  input port 2 
1601 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 TF (FF)
      input port 2 (FT) (FF)


   Logic block "Logical4"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ArbShortSOCIDFit
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2 
1601 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TF) FF
      input port 2 (FT) FF


   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ArbShortSOCIDFit
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ArbShortSOCIDFit
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ArbShortSOCIDFit
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ArbShortSOCIDFit
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  1601 

   RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ArbShortSOCIDFit
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  1601 

   RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ArbShortSOCIDFit
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 0% (0/2) condition outcomes
Execution 0% (0/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant1" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution
UnitDelay block "Unit Delay1" Execution
UnitDelay block "Unit Delay21" Execution

332. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ArbShortSOCIDFit

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ArbShortSOCIDFit/HDP_GbHDP_PackCrntSelfChck_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

333. SubSystem block "CalcCycleRunTime"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet
Child Systems: EdgeBi,  HDP_GbHDP_PackCrntSelfChck_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 50% (2/4) condition outcomes
Decision NA 50% (4/8) decision outcomes
Execution NA 100% (33/33) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcCycleRunTime
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcCycleRunTime
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcCycleRunTime
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcCycleRunTime
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
1601 

   Full Coverage

Model Object Metric
DataTypeConversion block "Data Type Conversion" Execution
DataTypeConversion block "Data Type Conversion1" Execution
DataTypeConversion block "Data Type Conversion2" Execution
DataTypeConversion block "Data Type Conversion3" Execution
DataTypeConversion block "Data Type Conversion4" Execution
DataTypeConversion block "Data Type Conversion5" Execution
DataTypeConversion block "Data Type Conversion6" Execution
Product block "Product" Execution
Product block "Product1" Execution
Product block "Product2" Execution
Sum block "Sum" Execution
Sum block "Sum1" Execution
Sum block "Sum2" Execution
Constant block "Constant1" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution
Constant block "Constant6" Execution
Constant block "Constant7" Execution
Constant block "Constant8" Execution
Constant block "Constant9" Execution
UnitDelay block "Unit Delay1" Execution
UnitDelay block "Unit Delay21" Execution

334. SubSystem block "EdgeBi"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcCycleRunTime

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 1
Condition NA 50% (1/2) condition outcomes
Execution NA 100% (2/2) objective outcomes

   RelationalOperator block "Not Equal"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcCycleRunTime/EdgeBi
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 ~= input2 
1601 

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

335. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcCycleRunTime

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcCycleRunTime/HDP_GbHDP_PackCrntSelfChck_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

336. SubSystem block "CalcRunTimeSum"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet
Child Systems: HDP_GbHDP_PackCrntSelfChck_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Decision NA 50% (2/4) decision outcomes
Execution NA 100% (8/8) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcRunTimeSum
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
DataTypeConversion block "Data Type Conversion" Execution
Sum block "Sum" Execution
Sum block "Sum1" Execution
Constant block "Constant1" Execution

337. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcRunTimeSum

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcRunTimeSum/HDP_GbHDP_PackCrntSelfChck_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

338. SubSystem block "CalcShortMinSOCID"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet
Child Systems: HDP_GbHDP_PackCrntSelfChck_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 4
Condition NA 50% (3/6) condition outcomes
Decision NA 33% (2/6) decision outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 89% (8/9) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcShortMinSOCID
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  1601 
  input port 2 
1601 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TT) (FT)
      input port 2 (TT) TF


   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcShortMinSOCID
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcShortMinSOCID
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   RelationalOperator block "Comparison5"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcShortMinSOCID
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 ~= input2 
1601 

   Full Coverage

Model Object Metric
DataTypeConversion block "Data Type Conversion" Execution
Constant block "Constant2" Execution

339. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcShortMinSOCID

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcShortMinSOCID/HDP_GbHDP_PackCrntSelfChck_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

340. SubSystem block "CalcShortSOCDiff"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet
Child Systems: HDP_GbHDP_PackCrntSelfChck_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 4
Condition NA 50% (3/6) condition outcomes
Decision NA 33% (2/6) decision outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 89% (8/9) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcShortSOCDiff
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  1601 
  input port 2 
1601 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TT) (FT)
      input port 2 (TT) TF


   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcShortSOCDiff
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcShortSOCDiff
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   RelationalOperator block "Comparison5"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcShortSOCDiff
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 ~= input2 
1601 

   Full Coverage

Model Object Metric
DataTypeConversion block "Data Type Conversion" Execution
Constant block "Constant2" Execution

341. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcShortSOCDiff

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/CalcShortSOCDiff/HDP_GbHDP_PackCrntSelfChck_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

342. SubSystem block "EdgeRising"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 1
Condition NA 50% (3/6) condition outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 100% (3/3) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/EdgeRising
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 
  input port 2  1601 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
C1 && ~C2
      C1 (AND In1) (TF) FF
      C2 (OR1 In1) (TF) (TT)


   Logic block "OR1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/EdgeRising
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see AND
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1601 

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

343. SubSystem block "OCVSOC_Calc"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet
Child Systems: 2D_Config_Word1,  2D_Config_Word2,  MinOCVSOC_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 2 31
Condition NA 0% (0/2) condition outcomes
Decision 50% (1/2) decision outcomes 3% (1/34) decision outcomes
Execution NA 5% (2/39) objective outcomes

  Decisions analyzed
  enable logical value  50%
      false 1601/1601
      true 0/1601

   Sum block "Sum1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant1" Execution

344. SubSystem block "2D_Config_Word1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc
Child Systems: Switch Case Action Subsystem,  Switch Case Action Subsystem1,  Switch Case Action Subsystem2,  Switch Case Action Subsystem3,  Switch Case Action Subsystem4,  Switch Case Action Subsystem5,  Switch Case Action Subsystem6,  Switch Case Action Subsystem7,  Switch Case Action Subsystem8,  Switch Case Action Subsystem9

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 11
Decision NA 0% (0/11) decision outcomes
Execution NA 0% (0/12) objective outcomes

   SwitchCase block "Switch Case"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 10
Decision 0% (0/11) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  truncated input  0%
      = Enum_UDSCapSel_Default --
      = Enum_UDSCapSel_CATL153Ah --
      = Enum_UDSCapSel_CATL180Ah --
      = Enum_UDSCapSel_CATL177Ah --
      = Enum_UDSCapSel_CATL203Ah --
      = Enum_UDSCapSel_CATL51Ah --
      = Enum_UDSCapSel_CATL132Ah --
      = Enum_UDSCapSel_XWD75Ah --
      = Enum_UDSCapSel_TFE177Ah --
      = Enum_UDSCapSel_CATLCTP248Ah --
      = implicit-default --

   DataTypeConversion block "Data Type Conversion"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

345. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1/Switch Case Action Subsystem
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

346. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1/Switch Case Action Subsystem1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

347. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1/Switch Case Action Subsystem2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

348. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1/Switch Case Action Subsystem3
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

349. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1/Switch Case Action Subsystem4
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

350. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1/Switch Case Action Subsystem5
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

351. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1/Switch Case Action Subsystem6
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

352. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1/Switch Case Action Subsystem7
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

353. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1/Switch Case Action Subsystem8
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

354. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word1/Switch Case Action Subsystem9
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

355. SubSystem block "2D_Config_Word2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc
Child Systems: Switch Case Action Subsystem,  Switch Case Action Subsystem1,  Switch Case Action Subsystem2,  Switch Case Action Subsystem3,  Switch Case Action Subsystem4,  Switch Case Action Subsystem5,  Switch Case Action Subsystem6,  Switch Case Action Subsystem7,  Switch Case Action Subsystem8,  Switch Case Action Subsystem9

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 11
Decision NA 0% (0/11) decision outcomes
Execution NA 0% (0/12) objective outcomes

   SwitchCase block "Switch Case"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 10
Decision 0% (0/11) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  truncated input  0%
      = Enum_UDSCapSel_Default --
      = Enum_UDSCapSel_CATL153Ah --
      = Enum_UDSCapSel_CATL180Ah --
      = Enum_UDSCapSel_CATL177Ah --
      = Enum_UDSCapSel_CATL203Ah --
      = Enum_UDSCapSel_CATL51Ah --
      = Enum_UDSCapSel_CATL132Ah --
      = Enum_UDSCapSel_XWD75Ah --
      = Enum_UDSCapSel_TFE177Ah --
      = Enum_UDSCapSel_CATLCTP248Ah --
      = implicit-default --

   DataTypeConversion block "Data Type Conversion"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

356. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2/Switch Case Action Subsystem
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

357. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2/Switch Case Action Subsystem1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

358. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2/Switch Case Action Subsystem2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

359. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2/Switch Case Action Subsystem3
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

360. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2/Switch Case Action Subsystem4
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

361. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2/Switch Case Action Subsystem5
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

362. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2/Switch Case Action Subsystem6
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

363. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2/Switch Case Action Subsystem7
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

364. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2/Switch Case Action Subsystem8
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

365. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 0% (0/1) objective outcomes

   Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/2D_Config_Word2/Switch Case Action Subsystem9
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

366. SubSystem block "MinOCVSOC_ForIterator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc
Child Systems: MinCellOCVSOCNumb_ForIterator

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 7
Condition NA 0% (0/2) condition outcomes
Decision NA 0% (0/10) decision outcomes
Execution NA 8% (1/13) objective outcomes

   ForIterator block "MinCellVoltNumbIterator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes

  Decisions analyzed
  loop condition  0%
      false --
      true --

   DataTypeConversion block "Data Type Conversion"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   Selector block "Selector"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

367. SubSystem block "MinCellOCVSOCNumb_ForIterator"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator
Child Systems: Unit Delay External IC1,  Unit Delay External IC2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 0% (0/2) condition outcomes
Decision NA 0% (0/8) decision outcomes
Execution NA 9% (1/11) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Switch block "Switch1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 0% (0/2) condition outcomes
Execution 0% (0/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant3" Execution

368. SubSystem block "Unit Delay External IC1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 0% (0/3) objective outcomes

   Switch block "Init"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator/Unit Delay External IC1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   UnitDelay block "Unit Delay"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator/Unit Delay External IC1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator/Unit Delay External IC1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

369. SubSystem block "Unit Delay External IC2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 0% (0/3) objective outcomes

   Switch block "Init"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator/Unit Delay External IC2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   UnitDelay block "Unit Delay"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator/Unit Delay External IC2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/OCVSOC_Calc/MinOCVSOC_ForIterator/MinCellOCVSOCNumb_ForIterator/Unit Delay External IC2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

370. SubSystem block "ShortThmRnwyAlrmDet"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet
Child Systems: HDP_GbHDP_PackCrntSelfChck_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (1/2) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (11/11) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ShortThmRnwyAlrmDet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  1601 
  input port 2  1601 
  input port 3 
1601 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ShortThmRnwyAlrmDet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2  1601 

   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ShortThmRnwyAlrmDet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2  1601 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ShortThmRnwyAlrmDet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
1601 

   Full Coverage

Model Object Metric
Sum block "Sum1" Execution
Constant block "Constant1" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution

371. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ShortThmRnwyAlrmDet

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ShortThmRnwyAlrmDet/HDP_GbHDP_PackCrntSelfChck_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

372. SubSystem block "ShortThmRnwyWarnDet"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet
Child Systems: HDP_GbHDP_PackCrntSelfChck_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Condition NA 50% (1/2) condition outcomes
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (5/5) objective outcomes

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ShortThmRnwyWarnDet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 
1601 

   Full Coverage

Model Object Metric
Constant block "Constant1" Execution

373. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ShortThmRnwyWarnDet

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck/ShortThmRnwyDet/ShortThmRnwyWarnDet/HDP_GbHDP_PackCrntSelfChck_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 0/1601
      true (output is from 1st input port) 1601/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

374. SubSystem block "WriteNVMData"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/RunawayWarnAlarmCheck

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 2 2
Decision 100% (2/2) decision outcomes 100% (2/2) decision outcomes
Execution NA 100% (10/10) objective outcomes

   Full Coverage

Model Object Metric
DataTypeConversion block "Data Type Conversion" Execution
DataTypeConversion block "Data Type Conversion1" Execution
DataTypeConversion block "Data Type Conversion2" Execution
DataTypeConversion block "Data Type Conversion3" Execution
DataTypeConversion block "Data Type Conversion4" Execution
DataStoreWrite block "Data Store Write" Execution
DataStoreWrite block "Data Store Write1" Execution
DataStoreWrite block "Data Store Write2" Execution
DataStoreWrite block "Data Store Write3" Execution
DataStoreWrite block "Data Store Write5" Execution

375. SubSystem block "TPLWakeUpSet"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys
Child Systems: HDP_GbHDP_PackCrntSelfChck_flg1,  HDP_GbHDP_PackCrntSelfChck_flg2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 5
Condition NA 50% (1/2) condition outcomes
Decision NA 50% (3/6) decision outcomes
Execution NA 100% (25/25) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/TPLWakeUpSet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/TPLWakeUpSet
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 
1601 

   Full Coverage

Model Object Metric
Lookup_n-D block "1-D Lookup Table" Execution
Lookup_n-D block "1-D Lookup Table1" Execution
DataTypeConversion block "Data Type Conversion" Execution
DataTypeConversion block "Data Type Conversion1" Execution
DataTypeConversion block "Data Type Conversion2" Execution
DataTypeConversion block "Data Type Conversion3" Execution
DataTypeConversion block "Data Type Conversion4" Execution
DataTypeConversion block "Data Type Conversion5" Execution
Sum block "Sum" Execution
Constant block "Constant1" Execution
Constant block "Constant15" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution
Constant block "Constant6" Execution
Constant block "Constant7" Execution

376. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg1"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/TPLWakeUpSet

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/TPLWakeUpSet/HDP_GbHDP_PackCrntSelfChck_flg1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

377. SubSystem block "HDP_GbHDP_PackCrntSelfChck_flg2"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/TPLWakeUpSet

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: TRA/TRA/ThemRunAway_10ms/ThemRunAway_10ms_sys/TPLWakeUpSet/HDP_GbHDP_PackCrntSelfChck_flg2
Uncovered Links:  Previous uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1601/1601
      true (output is from 1st input port) 0/1601

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution