Coverage Report for NDP_UT

Table of Contents

  1. Analysis Information
  2. Tests
  3. Summary
  4. Details

Analysis Information

Model Information

  Model version   'M109C113'
  Author   xigkd
  Last saved   Fri Apr 09 18:45:49 2021

Harness information

  Harness model(s)   NDP_UT_Harness
  Harness model owner   NDP_UT

Simulation Optimization Options

  Default parameter behavior   inlined
  Block reduction   forced off
  Conditional branch optimization   on

Coverage Options

  Analyzed model   NDP_UT
  Logic block short circuiting   off
  MCDC mode   masking

Tests

Test# Started execution Ended execution
Test 1 09-Apr-2021 19:59:44 09-Apr-2021 19:59:47

Summary

Model Hierarchy/Complexity Test 1  
Decision Condition MCDC Execution  
1. NDP_UT 749 45%
   
50%
   
0%
   
89%
   
 
2. . . . NDP 743 45%
   
50%
   
0%
   
89%
   
 
3. . . . . . . NvmDataRead_Init 620 48%
   
50%
   
0%
   
100%
   
 
4. . . . . . . . . . NvmDataRead_Init_sys 619 48%
   
50%
   
0%
   
100%
   
 
5. . . . . . . . . . . . . AllCellCap 259 47%
   
50%
   
0%
   
100%
   
 
6. . . . . . . . . . . . . . . . GbNDP_ReadAllCellCapVld_flgOverWrite 2 50%
   
NA NA 100%
   
 
7. . . . . . . . . . . . . . . . NDP_1D_Config_Word 11 9%
   
NA NA 100%
   
 
8. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem   NA NA NA 100%
   
 
9. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem1   NA NA NA 100%
   
 
10. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem2   NA NA NA 100%
   
 
11. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem3   NA NA NA 100%
   
 
12. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem4   NA NA NA 100%
   
 
13. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem5   NA NA NA 100%
   
 
14. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem6   NA NA NA 100%
   
 
15. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem7   NA NA NA 100%
   
 
16. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem8   NA NA NA 100%
   
 
17. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem9   NA NA NA 100%
   
 
18. . . . . . . . . . . . . . . . NDP_1D_Config_Word1 11 9%
   
NA NA 100%
   
 
19. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem   NA NA NA 100%
   
 
20. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem1   NA NA NA 100%
   
 
21. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem2   NA NA NA 100%
   
 
22. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem3   NA NA NA 100%
   
 
23. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem4   NA NA NA 100%
   
 
24. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem5   NA NA NA 100%
   
 
25. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem6   NA NA NA 100%
   
 
26. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem7   NA NA NA 100%
   
 
27. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem8   NA NA NA 100%
   
 
28. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem9   NA NA NA 100%
   
 
29. . . . . . . . . . . . . . . . NDP_1D_Config_Word2 11 9%
   
NA NA 100%
   
 
30. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem   NA NA NA 100%
   
 
31. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem1   NA NA NA 100%
   
 
32. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem2   NA NA NA 100%
   
 
33. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem3   NA NA NA 100%
   
 
34. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem4   NA NA NA 100%
   
 
35. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem5   NA NA NA 100%
   
 
36. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem6   NA NA NA 100%
   
 
37. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem7   NA NA NA 100%
   
 
38. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem8   NA NA NA 100%
   
 
39. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem9   NA NA NA 100%
   
 
40. . . . . . . . . . . . . AllCellOCVSOC 226 50%
   
50%
   
0%
   
100%
   
 
41. . . . . . . . . . . . . . . . NDP_GaNDP_ReadAllCellOCVSOCVld_flg 2 50%
   
NA NA 100%
   
 
42. . . . . . . . . . . . . CellAbsvCap 6 50%
   
50%
   
0%
   
100%
   
 
43. . . . . . . . . . . . . . . . NDP_GbNDP_ReadCellAbsvCapVld_flg 2 50%
   
NA NA 100%
   
 
44. . . . . . . . . . . . . CellChrgDisCap 17 29%
   
50%
   
0%
   
100%
   
 
45. . . . . . . . . . . . . . . . NDP_1D_Config_Word 11 9%
   
NA NA 100%
   
 
46. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem   NA NA NA 100%
   
 
47. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem1   NA NA NA 100%
   
 
48. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem2   NA NA NA 100%
   
 
49. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem3   NA NA NA 100%
   
 
50. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem4   NA NA NA 100%
   
 
51. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem5   NA NA NA 100%
   
 
52. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem6   NA NA NA 100%
   
 
53. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem7   NA NA NA 100%
   
 
54. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem8   NA NA NA 100%
   
 
55. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem9   NA NA NA 100%
   
 
56. . . . . . . . . . . . . . . . NDP_GbNDP_ReadCellChrgDisCapVld_flg 2 50%
   
NA NA 100%
   
 
57. . . . . . . . . . . . . DCNegChrgCtlLoadOpenCnt 3 50%
   
50%
   
0%
   
100%
   
 
58. . . . . . . . . . . . . . . . NDP_GbNDP_ReadACChrgCtlLoadOpenCntVld_flg 2 50%
   
NA NA 100%
   
 
59. . . . . . . . . . . . . DCNegChrgCtlLoadOpenCurr 3 50%
   
50%
   
0%
   
100%
   
 
60. . . . . . . . . . . . . . . . NDP_GbNDP_ReadACChrgCtlLoadOpenCurrVld_flg 2 50%
   
NA NA 100%
   
 
61. . . . . . . . . . . . . DCPosChrgCtlLoadOpenCnt 3 50%
   
50%
   
0%
   
100%
   
 
62. . . . . . . . . . . . . . . . NDP_GbNDP_ReadDCPosChrgCtlLoadOpenCntVld_flg 2 50%
   
NA NA 100%
   
 
63. . . . . . . . . . . . . DCPosChrgCtlLoadOpenCurr 3 50%
   
50%
   
0%
   
100%
   
 
64. . . . . . . . . . . . . . . . NDP_GbNDP_ReadDCPosChrgCtlLoadOpenCurrVld_flg 2 50%
   
NA NA 100%
   
 
65. . . . . . . . . . . . . DispSOC 4 50%
   
50%
   
0%
   
100%
   
 
66. . . . . . . . . . . . . . . . NDP_GbNDP_ReadDispSOCVld_flg 2 50%
   
NA NA 100%
   
 
67. . . . . . . . . . . . . HVIsoValue 3 50%
   
50%
   
0%
   
100%
   
 
68. . . . . . . . . . . . . . . . NDP_GbNDP_ReadHVIsoValueVld_flg 2 50%
   
NA NA 100%
   
 
69. . . . . . . . . . . . . MaxCellSOC 4 50%
   
50%
   
0%
   
100%
   
 
70. . . . . . . . . . . . . . . . NDP_GbNDP_ReadMaxCellSOCVld_flg1 2 50%
   
NA NA 100%
   
 
71. . . . . . . . . . . . . MaxCellVolt 3 50%
   
50%
   
0%
   
100%
   
 
72. . . . . . . . . . . . . . . . NDP_GbNDP_ReadMaxCellVoltVld_flg 2 50%
   
NA NA 100%
   
 
73. . . . . . . . . . . . . MaxPackCurr 3 50%
   
50%
   
0%
   
100%
   
 
74. . . . . . . . . . . . . . . . NDP_GbNDP_ReadMaxPackCurrVld_flg 2 50%
   
NA NA 100%
   
 
75. . . . . . . . . . . . . MinCellSOC 4 50%
   
50%
   
0%
   
100%
   
 
76. . . . . . . . . . . . . . . . NDP_GbNDP_ReadMinCellSOCVld_flg 2 50%
   
NA NA 100%
   
 
77. . . . . . . . . . . . . MinCellVolt 3 50%
   
50%
   
0%
   
100%
   
 
78. . . . . . . . . . . . . . . . NDP_GbNDP_ReadMinCellVoltVld_flg 2 50%
   
NA NA 100%
   
 
79. . . . . . . . . . . . . NDP_GbNDP_ReadShutdownTimeVld_flg 2 50%
   
NA NA 100%
   
 
80. . . . . . . . . . . . . NVMOCVCorrdSign 4 50%
   
50%
   
0%
   
100%
   
 
81. . . . . . . . . . . . . . . . NDP_GbNDP_ReadNVMOCVCorrdSignVld_flg 2 50%
   
NA NA 100%
   
 
82. . . . . . . . . . . . . NVMOCVCorrdSumTi 4 50%
   
50%
   
0%
   
100%
   
 
83. . . . . . . . . . . . . . . . NDP_GbNDP_ReadNVMOCVCorrdSumTiVld_flg 2 50%
   
NA NA 100%
   
 
84. . . . . . . . . . . . . NVMPreChrgFail 4 50%
   
50%
   
0%
   
100%
   
 
85. . . . . . . . . . . . . . . . NDP_GbNDP_ReadNVMPreChrgFailVld_flg 2 50%
   
NA NA 100%
   
 
86. . . . . . . . . . . . . NVMVld_State   NA 50%
   
0%
   
100%
   
 
87. . . . . . . . . . . . . NegCtlLoadOpenCnt 3 50%
   
50%
   
0%
   
100%
   
 
88. . . . . . . . . . . . . . . . NDP_GbNDP_ReadNegCtlLoadOpenCntVld_flg 2 50%
   
NA NA 100%
   
 
89. . . . . . . . . . . . . NegCtlLoadOpenCurr 3 50%
   
50%
   
0%
   
100%
   
 
90. . . . . . . . . . . . . . . . NDP_GbNDP_ReadNegCtlLoadOpenCurrVld_flg 2 50%
   
NA NA 100%
   
 
91. . . . . . . . . . . . . PosCtlLoadOpenCnt 3 50%
   
50%
   
0%
   
100%
   
 
92. . . . . . . . . . . . . . . . NDP_GbNDP_ReadPosCtlLoadOpenCntVld_flg 2 50%
   
NA NA 100%
   
 
93. . . . . . . . . . . . . PosCtlLoadOpenCurr 3 50%
   
50%
   
0%
   
100%
   
 
94. . . . . . . . . . . . . . . . NDP_GbNDP_ReadPosCtlLoadOpenCurrVld_flg 2 50%
   
NA NA 100%
   
 
95. . . . . . . . . . . . . SOCCorrdMaxCellVolt 3 50%
   
50%
   
0%
   
100%
   
 
96. . . . . . . . . . . . . . . . NDP_GbNDP_ReadSOCCorrdMaxCellVoltVld_flg 2 50%
   
NA NA 100%
   
 
97. . . . . . . . . . . . . SOCCorrdMinCellVolt 3 50%
   
50%
   
0%
   
100%
   
 
98. . . . . . . . . . . . . . . . NDP_GbNDP_ReadSOCCorrdMinCellVoltVld_flg 2 50%
   
NA NA 100%
   
 
99. . . . . . . . . . . . . SOH2 4 50%
   
50%
   
0%
   
100%
   
 
100. . . . . . . . . . . . . . . . NDP_GbNDP_ReadMaxCellSOCVld_flg1 2 50%
   
NA NA 100%
   
 
101. . . . . . . . . . . . . SOH3 4 50%
   
50%
   
0%
   
100%
   
 
102. . . . . . . . . . . . . . . . NDP_GbNDP_ReadMaxCellSOCVld_flg1 2 50%
   
NA NA 100%
   
 
103. . . . . . . . . . . . . ShutdownTimeDay 3 50%
   
50%
   
0%
   
100%
   
 
104. . . . . . . . . . . . . . . . NDP_GbNDP_ReadTotalDischrgPwrVld_flg 2 50%
   
NA NA 100%
   
 
105. . . . . . . . . . . . . ShutdownTimeHr 3 50%
   
50%
   
0%
   
100%
   
 
106. . . . . . . . . . . . . . . . NDP_GbNDP_ReadTotalDischrgPwrVld_flg 2 50%
   
NA NA 100%
   
 
107. . . . . . . . . . . . . ShutdownTimeMint 3 50%
   
50%
   
0%
   
100%
   
 
108. . . . . . . . . . . . . . . . NDP_GbNDP_ReadTotalDischrgPwrVld_flg 2 50%
   
NA NA 100%
   
 
109. . . . . . . . . . . . . ShutdownTimeMonth 3 50%
   
50%
   
0%
   
100%
   
 
110. . . . . . . . . . . . . . . . NDP_GbNDP_ReadTotalDischrgPwrVld_flg 2 50%
   
NA NA 100%
   
 
111. . . . . . . . . . . . . ShutdownTimeSec 3 50%
   
50%
   
0%
   
100%
   
 
112. . . . . . . . . . . . . . . . NDP_GbNDP_ReadTotalDischrgPwrVld_flg 2 50%
   
NA NA 100%
   
 
113. . . . . . . . . . . . . ShutdownTimeSec1 3 50%
   
50%
   
0%
   
100%
   
 
114. . . . . . . . . . . . . . . . NDP_GbNDP_ReadTotalDischrgPwrVld_flg 2 50%
   
NA NA 100%
   
 
115. . . . . . . . . . . . . ShutdownTimeYr 3 50%
   
50%
   
0%
   
100%
   
 
116. . . . . . . . . . . . . . . . NDP_GbNDP_ReadTotalDischrgPwrVld_flg 2 50%
   
NA NA 100%
   
 
117. . . . . . . . . . . . . TotalChrgCap 3 50%
   
50%
   
0%
   
100%
   
 
118. . . . . . . . . . . . . . . . NDP_GbNDP_ReadTotalChrgCapVld_flg 2 50%
   
NA NA 100%
   
 
119. . . . . . . . . . . . . TotalChrgPwr 3 50%
   
50%
   
0%
   
100%
   
 
120. . . . . . . . . . . . . . . . NDP_GbNDP_ReadTotalChrgPwrVld_flg 2 50%
   
NA NA 100%
   
 
121. . . . . . . . . . . . . TotalDischrgCap 3 50%
   
50%
   
0%
   
100%
   
 
122. . . . . . . . . . . . . . . . NDP_GbNDP_ReadTotalDischrgCapVld_flg 2 50%
   
NA NA 100%
   
 
123. . . . . . . . . . . . . TotalDischrgPwr 3 50%
   
50%
   
0%
   
100%
   
 
124. . . . . . . . . . . . . . . . NDP_GbNDP_ReadTotalDischrgPwrVld_flg 2 50%
   
NA NA 100%
   
 
125. . . . . . . . . . . . . bNDP_NVMDatStrFlt_flgOverWrite 2 50%
   
NA NA 100%
   
 
126. . . . . . . NvmDataWrite_10ms 123 7%
   
50%
   
0%
   
58%
   
 
127. . . . . . . . . . NvmDataWrite_10ms_sys 122 6%
   
50%
   
0%
   
57%
   
 
128. . . . . . . . . . . . . NDP_GbNDP_ShutDowmNvmChange_flg 2 50%
   
NA NA 100%
   
 
129. . . . . . . . . . . . . RunNvmDataWrite_10ms 26 4%
   
NA NA 50%
   
 
130. . . . . . . . . . . . . . . . NDP_GaNDP_RunAllCellCap_Ah 2 0%
   
NA NA 67%
   
 
131. . . . . . . . . . . . . . . . NDP_GaNDP_RunAllCellOCVSOC_pct 2 0%
   
NA NA 67%
   
 
132. . . . . . . . . . . . . . . . NDP_GcNDP_RunCellAbsvCap_Ah 2 0%
   
NA NA 67%
   
 
133. . . . . . . . . . . . . . . . NDP_GcNDP_RunCellAbsvCap_Ah1 2 0%
   
NA NA 67%
   
 
134. . . . . . . . . . . . . . . . NDP_GcNDP_RunCellAbsvCap_Ah2 2 0%
   
NA NA 67%
   
 
135. . . . . . . . . . . . . . . . NDP_GcNDP_RunCellChrgDisCap_Ah 2 0%
   
NA NA 67%
   
 
136. . . . . . . . . . . . . . . . NDP_GcNDP_RunDispSOC_pct 2 0%
   
NA NA 67%
   
 
137. . . . . . . . . . . . . . . . NDP_GcNDP_RunMaxCellSOC_pct 2 0%
   
NA NA 67%
   
 
138. . . . . . . . . . . . . . . . NDP_GcNDP_RunMinCellSOC_pct 2 0%
   
NA NA 67%
   
 
139. . . . . . . . . . . . . . . . NDP_GcNDP_RunNVMOCVCorrdSign_numb 2 0%
   
NA NA 67%
   
 
140. . . . . . . . . . . . . . . . NDP_GcNDP_RunNVMOCVCorrdSumTi_ms 2 0%
   
NA NA 67%
   
 
141. . . . . . . . . . . . . . . . NDP_GcNDP_RunNVMPreChrgFail_numb 2 0%
   
NA NA 67%
   
 
142. . . . . . . . . . . . . RunNvmDataWrite_flg 18 57%
   
50%
   
0%
   
100%
   
 
143. . . . . . . . . . . . . . . . EdgeRising2 1 NA 50%
   
0%
   
100%
   
 
144. . . . . . . . . . . . . . . . EdgeRising3 1 NA 50%
   
0%
   
100%
   
 
145. . . . . . . . . . . . . . . . EdgeRising4 1 NA 50%
   
0%
   
100%
   
 
146. . . . . . . . . . . . . . . . NDP_GbNDP_RunNvmChange_flg 2 50%
   
NA NA 100%
   
 
147. . . . . . . . . . . . . . . . RunNVMStore 13 60%
   
50%
   
0%
   
NA  
148. . . . . . . . . . . . . . . . . . . SF: NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg/RunNVMStore 12 60%
   
50%
   
0%
   
NA  
149. . . . . . . . . . . . . ShutDownNvmDataWrite_10ms 76 1%
   
NA NA 50%
   
 
150. . . . . . . . . . . . . . . . NDP_GaNDP_ShutDownAllCellCap_Ah 2 0%
   
NA NA 67%
   
 
151. . . . . . . . . . . . . . . . NDP_GaNDP_ShutDownAllCellOCVSOC_pct 2 0%
   
NA NA 67%
   
 
152. . . . . . . . . . . . . . . . NDP_GcNDP_RunCellAbsvCap_Ah1 2 0%
   
NA NA 67%
   
 
153. . . . . . . . . . . . . . . . NDP_GcNDP_RunCellAbsvCap_Ah2 2 0%
   
NA NA 67%
   
 
154. . . . . . . . . . . . . . . . NDP_GcNDP_RunCellAbsvCap_Ah3 2 0%
   
NA NA 67%
   
 
155. . . . . . . . . . . . . . . . NDP_GcNDP_RunCellAbsvCap_Ah4 2 0%
   
NA NA 67%
   
 
156. . . . . . . . . . . . . . . . NDP_GcNDP_RunCellAbsvCap_Ah5 2 0%
   
NA NA 67%
   
 
157. . . . . . . . . . . . . . . . NDP_GcNDP_RunCellAbsvCap_Ah6 2 0%
   
NA NA 67%
   
 
158. . . . . . . . . . . . . . . . NDP_GcNDP_RunCellAbsvCap_Ah7 2 0%
   
NA NA 67%
   
 
159. . . . . . . . . . . . . . . . NDP_GcNDP_RunCellAbsvCap_Ah8 2 0%
   
NA NA 67%
   
 
160. . . . . . . . . . . . . . . . NDP_GcNDP_RunCellAbsvCap_Ah9 2 0%
   
NA NA 67%
   
 
161. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownCellAbsvCap_Ah 2 0%
   
NA NA 67%
   
 
162. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownCellChrgDisCap_Ah 2 0%
   
NA NA 67%
   
 
163. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownDCNegChrgCtlLoadOpenCnt_numb 2 0%
   
NA NA 67%
   
 
164. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownDCNegChrgCtlLoadOpenCurr_A 2 0%
   
NA NA 67%
   
 
165. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownDCPosChrgCtlLoadOpenCnt_numb 2 0%
   
NA NA 67%
   
 
166. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownDCPosChrgCtlLoadOpenCurr_A 2 0%
   
NA NA 67%
   
 
167. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownDispSOC_pct 2 0%
   
NA NA 67%
   
 
168. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownHVIsoValue_kohm 2 0%
   
NA NA 67%
   
 
169. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownMaxCellSOC_pct 2 0%
   
NA NA 67%
   
 
170. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownMaxCellVolt_mV 2 0%
   
NA NA 67%
   
 
171. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownMaxPackCurr_A 2 0%
   
NA NA 67%
   
 
172. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownMinCellSOC_pct 2 0%
   
NA NA 67%
   
 
173. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownMinCellVolt_mV 2 0%
   
NA NA 67%
   
 
174. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownNVMOCVCorrdSign_numb 2 0%
   
NA NA 67%
   
 
175. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownNVMOCVCorrdSumTi_ms 2 0%
   
NA NA 67%
   
 
176. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownNVMPreChrgFail_numb 2 0%
   
NA NA 67%
   
 
177. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownNegCtlLoadOpenCnt_numb 2 0%
   
NA NA 67%
   
 
178. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownNegCtlLoadOpenCurr_A 2 0%
   
NA NA 67%
   
 
179. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownPosCtlLoadOpenCnt_numb 2 0%
   
NA NA 67%
   
 
180. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownPosCtlLoadOpenCurr_A 2 0%
   
NA NA 67%
   
 
181. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownSOCCorrdMaxCellVolt_mV 2 0%
   
NA NA 67%
   
 
182. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownSOCCorrdMinCellVolt_mV 2 0%
   
NA NA 67%
   
 
183. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownTotalChrgCap_Ah 2 0%
   
NA NA 67%
   
 
184. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownTotalChrgPwr_kWh 2 0%
   
NA NA 67%
   
 
185. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownTotalDischrgCap_Ah 2 0%
   
NA NA 67%
   
 
186. . . . . . . . . . . . . . . . NDP_GcNDP_ShutDownTotalDischrgPwr_kWh 2 0%
   
NA NA 67%
   
 

Details

1. Model "NDP_UT"

Child Systems: NDP

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 749
Condition NA 50% (2854/5708) condition outcomes
Decision NA 45% (549/1229) decision outcomes
MCDC NA 0% (0/2242) conditions reversed the outcome
Execution NA 89% (817/915) objective outcomes

   Full Coverage

Model Object Metric
Gain block "Gain" Execution
Gain block "Gain1" Execution
Gain block "Gain2" Execution
Gain block "Gain3" Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution

2. SubSystem block "NDP"

Justify or Exclude
Parent: /NDP_UT
Child Systems: NvmDataRead_Init,  NvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 743
Condition NA 50% (2854/5708) condition outcomes
Decision NA 45% (549/1229) decision outcomes
MCDC NA 0% (0/2242) conditions reversed the outcome
Execution NA 89% (808/906) objective outcomes

3. SubSystem block "NvmDataRead_Init"

Justify or Exclude
Parent: NDP_UT/NDP
Child Systems: NvmDataRead_Init_sys

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 620
Condition NA 50% (2827/5654) condition outcomes
Decision 100% (1/1) decision outcomes 48% (541/1117) decision outcomes
MCDC NA 0% (0/2222) conditions reversed the outcome
Execution NA 100% (675/675) objective outcomes

  Decisions analyzed
  Function call  100%
      executed 1/1

   Full Coverage

Model Object Metric
SignalConversion block "Signal Conversion" Execution
SignalConversion block "Signal Conversion1" Execution

4. SubSystem block "NvmDataRead_Init_sys"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init
Child Systems: AllCellCap,  AllCellOCVSOC,  CellAbsvCap,  CellChrgDisCap,  DCNegChrgCtlLoadOpenCnt,  DCNegChrgCtlLoadOpenCurr,  DCPosChrgCtlLoadOpenCnt,  DCPosChrgCtlLoadOpenCurr,  DispSOC,  HVIsoValue,  MaxCellSOC,  MaxCellVolt,  MaxPackCurr,  MinCellSOC,  MinCellVolt,  NDP_GbNDP_ReadShutdownTimeVld_flg,  NVMOCVCorrdSign,  NVMOCVCorrdSumTi,  NVMPreChrgFail,  NVMVld_State,  NegCtlLoadOpenCnt,  NegCtlLoadOpenCurr,  PosCtlLoadOpenCnt,  PosCtlLoadOpenCurr,  SOCCorrdMaxCellVolt,  SOCCorrdMinCellVolt,  SOH2,  SOH3,  ShutdownTimeDay,  ShutdownTimeHr,  ShutdownTimeMint,  ShutdownTimeMonth,  ShutdownTimeSec,  ShutdownTimeSec1,  ShutdownTimeYr,  TotalChrgCap,  TotalChrgPwr,  TotalDischrgCap,  TotalDischrgPwr,  bNDP_NVMDatStrFlt_flgOverWrite

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 619
Condition NA 50% (2827/5654) condition outcomes
Decision NA 48% (540/1116) decision outcomes
MCDC NA 0% (0/2222) conditions reversed the outcome
Execution NA 100% (673/673) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Uncovered Links:  Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (112/224) condition outcomes
MCDC 0% (0/112) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port1(1) 
  input port1(2) 
  input port1(3) 
  input port1(4) 
  input port1(5) 
  input port1(6) 
  input port1(7) 
  input port1(8) 
  input port1(9) 
  input port1(10) 
  input port1(11) 
  input port1(12) 
  input port1(13) 
  input port1(14) 
  input port1(15) 
  input port1(16) 
  input port1(17) 
  input port1(18) 
  input port1(19) 
  input port1(20) 
  input port1(21) 
  input port1(22) 
  input port1(23) 
  input port1(24) 
  input port1(25) 
  input port1(26) 
  input port1(27) 
  input port1(28) 
  input port1(29) 
  input port1(30) 
  input port1(31) 
  input port1(32) 
  input port1(33) 
  input port1(34) 
  input port1(35) 
  input port1(36) 
  input port1(37) 
  input port1(38) 
  input port1(39) 
  input port1(40) 
  input port1(41) 
  input port1(42) 
  input port1(43) 
  input port1(44) 
  input port1(45) 
  input port1(46) 
  input port1(47) 
  input port1(48) 
  input port1(49) 
  input port1(50) 
  input port1(51) 
  input port1(52) 
  input port1(53) 
  input port1(54) 
  input port1(55) 
  input port1(56) 
  input port1(57) 
  input port1(58) 
  input port1(59) 
  input port1(60) 
  input port1(61) 
  input port1(62) 
  input port1(63) 
  input port1(64) 
  input port1(65) 
  input port1(66) 
  input port1(67) 
  input port1(68) 
  input port1(69) 
  input port1(70) 
  input port1(71) 
  input port1(72) 
  input port1(73) 
  input port1(74) 
  input port1(75) 
  input port1(76) 
  input port1(77) 
  input port1(78) 
  input port1(79) 
  input port1(80) 
  input port1(81) 
  input port1(82) 
  input port1(83) 
  input port1(84) 
  input port1(85) 
  input port1(86) 
  input port1(87) 
  input port1(88) 
  input port1(89) 
  input port1(90) 
  input port1(91) 
  input port1(92) 
  input port1(93) 
  input port1(94) 
  input port1(95) 
  input port1(96) 
  input port1(97) 
  input port1(98) 
  input port1(99) 
  input port1(100) 
  input port1(101) 
  input port1(102) 
  input port1(103) 
  input port1(104) 
  input port1(105) 
  input port1(106) 
  input port1(107) 
  input port1(108) 
  input port1(109) 
  input port1(110) 
  input port1(111) 
  input port1(112) 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port1(1) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (FTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(2) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(3) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(4) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(5) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(6) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(7) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(8) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(9) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(10) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(11) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(12) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(13) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(14) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(15) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(16) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(17) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(18) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(19) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(20) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(21) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(22) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(23) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(24) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(25) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(26) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(27) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(28) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(29) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(30) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(31) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(32) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(33) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(34) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(35) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(36) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(37) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(38) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(39) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(40) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(41) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(42) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(43) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(44) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(45) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(46) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(47) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(48) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(49) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(50) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(51) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(52) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(53) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(54) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(55) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(56) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(57) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(58) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(59) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(60) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(61) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(62) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(63) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(64) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(65) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(66) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(67) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(68) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(69) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(70) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(71) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(72) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(73) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(74) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(75) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(76) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(77) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(78) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(79) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(80) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(81) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(82) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(83) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(84) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(85) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(86) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(87) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(88) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(89) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(90) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTT)
      input port1(91) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTT)
      input port1(92) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTT)
      input port1(93) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTT)
      input port1(94) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTT)
      input port1(95) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTT)
      input port1(96) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTT)
      input port1(97) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTT)
      input port1(98) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTT)
      input port1(99) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTT)
      input port1(100) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTT)
      input port1(101) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTT)
      input port1(102) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTT)
      input port1(103) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTT)
      input port1(104) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTT)
      input port1(105) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTT)
      input port1(106) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTT)
      input port1(107) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTT)
      input port1(108) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTT)
      input port1(109) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTT)
      input port1(110) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTT)
      input port1(111) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFT)
      input port1(112) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTF)


   Logic block "Logical1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (37/74) condition outcomes
MCDC 0% (0/37) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 
  input port 4 
  input port 5 
  input port 6 
  input port 7 
  input port 8 
  input port 9 
  input port 10 
  input port 11 
  input port 12 
  input port 13 
  input port 14 
  input port 15 
  input port 16 
  input port 17 
  input port 18 
  input port 19 
  input port 20 
  input port 21 
  input port 22 
  input port 23 
  input port 24 
  input port 25 
  input port 26 
  input port 27 
  input port 28 
  input port 29 
  input port 30 
  input port 31 
  input port 32 
  input port 33 
  input port 34 
  input port 35 
  input port 36 
  input port 37 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (FTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 2 (TFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 3 (TTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 4 (TTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 5 (TTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 6 (TTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 7 (TTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 8 (TTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 9 (TTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 10 (TTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 11 (TTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 12 (TTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 13 (TTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 14 (TTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 15 (TTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 16 (TTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 17 (TTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 18 (TTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 19 (TTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 20 (TTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 21 (TTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 22 (TTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 23 (TTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 24 (TTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 25 (TTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 26 (TTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 27 (TTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 28 (TTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 29 (TTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 30 (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 31 (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 32 (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 33 (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 34 (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 35 (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 36 (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port 37 (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTF) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)


   Logic block "Logical2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (112/224) condition outcomes
MCDC 0% (0/112) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port1(1) 
  input port1(2) 
  input port1(3) 
  input port1(4) 
  input port1(5) 
  input port1(6) 
  input port1(7) 
  input port1(8) 
  input port1(9) 
  input port1(10) 
  input port1(11) 
  input port1(12) 
  input port1(13) 
  input port1(14) 
  input port1(15) 
  input port1(16) 
  input port1(17) 
  input port1(18) 
  input port1(19) 
  input port1(20) 
  input port1(21) 
  input port1(22) 
  input port1(23) 
  input port1(24) 
  input port1(25) 
  input port1(26) 
  input port1(27) 
  input port1(28) 
  input port1(29) 
  input port1(30) 
  input port1(31) 
  input port1(32) 
  input port1(33) 
  input port1(34) 
  input port1(35) 
  input port1(36) 
  input port1(37) 
  input port1(38) 
  input port1(39) 
  input port1(40) 
  input port1(41) 
  input port1(42) 
  input port1(43) 
  input port1(44) 
  input port1(45) 
  input port1(46) 
  input port1(47) 
  input port1(48) 
  input port1(49) 
  input port1(50) 
  input port1(51) 
  input port1(52) 
  input port1(53) 
  input port1(54) 
  input port1(55) 
  input port1(56) 
  input port1(57) 
  input port1(58) 
  input port1(59) 
  input port1(60) 
  input port1(61) 
  input port1(62) 
  input port1(63) 
  input port1(64) 
  input port1(65) 
  input port1(66) 
  input port1(67) 
  input port1(68) 
  input port1(69) 
  input port1(70) 
  input port1(71) 
  input port1(72) 
  input port1(73) 
  input port1(74) 
  input port1(75) 
  input port1(76) 
  input port1(77) 
  input port1(78) 
  input port1(79) 
  input port1(80) 
  input port1(81) 
  input port1(82) 
  input port1(83) 
  input port1(84) 
  input port1(85) 
  input port1(86) 
  input port1(87) 
  input port1(88) 
  input port1(89) 
  input port1(90) 
  input port1(91) 
  input port1(92) 
  input port1(93) 
  input port1(94) 
  input port1(95) 
  input port1(96) 
  input port1(97) 
  input port1(98) 
  input port1(99) 
  input port1(100) 
  input port1(101) 
  input port1(102) 
  input port1(103) 
  input port1(104) 
  input port1(105) 
  input port1(106) 
  input port1(107) 
  input port1(108) 
  input port1(109) 
  input port1(110) 
  input port1(111) 
  input port1(112) 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port1(1) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (FTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(2) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(3) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(4) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(5) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(6) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(7) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(8) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(9) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(10) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(11) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(12) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(13) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(14) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(15) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(16) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(17) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(18) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(19) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(20) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(21) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(22) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(23) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(24) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(25) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(26) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(27) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(28) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(29) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(30) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(31) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(32) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(33) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(34) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(35) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(36) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(37) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(38) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(39) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(40) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(41) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(42) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(43) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(44) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(45) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(46) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(47) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(48) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(49) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(50) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(51) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(52) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(53) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(54) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(55) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(56) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(57) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(58) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(59) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(60) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(61) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(62) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(63) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(64) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(65) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(66) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(67) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(68) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(69) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(70) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(71) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(72) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(73) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(74) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(75) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(76) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(77) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(78) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(79) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(80) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(81) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(82) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(83) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(84) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(85) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(86) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(87) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(88) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(89) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTTT)
      input port1(90) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTTT)
      input port1(91) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTTT)
      input port1(92) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTTT)
      input port1(93) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTTT)
      input port1(94) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTTT)
      input port1(95) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTTT)
      input port1(96) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTTT)
      input port1(97) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTTT)
      input port1(98) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTTT)
      input port1(99) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTTT)
      input port1(100) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTTT)
      input port1(101) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTTT)
      input port1(102) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTTT)
      input port1(103) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTTT)
      input port1(104) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTTT)
      input port1(105) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTTT)
      input port1(106) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTTT)
      input port1(107) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTTT)
      input port1(108) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTTT)
      input port1(109) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTTT)
      input port1(110) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFTT)
      input port1(111) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTFT)
      input port1(112) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT) (TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTF)


   Logic block "Logical3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (6/12) condition outcomes
MCDC 0% (0/6) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 
  input port 4 
  input port 5 
  input port 6 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTTTTT) (FTTTTT)
      input port 2 (TTTTTT) (TFTTTT)
      input port 3 (TTTTTT) (TTFTTT)
      input port 4 (TTTTTT) (TTTFTT)
      input port 5 (TTTTTT) (TTTTFT)
      input port 6 (TTTTTT) (TTTTTF)


5. SubSystem block "AllCellCap"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: GbNDP_ReadAllCellCapVld_flgOverWrite,  NDP_1D_Config_Word,  NDP_1D_Config_Word1,  NDP_1D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 259
Condition NA 50% (1124/2248) condition outcomes
Decision NA 47% (228/483) decision outcomes
MCDC NA 0% (0/896) conditions reversed the outcome
Execution NA 100% (53/53) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (225/450) condition outcomes
MCDC 0% (0/336) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port1(1) 
  input port1(2) 
  input port1(3) 
  input port1(4) 
  input port1(5) 
  input port1(6) 
  input port1(7) 
  input port1(8) 
  input port1(9) 
  input port1(10) 
  input port1(11) 
  input port1(12) 
  input port1(13) 
  input port1(14) 
  input port1(15) 
  input port1(16) 
  input port1(17) 
  input port1(18) 
  input port1(19) 
  input port1(20) 
  input port1(21) 
  input port1(22) 
  input port1(23) 
  input port1(24) 
  input port1(25) 
  input port1(26) 
  input port1(27) 
  input port1(28) 
  input port1(29) 
  input port1(30) 
  input port1(31) 
  input port1(32) 
  input port1(33) 
  input port1(34) 
  input port1(35) 
  input port1(36) 
  input port1(37) 
  input port1(38) 
  input port1(39) 
  input port1(40) 
  input port1(41) 
  input port1(42) 
  input port1(43) 
  input port1(44) 
  input port1(45) 
  input port1(46) 
  input port1(47) 
  input port1(48) 
  input port1(49) 
  input port1(50) 
  input port1(51) 
  input port1(52) 
  input port1(53) 
  input port1(54) 
  input port1(55) 
  input port1(56) 
  input port1(57) 
  input port1(58) 
  input port1(59) 
  input port1(60) 
  input port1(61) 
  input port1(62) 
  input port1(63) 
  input port1(64) 
  input port1(65) 
  input port1(66) 
  input port1(67) 
  input port1(68) 
  input port1(69) 
  input port1(70) 
  input port1(71) 
  input port1(72) 
  input port1(73) 
  input port1(74) 
  input port1(75) 
  input port1(76) 
  input port1(77) 
  input port1(78) 
  input port1(79) 
  input port1(80) 
  input port1(81) 
  input port1(82) 
  input port1(83) 
  input port1(84) 
  input port1(85) 
  input port1(86) 
  input port1(87) 
  input port1(88) 
  input port1(89) 
  input port1(90) 
  input port1(91) 
  input port1(92) 
  input port1(93) 
  input port1(94) 
  input port1(95) 
  input port1(96) 
  input port1(97) 
  input port1(98) 
  input port1(99) 
  input port1(100) 
  input port1(101) 
  input port1(102) 
  input port1(103) 
  input port1(104) 
  input port1(105) 
  input port1(106) 
  input port1(107) 
  input port1(108) 
  input port1(109) 
  input port1(110) 
  input port1(111) 
  input port1(112) 
  input port2(1) 
  input port2(2) 
  input port2(3) 
  input port2(4) 
  input port2(5) 
  input port2(6) 
  input port2(7) 
  input port2(8) 
  input port2(9) 
  input port2(10) 
  input port2(11) 
  input port2(12) 
  input port2(13) 
  input port2(14) 
  input port2(15) 
  input port2(16) 
  input port2(17) 
  input port2(18) 
  input port2(19) 
  input port2(20) 
  input port2(21) 
  input port2(22) 
  input port2(23) 
  input port2(24) 
  input port2(25) 
  input port2(26) 
  input port2(27) 
  input port2(28) 
  input port2(29) 
  input port2(30) 
  input port2(31) 
  input port2(32) 
  input port2(33) 
  input port2(34) 
  input port2(35) 
  input port2(36) 
  input port2(37) 
  input port2(38) 
  input port2(39) 
  input port2(40) 
  input port2(41) 
  input port2(42) 
  input port2(43) 
  input port2(44) 
  input port2(45) 
  input port2(46) 
  input port2(47) 
  input port2(48) 
  input port2(49) 
  input port2(50) 
  input port2(51) 
  input port2(52) 
  input port2(53) 
  input port2(54) 
  input port2(55) 
  input port2(56) 
  input port2(57) 
  input port2(58) 
  input port2(59) 
  input port2(60) 
  input port2(61) 
  input port2(62) 
  input port2(63) 
  input port2(64) 
  input port2(65) 
  input port2(66) 
  input port2(67) 
  input port2(68) 
  input port2(69) 
  input port2(70) 
  input port2(71) 
  input port2(72) 
  input port2(73) 
  input port2(74) 
  input port2(75) 
  input port2(76) 
  input port2(77) 
  input port2(78) 
  input port2(79) 
  input port2(80) 
  input port2(81) 
  input port2(82) 
  input port2(83) 
  input port2(84) 
  input port2(85) 
  input port2(86) 
  input port2(87) 
  input port2(88) 
  input port2(89) 
  input port2(90) 
  input port2(91) 
  input port2(92) 
  input port2(93) 
  input port2(94) 
  input port2(95) 
  input port2(96) 
  input port2(97) 
  input port2(98) 
  input port2(99) 
  input port2(100) 
  input port2(101) 
  input port2(102) 
  input port2(103) 
  input port2(104) 
  input port2(105) 
  input port2(106) 
  input port2(107) 
  input port2(108) 
  input port2(109) 
  input port2(110) 
  input port2(111) 
  input port2(112) 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output(1)
      input port1(1) (TTT) (FTT)
      input port2(1) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(2)
      input port1(2) (TTT) (FTT)
      input port2(2) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(3)
      input port1(3) (TTT) (FTT)
      input port2(3) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(4)
      input port1(4) (TTT) (FTT)
      input port2(4) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(5)
      input port1(5) (TTT) (FTT)
      input port2(5) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(6)
      input port1(6) (TTT) (FTT)
      input port2(6) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(7)
      input port1(7) (TTT) (FTT)
      input port2(7) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(8)
      input port1(8) (TTT) (FTT)
      input port2(8) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(9)
      input port1(9) (TTT) (FTT)
      input port2(9) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(10)
      input port1(10) (TTT) (FTT)
      input port2(10) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(11)
      input port1(11) (TTT) (FTT)
      input port2(11) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(12)
      input port1(12) (TTT) (FTT)
      input port2(12) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(13)
      input port1(13) (TTT) (FTT)
      input port2(13) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(14)
      input port1(14) (TTT) (FTT)
      input port2(14) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(15)
      input port1(15) (TTT) (FTT)
      input port2(15) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(16)
      input port1(16) (TTT) (FTT)
      input port2(16) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(17)
      input port1(17) (TTT) (FTT)
      input port2(17) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(18)
      input port1(18) (TTT) (FTT)
      input port2(18) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(19)
      input port1(19) (TTT) (FTT)
      input port2(19) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(20)
      input port1(20) (TTT) (FTT)
      input port2(20) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(21)
      input port1(21) (TTT) (FTT)
      input port2(21) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(22)
      input port1(22) (TTT) (FTT)
      input port2(22) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(23)
      input port1(23) (TTT) (FTT)
      input port2(23) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(24)
      input port1(24) (TTT) (FTT)
      input port2(24) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(25)
      input port1(25) (TTT) (FTT)
      input port2(25) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(26)
      input port1(26) (TTT) (FTT)
      input port2(26) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(27)
      input port1(27) (TTT) (FTT)
      input port2(27) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(28)
      input port1(28) (TTT) (FTT)
      input port2(28) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(29)
      input port1(29) (TTT) (FTT)
      input port2(29) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(30)
      input port1(30) (TTT) (FTT)
      input port2(30) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(31)
      input port1(31) (TTT) (FTT)
      input port2(31) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(32)
      input port1(32) (TTT) (FTT)
      input port2(32) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(33)
      input port1(33) (TTT) (FTT)
      input port2(33) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(34)
      input port1(34) (TTT) (FTT)
      input port2(34) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(35)
      input port1(35) (TTT) (FTT)
      input port2(35) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(36)
      input port1(36) (TTT) (FTT)
      input port2(36) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(37)
      input port1(37) (TTT) (FTT)
      input port2(37) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(38)
      input port1(38) (TTT) (FTT)
      input port2(38) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(39)
      input port1(39) (TTT) (FTT)
      input port2(39) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(40)
      input port1(40) (TTT) (FTT)
      input port2(40) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(41)
      input port1(41) (TTT) (FTT)
      input port2(41) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(42)
      input port1(42) (TTT) (FTT)
      input port2(42) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(43)
      input port1(43) (TTT) (FTT)
      input port2(43) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(44)
      input port1(44) (TTT) (FTT)
      input port2(44) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(45)
      input port1(45) (TTT) (FTT)
      input port2(45) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(46)
      input port1(46) (TTT) (FTT)
      input port2(46) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(47)
      input port1(47) (TTT) (FTT)
      input port2(47) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(48)
      input port1(48) (TTT) (FTT)
      input port2(48) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(49)
      input port1(49) (TTT) (FTT)
      input port2(49) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(50)
      input port1(50) (TTT) (FTT)
      input port2(50) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(51)
      input port1(51) (TTT) (FTT)
      input port2(51) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(52)
      input port1(52) (TTT) (FTT)
      input port2(52) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(53)
      input port1(53) (TTT) (FTT)
      input port2(53) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(54)
      input port1(54) (TTT) (FTT)
      input port2(54) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(55)
      input port1(55) (TTT) (FTT)
      input port2(55) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(56)
      input port1(56) (TTT) (FTT)
      input port2(56) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(57)
      input port1(57) (TTT) (FTT)
      input port2(57) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(58)
      input port1(58) (TTT) (FTT)
      input port2(58) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(59)
      input port1(59) (TTT) (FTT)
      input port2(59) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(60)
      input port1(60) (TTT) (FTT)
      input port2(60) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(61)
      input port1(61) (TTT) (FTT)
      input port2(61) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(62)
      input port1(62) (TTT) (FTT)
      input port2(62) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(63)
      input port1(63) (TTT) (FTT)
      input port2(63) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(64)
      input port1(64) (TTT) (FTT)
      input port2(64) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(65)
      input port1(65) (TTT) (FTT)
      input port2(65) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(66)
      input port1(66) (TTT) (FTT)
      input port2(66) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(67)
      input port1(67) (TTT) (FTT)
      input port2(67) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(68)
      input port1(68) (TTT) (FTT)
      input port2(68) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(69)
      input port1(69) (TTT) (FTT)
      input port2(69) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(70)
      input port1(70) (TTT) (FTT)
      input port2(70) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(71)
      input port1(71) (TTT) (FTT)
      input port2(71) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(72)
      input port1(72) (TTT) (FTT)
      input port2(72) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(73)
      input port1(73) (TTT) (FTT)
      input port2(73) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(74)
      input port1(74) (TTT) (FTT)
      input port2(74) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(75)
      input port1(75) (TTT) (FTT)
      input port2(75) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(76)
      input port1(76) (TTT) (FTT)
      input port2(76) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(77)
      input port1(77) (TTT) (FTT)
      input port2(77) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(78)
      input port1(78) (TTT) (FTT)
      input port2(78) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(79)
      input port1(79) (TTT) (FTT)
      input port2(79) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(80)
      input port1(80) (TTT) (FTT)
      input port2(80) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(81)
      input port1(81) (TTT) (FTT)
      input port2(81) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(82)
      input port1(82) (TTT) (FTT)
      input port2(82) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(83)
      input port1(83) (TTT) (FTT)
      input port2(83) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(84)
      input port1(84) (TTT) (FTT)
      input port2(84) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(85)
      input port1(85) (TTT) (FTT)
      input port2(85) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(86)
      input port1(86) (TTT) (FTT)
      input port2(86) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(87)
      input port1(87) (TTT) (FTT)
      input port2(87) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(88)
      input port1(88) (TTT) (FTT)
      input port2(88) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(89)
      input port1(89) (TTT) (FTT)
      input port2(89) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(90)
      input port1(90) (TTT) (FTT)
      input port2(90) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(91)
      input port1(91) (TTT) (FTT)
      input port2(91) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(92)
      input port1(92) (TTT) (FTT)
      input port2(92) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(93)
      input port1(93) (TTT) (FTT)
      input port2(93) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(94)
      input port1(94) (TTT) (FTT)
      input port2(94) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(95)
      input port1(95) (TTT) (FTT)
      input port2(95) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(96)
      input port1(96) (TTT) (FTT)
      input port2(96) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(97)
      input port1(97) (TTT) (FTT)
      input port2(97) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(98)
      input port1(98) (TTT) (FTT)
      input port2(98) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(99)
      input port1(99) (TTT) (FTT)
      input port2(99) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(100)
      input port1(100) (TTT) (FTT)
      input port2(100) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(101)
      input port1(101) (TTT) (FTT)
      input port2(101) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(102)
      input port1(102) (TTT) (FTT)
      input port2(102) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(103)
      input port1(103) (TTT) (FTT)
      input port2(103) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(104)
      input port1(104) (TTT) (FTT)
      input port2(104) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(105)
      input port1(105) (TTT) (FTT)
      input port2(105) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(106)
      input port1(106) (TTT) (FTT)
      input port2(106) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(107)
      input port1(107) (TTT) (FTT)
      input port2(107) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(108)
      input port1(108) (TTT) (FTT)
      input port2(108) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(109)
      input port1(109) (TTT) (FTT)
      input port2(109) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(110)
      input port1(110) (TTT) (FTT)
      input port2(110) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(111)
      input port1(111) (TTT) (FTT)
      input port2(111) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(112)
      input port1(112) (TTT) (FTT)
      input port2(112) (TTT) (TFT)
      input port 3 (TTT) (TTF)


   Logic block "Logical1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (225/450) condition outcomes
MCDC 0% (0/336) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port1(1) 
  input port1(2) 
  input port1(3) 
  input port1(4) 
  input port1(5) 
  input port1(6) 
  input port1(7) 
  input port1(8) 
  input port1(9) 
  input port1(10) 
  input port1(11) 
  input port1(12) 
  input port1(13) 
  input port1(14) 
  input port1(15) 
  input port1(16) 
  input port1(17) 
  input port1(18) 
  input port1(19) 
  input port1(20) 
  input port1(21) 
  input port1(22) 
  input port1(23) 
  input port1(24) 
  input port1(25) 
  input port1(26) 
  input port1(27) 
  input port1(28) 
  input port1(29) 
  input port1(30) 
  input port1(31) 
  input port1(32) 
  input port1(33) 
  input port1(34) 
  input port1(35) 
  input port1(36) 
  input port1(37) 
  input port1(38) 
  input port1(39) 
  input port1(40) 
  input port1(41) 
  input port1(42) 
  input port1(43) 
  input port1(44) 
  input port1(45) 
  input port1(46) 
  input port1(47) 
  input port1(48) 
  input port1(49) 
  input port1(50) 
  input port1(51) 
  input port1(52) 
  input port1(53) 
  input port1(54) 
  input port1(55) 
  input port1(56) 
  input port1(57) 
  input port1(58) 
  input port1(59) 
  input port1(60) 
  input port1(61) 
  input port1(62) 
  input port1(63) 
  input port1(64) 
  input port1(65) 
  input port1(66) 
  input port1(67) 
  input port1(68) 
  input port1(69) 
  input port1(70) 
  input port1(71) 
  input port1(72) 
  input port1(73) 
  input port1(74) 
  input port1(75) 
  input port1(76) 
  input port1(77) 
  input port1(78) 
  input port1(79) 
  input port1(80) 
  input port1(81) 
  input port1(82) 
  input port1(83) 
  input port1(84) 
  input port1(85) 
  input port1(86) 
  input port1(87) 
  input port1(88) 
  input port1(89) 
  input port1(90) 
  input port1(91) 
  input port1(92) 
  input port1(93) 
  input port1(94) 
  input port1(95) 
  input port1(96) 
  input port1(97) 
  input port1(98) 
  input port1(99) 
  input port1(100) 
  input port1(101) 
  input port1(102) 
  input port1(103) 
  input port1(104) 
  input port1(105) 
  input port1(106) 
  input port1(107) 
  input port1(108) 
  input port1(109) 
  input port1(110) 
  input port1(111) 
  input port1(112) 
  input port2(1) 
  input port2(2) 
  input port2(3) 
  input port2(4) 
  input port2(5) 
  input port2(6) 
  input port2(7) 
  input port2(8) 
  input port2(9) 
  input port2(10) 
  input port2(11) 
  input port2(12) 
  input port2(13) 
  input port2(14) 
  input port2(15) 
  input port2(16) 
  input port2(17) 
  input port2(18) 
  input port2(19) 
  input port2(20) 
  input port2(21) 
  input port2(22) 
  input port2(23) 
  input port2(24) 
  input port2(25) 
  input port2(26) 
  input port2(27) 
  input port2(28) 
  input port2(29) 
  input port2(30) 
  input port2(31) 
  input port2(32) 
  input port2(33) 
  input port2(34) 
  input port2(35) 
  input port2(36) 
  input port2(37) 
  input port2(38) 
  input port2(39) 
  input port2(40) 
  input port2(41) 
  input port2(42) 
  input port2(43) 
  input port2(44) 
  input port2(45) 
  input port2(46) 
  input port2(47) 
  input port2(48) 
  input port2(49) 
  input port2(50) 
  input port2(51) 
  input port2(52) 
  input port2(53) 
  input port2(54) 
  input port2(55) 
  input port2(56) 
  input port2(57) 
  input port2(58) 
  input port2(59) 
  input port2(60) 
  input port2(61) 
  input port2(62) 
  input port2(63) 
  input port2(64) 
  input port2(65) 
  input port2(66) 
  input port2(67) 
  input port2(68) 
  input port2(69) 
  input port2(70) 
  input port2(71) 
  input port2(72) 
  input port2(73) 
  input port2(74) 
  input port2(75) 
  input port2(76) 
  input port2(77) 
  input port2(78) 
  input port2(79) 
  input port2(80) 
  input port2(81) 
  input port2(82) 
  input port2(83) 
  input port2(84) 
  input port2(85) 
  input port2(86) 
  input port2(87) 
  input port2(88) 
  input port2(89) 
  input port2(90) 
  input port2(91) 
  input port2(92) 
  input port2(93) 
  input port2(94) 
  input port2(95) 
  input port2(96) 
  input port2(97) 
  input port2(98) 
  input port2(99) 
  input port2(100) 
  input port2(101) 
  input port2(102) 
  input port2(103) 
  input port2(104) 
  input port2(105) 
  input port2(106) 
  input port2(107) 
  input port2(108) 
  input port2(109) 
  input port2(110) 
  input port2(111) 
  input port2(112) 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output(1)
      input port1(1) (TTT) (FTT)
      input port2(1) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(2)
      input port1(2) (TTT) (FTT)
      input port2(2) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(3)
      input port1(3) (TTT) (FTT)
      input port2(3) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(4)
      input port1(4) (TTT) (FTT)
      input port2(4) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(5)
      input port1(5) (TTT) (FTT)
      input port2(5) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(6)
      input port1(6) (TTT) (FTT)
      input port2(6) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(7)
      input port1(7) (TTT) (FTT)
      input port2(7) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(8)
      input port1(8) (TTT) (FTT)
      input port2(8) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(9)
      input port1(9) (TTT) (FTT)
      input port2(9) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(10)
      input port1(10) (TTT) (FTT)
      input port2(10) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(11)
      input port1(11) (TTT) (FTT)
      input port2(11) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(12)
      input port1(12) (TTT) (FTT)
      input port2(12) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(13)
      input port1(13) (TTT) (FTT)
      input port2(13) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(14)
      input port1(14) (TTT) (FTT)
      input port2(14) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(15)
      input port1(15) (TTT) (FTT)
      input port2(15) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(16)
      input port1(16) (TTT) (FTT)
      input port2(16) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(17)
      input port1(17) (TTT) (FTT)
      input port2(17) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(18)
      input port1(18) (TTT) (FTT)
      input port2(18) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(19)
      input port1(19) (TTT) (FTT)
      input port2(19) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(20)
      input port1(20) (TTT) (FTT)
      input port2(20) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(21)
      input port1(21) (TTT) (FTT)
      input port2(21) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(22)
      input port1(22) (TTT) (FTT)
      input port2(22) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(23)
      input port1(23) (TTT) (FTT)
      input port2(23) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(24)
      input port1(24) (TTT) (FTT)
      input port2(24) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(25)
      input port1(25) (TTT) (FTT)
      input port2(25) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(26)
      input port1(26) (TTT) (FTT)
      input port2(26) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(27)
      input port1(27) (TTT) (FTT)
      input port2(27) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(28)
      input port1(28) (TTT) (FTT)
      input port2(28) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(29)
      input port1(29) (TTT) (FTT)
      input port2(29) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(30)
      input port1(30) (TTT) (FTT)
      input port2(30) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(31)
      input port1(31) (TTT) (FTT)
      input port2(31) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(32)
      input port1(32) (TTT) (FTT)
      input port2(32) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(33)
      input port1(33) (TTT) (FTT)
      input port2(33) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(34)
      input port1(34) (TTT) (FTT)
      input port2(34) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(35)
      input port1(35) (TTT) (FTT)
      input port2(35) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(36)
      input port1(36) (TTT) (FTT)
      input port2(36) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(37)
      input port1(37) (TTT) (FTT)
      input port2(37) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(38)
      input port1(38) (TTT) (FTT)
      input port2(38) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(39)
      input port1(39) (TTT) (FTT)
      input port2(39) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(40)
      input port1(40) (TTT) (FTT)
      input port2(40) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(41)
      input port1(41) (TTT) (FTT)
      input port2(41) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(42)
      input port1(42) (TTT) (FTT)
      input port2(42) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(43)
      input port1(43) (TTT) (FTT)
      input port2(43) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(44)
      input port1(44) (TTT) (FTT)
      input port2(44) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(45)
      input port1(45) (TTT) (FTT)
      input port2(45) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(46)
      input port1(46) (TTT) (FTT)
      input port2(46) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(47)
      input port1(47) (TTT) (FTT)
      input port2(47) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(48)
      input port1(48) (TTT) (FTT)
      input port2(48) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(49)
      input port1(49) (TTT) (FTT)
      input port2(49) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(50)
      input port1(50) (TTT) (FTT)
      input port2(50) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(51)
      input port1(51) (TTT) (FTT)
      input port2(51) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(52)
      input port1(52) (TTT) (FTT)
      input port2(52) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(53)
      input port1(53) (TTT) (FTT)
      input port2(53) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(54)
      input port1(54) (TTT) (FTT)
      input port2(54) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(55)
      input port1(55) (TTT) (FTT)
      input port2(55) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(56)
      input port1(56) (TTT) (FTT)
      input port2(56) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(57)
      input port1(57) (TTT) (FTT)
      input port2(57) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(58)
      input port1(58) (TTT) (FTT)
      input port2(58) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(59)
      input port1(59) (TTT) (FTT)
      input port2(59) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(60)
      input port1(60) (TTT) (FTT)
      input port2(60) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(61)
      input port1(61) (TTT) (FTT)
      input port2(61) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(62)
      input port1(62) (TTT) (FTT)
      input port2(62) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(63)
      input port1(63) (TTT) (FTT)
      input port2(63) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(64)
      input port1(64) (TTT) (FTT)
      input port2(64) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(65)
      input port1(65) (TTT) (FTT)
      input port2(65) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(66)
      input port1(66) (TTT) (FTT)
      input port2(66) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(67)
      input port1(67) (TTT) (FTT)
      input port2(67) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(68)
      input port1(68) (TTT) (FTT)
      input port2(68) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(69)
      input port1(69) (TTT) (FTT)
      input port2(69) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(70)
      input port1(70) (TTT) (FTT)
      input port2(70) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(71)
      input port1(71) (TTT) (FTT)
      input port2(71) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(72)
      input port1(72) (TTT) (FTT)
      input port2(72) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(73)
      input port1(73) (TTT) (FTT)
      input port2(73) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(74)
      input port1(74) (TTT) (FTT)
      input port2(74) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(75)
      input port1(75) (TTT) (FTT)
      input port2(75) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(76)
      input port1(76) (TTT) (FTT)
      input port2(76) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(77)
      input port1(77) (TTT) (FTT)
      input port2(77) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(78)
      input port1(78) (TTT) (FTT)
      input port2(78) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(79)
      input port1(79) (TTT) (FTT)
      input port2(79) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(80)
      input port1(80) (TTT) (FTT)
      input port2(80) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(81)
      input port1(81) (TTT) (FTT)
      input port2(81) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(82)
      input port1(82) (TTT) (FTT)
      input port2(82) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(83)
      input port1(83) (TTT) (FTT)
      input port2(83) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(84)
      input port1(84) (TTT) (FTT)
      input port2(84) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(85)
      input port1(85) (TTT) (FTT)
      input port2(85) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(86)
      input port1(86) (TTT) (FTT)
      input port2(86) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(87)
      input port1(87) (TTT) (FTT)
      input port2(87) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(88)
      input port1(88) (TTT) (FTT)
      input port2(88) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(89)
      input port1(89) (TTT) (FTT)
      input port2(89) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(90)
      input port1(90) (TTT) (FTT)
      input port2(90) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(91)
      input port1(91) (TTT) (FTT)
      input port2(91) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(92)
      input port1(92) (TTT) (FTT)
      input port2(92) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(93)
      input port1(93) (TTT) (FTT)
      input port2(93) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(94)
      input port1(94) (TTT) (FTT)
      input port2(94) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(95)
      input port1(95) (TTT) (FTT)
      input port2(95) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(96)
      input port1(96) (TTT) (FTT)
      input port2(96) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(97)
      input port1(97) (TTT) (FTT)
      input port2(97) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(98)
      input port1(98) (TTT) (FTT)
      input port2(98) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(99)
      input port1(99) (TTT) (FTT)
      input port2(99) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(100)
      input port1(100) (TTT) (FTT)
      input port2(100) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(101)
      input port1(101) (TTT) (FTT)
      input port2(101) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(102)
      input port1(102) (TTT) (FTT)
      input port2(102) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(103)
      input port1(103) (TTT) (FTT)
      input port2(103) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(104)
      input port1(104) (TTT) (FTT)
      input port2(104) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(105)
      input port1(105) (TTT) (FTT)
      input port2(105) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(106)
      input port1(106) (TTT) (FTT)
      input port2(106) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(107)
      input port1(107) (TTT) (FTT)
      input port2(107) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(108)
      input port1(108) (TTT) (FTT)
      input port2(108) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(109)
      input port1(109) (TTT) (FTT)
      input port2(109) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(110)
      input port1(110) (TTT) (FTT)
      input port2(110) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(111)
      input port1(111) (TTT) (FTT)
      input port2(111) (TTT) (TFT)
      input port 3 (TTT) (TTF)
expression for output(112)
      input port1(112) (TTT) (FTT)
      input port2(112) (TTT) (TFT)
      input port 3 (TTT) (TTF)


   Logic block "Logical2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (224/448) condition outcomes
MCDC 0% (0/224) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port1(1) 
  input port1(2) 
  input port1(3) 
  input port1(4) 
  input port1(5) 
  input port1(6) 
  input port1(7) 
  input port1(8) 
  input port1(9) 
  input port1(10) 
  input port1(11) 
  input port1(12) 
  input port1(13) 
  input port1(14) 
  input port1(15) 
  input port1(16) 
  input port1(17) 
  input port1(18) 
  input port1(19) 
  input port1(20) 
  input port1(21) 
  input port1(22) 
  input port1(23) 
  input port1(24) 
  input port1(25) 
  input port1(26) 
  input port1(27) 
  input port1(28) 
  input port1(29) 
  input port1(30) 
  input port1(31) 
  input port1(32) 
  input port1(33) 
  input port1(34) 
  input port1(35) 
  input port1(36) 
  input port1(37) 
  input port1(38) 
  input port1(39) 
  input port1(40) 
  input port1(41) 
  input port1(42) 
  input port1(43) 
  input port1(44) 
  input port1(45) 
  input port1(46) 
  input port1(47) 
  input port1(48) 
  input port1(49) 
  input port1(50) 
  input port1(51) 
  input port1(52) 
  input port1(53) 
  input port1(54) 
  input port1(55) 
  input port1(56) 
  input port1(57) 
  input port1(58) 
  input port1(59) 
  input port1(60) 
  input port1(61) 
  input port1(62) 
  input port1(63) 
  input port1(64) 
  input port1(65) 
  input port1(66) 
  input port1(67) 
  input port1(68) 
  input port1(69) 
  input port1(70) 
  input port1(71) 
  input port1(72) 
  input port1(73) 
  input port1(74) 
  input port1(75) 
  input port1(76) 
  input port1(77) 
  input port1(78) 
  input port1(79) 
  input port1(80) 
  input port1(81) 
  input port1(82) 
  input port1(83) 
  input port1(84) 
  input port1(85) 
  input port1(86) 
  input port1(87) 
  input port1(88) 
  input port1(89) 
  input port1(90) 
  input port1(91) 
  input port1(92) 
  input port1(93) 
  input port1(94) 
  input port1(95) 
  input port1(96) 
  input port1(97) 
  input port1(98) 
  input port1(99) 
  input port1(100) 
  input port1(101) 
  input port1(102) 
  input port1(103) 
  input port1(104) 
  input port1(105) 
  input port1(106) 
  input port1(107) 
  input port1(108) 
  input port1(109) 
  input port1(110) 
  input port1(111) 
  input port1(112) 
  input port2(1) 
  input port2(2) 
  input port2(3) 
  input port2(4) 
  input port2(5) 
  input port2(6) 
  input port2(7) 
  input port2(8) 
  input port2(9) 
  input port2(10) 
  input port2(11) 
  input port2(12) 
  input port2(13) 
  input port2(14) 
  input port2(15) 
  input port2(16) 
  input port2(17) 
  input port2(18) 
  input port2(19) 
  input port2(20) 
  input port2(21) 
  input port2(22) 
  input port2(23) 
  input port2(24) 
  input port2(25) 
  input port2(26) 
  input port2(27) 
  input port2(28) 
  input port2(29) 
  input port2(30) 
  input port2(31) 
  input port2(32) 
  input port2(33) 
  input port2(34) 
  input port2(35) 
  input port2(36) 
  input port2(37) 
  input port2(38) 
  input port2(39) 
  input port2(40) 
  input port2(41) 
  input port2(42) 
  input port2(43) 
  input port2(44) 
  input port2(45) 
  input port2(46) 
  input port2(47) 
  input port2(48) 
  input port2(49) 
  input port2(50) 
  input port2(51) 
  input port2(52) 
  input port2(53) 
  input port2(54) 
  input port2(55) 
  input port2(56) 
  input port2(57) 
  input port2(58) 
  input port2(59) 
  input port2(60) 
  input port2(61) 
  input port2(62) 
  input port2(63) 
  input port2(64) 
  input port2(65) 
  input port2(66) 
  input port2(67) 
  input port2(68) 
  input port2(69) 
  input port2(70) 
  input port2(71) 
  input port2(72) 
  input port2(73) 
  input port2(74) 
  input port2(75) 
  input port2(76) 
  input port2(77) 
  input port2(78) 
  input port2(79) 
  input port2(80) 
  input port2(81) 
  input port2(82) 
  input port2(83) 
  input port2(84) 
  input port2(85) 
  input port2(86) 
  input port2(87) 
  input port2(88) 
  input port2(89) 
  input port2(90) 
  input port2(91) 
  input port2(92) 
  input port2(93) 
  input port2(94) 
  input port2(95) 
  input port2(96) 
  input port2(97) 
  input port2(98) 
  input port2(99) 
  input port2(100) 
  input port2(101) 
  input port2(102) 
  input port2(103) 
  input port2(104) 
  input port2(105) 
  input port2(106) 
  input port2(107) 
  input port2(108) 
  input port2(109) 
  input port2(110) 
  input port2(111) 
  input port2(112) 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output(1)
      input port1(1) (TF) FF
      input port2(1) (FT) FF
expression for output(2)
      input port1(2) (TF) FF
      input port2(2) (FT) FF
expression for output(3)
      input port1(3) (TF) FF
      input port2(3) (FT) FF
expression for output(4)
      input port1(4) (TF) FF
      input port2(4) (FT) FF
expression for output(5)
      input port1(5) (TF) FF
      input port2(5) (FT) FF
expression for output(6)
      input port1(6) (TF) FF
      input port2(6) (FT) FF
expression for output(7)
      input port1(7) (TF) FF
      input port2(7) (FT) FF
expression for output(8)
      input port1(8) (TF) FF
      input port2(8) (FT) FF
expression for output(9)
      input port1(9) (TF) FF
      input port2(9) (FT) FF
expression for output(10)
      input port1(10) (TF) FF
      input port2(10) (FT) FF
expression for output(11)
      input port1(11) (TF) FF
      input port2(11) (FT) FF
expression for output(12)
      input port1(12) (TF) FF
      input port2(12) (FT) FF
expression for output(13)
      input port1(13) (TF) FF
      input port2(13) (FT) FF
expression for output(14)
      input port1(14) (TF) FF
      input port2(14) (FT) FF
expression for output(15)
      input port1(15) (TF) FF
      input port2(15) (FT) FF
expression for output(16)
      input port1(16) (TF) FF
      input port2(16) (FT) FF
expression for output(17)
      input port1(17) (TF) FF
      input port2(17) (FT) FF
expression for output(18)
      input port1(18) (TF) FF
      input port2(18) (FT) FF
expression for output(19)
      input port1(19) (TF) FF
      input port2(19) (FT) FF
expression for output(20)
      input port1(20) (TF) FF
      input port2(20) (FT) FF
expression for output(21)
      input port1(21) (TF) FF
      input port2(21) (FT) FF
expression for output(22)
      input port1(22) (TF) FF
      input port2(22) (FT) FF
expression for output(23)
      input port1(23) (TF) FF
      input port2(23) (FT) FF
expression for output(24)
      input port1(24) (TF) FF
      input port2(24) (FT) FF
expression for output(25)
      input port1(25) (TF) FF
      input port2(25) (FT) FF
expression for output(26)
      input port1(26) (TF) FF
      input port2(26) (FT) FF
expression for output(27)
      input port1(27) (TF) FF
      input port2(27) (FT) FF
expression for output(28)
      input port1(28) (TF) FF
      input port2(28) (FT) FF
expression for output(29)
      input port1(29) (TF) FF
      input port2(29) (FT) FF
expression for output(30)
      input port1(30) (TF) FF
      input port2(30) (FT) FF
expression for output(31)
      input port1(31) (TF) FF
      input port2(31) (FT) FF
expression for output(32)
      input port1(32) (TF) FF
      input port2(32) (FT) FF
expression for output(33)
      input port1(33) (TF) FF
      input port2(33) (FT) FF
expression for output(34)
      input port1(34) (TF) FF
      input port2(34) (FT) FF
expression for output(35)
      input port1(35) (TF) FF
      input port2(35) (FT) FF
expression for output(36)
      input port1(36) (TF) FF
      input port2(36) (FT) FF
expression for output(37)
      input port1(37) (TF) FF
      input port2(37) (FT) FF
expression for output(38)
      input port1(38) (TF) FF
      input port2(38) (FT) FF
expression for output(39)
      input port1(39) (TF) FF
      input port2(39) (FT) FF
expression for output(40)
      input port1(40) (TF) FF
      input port2(40) (FT) FF
expression for output(41)
      input port1(41) (TF) FF
      input port2(41) (FT) FF
expression for output(42)
      input port1(42) (TF) FF
      input port2(42) (FT) FF
expression for output(43)
      input port1(43) (TF) FF
      input port2(43) (FT) FF
expression for output(44)
      input port1(44) (TF) FF
      input port2(44) (FT) FF
expression for output(45)
      input port1(45) (TF) FF
      input port2(45) (FT) FF
expression for output(46)
      input port1(46) (TF) FF
      input port2(46) (FT) FF
expression for output(47)
      input port1(47) (TF) FF
      input port2(47) (FT) FF
expression for output(48)
      input port1(48) (TF) FF
      input port2(48) (FT) FF
expression for output(49)
      input port1(49) (TF) FF
      input port2(49) (FT) FF
expression for output(50)
      input port1(50) (TF) FF
      input port2(50) (FT) FF
expression for output(51)
      input port1(51) (TF) FF
      input port2(51) (FT) FF
expression for output(52)
      input port1(52) (TF) FF
      input port2(52) (FT) FF
expression for output(53)
      input port1(53) (TF) FF
      input port2(53) (FT) FF
expression for output(54)
      input port1(54) (TF) FF
      input port2(54) (FT) FF
expression for output(55)
      input port1(55) (TF) FF
      input port2(55) (FT) FF
expression for output(56)
      input port1(56) (TF) FF
      input port2(56) (FT) FF
expression for output(57)
      input port1(57) (TF) FF
      input port2(57) (FT) FF
expression for output(58)
      input port1(58) (TF) FF
      input port2(58) (FT) FF
expression for output(59)
      input port1(59) (TF) FF
      input port2(59) (FT) FF
expression for output(60)
      input port1(60) (TF) FF
      input port2(60) (FT) FF
expression for output(61)
      input port1(61) (TF) FF
      input port2(61) (FT) FF
expression for output(62)
      input port1(62) (TF) FF
      input port2(62) (FT) FF
expression for output(63)
      input port1(63) (TF) FF
      input port2(63) (FT) FF
expression for output(64)
      input port1(64) (TF) FF
      input port2(64) (FT) FF
expression for output(65)
      input port1(65) (TF) FF
      input port2(65) (FT) FF
expression for output(66)
      input port1(66) (TF) FF
      input port2(66) (FT) FF
expression for output(67)
      input port1(67) (TF) FF
      input port2(67) (FT) FF
expression for output(68)
      input port1(68) (TF) FF
      input port2(68) (FT) FF
expression for output(69)
      input port1(69) (TF) FF
      input port2(69) (FT) FF
expression for output(70)
      input port1(70) (TF) FF
      input port2(70) (FT) FF
expression for output(71)
      input port1(71) (TF) FF
      input port2(71) (FT) FF
expression for output(72)
      input port1(72) (TF) FF
      input port2(72) (FT) FF
expression for output(73)
      input port1(73) (TF) FF
      input port2(73) (FT) FF
expression for output(74)
      input port1(74) (TF) FF
      input port2(74) (FT) FF
expression for output(75)
      input port1(75) (TF) FF
      input port2(75) (FT) FF
expression for output(76)
      input port1(76) (TF) FF
      input port2(76) (FT) FF
expression for output(77)
      input port1(77) (TF) FF
      input port2(77) (FT) FF
expression for output(78)
      input port1(78) (TF) FF
      input port2(78) (FT) FF
expression for output(79)
      input port1(79) (TF) FF
      input port2(79) (FT) FF
expression for output(80)
      input port1(80) (TF) FF
      input port2(80) (FT) FF
expression for output(81)
      input port1(81) (TF) FF
      input port2(81) (FT) FF
expression for output(82)
      input port1(82) (TF) FF
      input port2(82) (FT) FF
expression for output(83)
      input port1(83) (TF) FF
      input port2(83) (FT) FF
expression for output(84)
      input port1(84) (TF) FF
      input port2(84) (FT) FF
expression for output(85)
      input port1(85) (TF) FF
      input port2(85) (FT) FF
expression for output(86)
      input port1(86) (TF) FF
      input port2(86) (FT) FF
expression for output(87)
      input port1(87) (TF) FF
      input port2(87) (FT) FF
expression for output(88)
      input port1(88) (TF) FF
      input port2(88) (FT) FF
expression for output(89)
      input port1(89) (TF) FF
      input port2(89) (FT) FF
expression for output(90)
      input port1(90) (TF) FF
      input port2(90) (FT) FF
expression for output(91)
      input port1(91) (TF) FF
      input port2(91) (FT) FF
expression for output(92)
      input port1(92) (TF) FF
      input port2(92) (FT) FF
expression for output(93)
      input port1(93) (TF) FF
      input port2(93) (FT) FF
expression for output(94)
      input port1(94) (TF) FF
      input port2(94) (FT) FF
expression for output(95)
      input port1(95) (TF) FF
      input port2(95) (FT) FF
expression for output(96)
      input port1(96) (TF) FF
      input port2(96) (FT) FF
expression for output(97)
      input port1(97) (TF) FF
      input port2(97) (FT) FF
expression for output(98)
      input port1(98) (TF) FF
      input port2(98) (FT) FF
expression for output(99)
      input port1(99) (TF) FF
      input port2(99) (FT) FF
expression for output(100)
      input port1(100) (TF) FF
      input port2(100) (FT) FF
expression for output(101)
      input port1(101) (TF) FF
      input port2(101) (FT) FF
expression for output(102)
      input port1(102) (TF) FF
      input port2(102) (FT) FF
expression for output(103)
      input port1(103) (TF) FF
      input port2(103) (FT) FF
expression for output(104)
      input port1(104) (TF) FF
      input port2(104) (FT) FF
expression for output(105)
      input port1(105) (TF) FF
      input port2(105) (FT) FF
expression for output(106)
      input port1(106) (TF) FF
      input port2(106) (FT) FF
expression for output(107)
      input port1(107) (TF) FF
      input port2(107) (FT) FF
expression for output(108)
      input port1(108) (TF) FF
      input port2(108) (FT) FF
expression for output(109)
      input port1(109) (TF) FF
      input port2(109) (FT) FF
expression for output(110)
      input port1(110) (TF) FF
      input port2(110) (FT) FF
expression for output(111)
      input port1(111) (TF) FF
      input port2(111) (FT) FF
expression for output(112)
      input port1(112) (TF) FF
      input port2(112) (FT) FF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 112
Decision 50% (112/224) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(2)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(3)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(4)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(5)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(6)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(7)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(8)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(9)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(10)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(11)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(12)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(13)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(14)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(15)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(16)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(17)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(18)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(19)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(20)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(21)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(22)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(23)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(24)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(25)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(26)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(27)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(28)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(29)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(30)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(31)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(32)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(33)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(34)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(35)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(36)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(37)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(38)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(39)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(40)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(41)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(42)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(43)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(44)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(45)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(46)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(47)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(48)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(49)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(50)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(51)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(52)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(53)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(54)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(55)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(56)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(57)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(58)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(59)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(60)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(61)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(62)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(63)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(64)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(65)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(66)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(67)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(68)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(69)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(70)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(71)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(72)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(73)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(74)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(75)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(76)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(77)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(78)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(79)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(80)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(81)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(82)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(83)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(84)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(85)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(86)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(87)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(88)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(89)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(90)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(91)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(92)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(93)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(94)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(95)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(96)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(97)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(98)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(99)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(100)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(101)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(102)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(103)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(104)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(105)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(106)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(107)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(108)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(109)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(110)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(111)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(112)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Switch block "Switch1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 112
Decision 50% (112/224) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(2)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(3)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(4)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(5)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(6)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(7)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(8)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(9)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(10)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(11)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(12)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(13)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(14)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(15)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(16)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(17)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(18)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(19)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(20)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(21)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(22)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(23)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(24)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(25)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(26)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(27)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(28)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(29)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(30)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(31)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(32)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(33)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(34)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(35)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(36)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(37)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(38)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(39)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(40)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(41)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(42)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(43)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(44)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(45)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(46)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(47)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(48)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(49)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(50)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(51)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(52)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(53)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(54)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(55)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(56)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(57)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(58)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(59)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(60)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(61)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(62)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(63)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(64)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(65)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(66)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(67)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(68)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(69)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(70)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(71)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(72)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(73)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(74)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(75)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(76)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(77)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(78)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(79)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(80)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(81)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(82)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(83)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(84)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(85)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(86)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(87)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(88)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(89)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(90)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(91)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(92)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(93)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(94)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(95)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(96)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(97)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(98)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(99)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(100)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(101)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(102)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(103)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(104)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(105)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(106)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(107)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(108)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(109)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(110)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(111)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(112)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (112/224) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) > input2(1) 
  input1(2) > input2(2) 
  input1(3) > input2(3) 
  input1(4) > input2(4) 
  input1(5) > input2(5) 
  input1(6) > input2(6) 
  input1(7) > input2(7) 
  input1(8) > input2(8) 
  input1(9) > input2(9) 
  input1(10) > input2(10) 
  input1(11) > input2(11) 
  input1(12) > input2(12) 
  input1(13) > input2(13) 
  input1(14) > input2(14) 
  input1(15) > input2(15) 
  input1(16) > input2(16) 
  input1(17) > input2(17) 
  input1(18) > input2(18) 
  input1(19) > input2(19) 
  input1(20) > input2(20) 
  input1(21) > input2(21) 
  input1(22) > input2(22) 
  input1(23) > input2(23) 
  input1(24) > input2(24) 
  input1(25) > input2(25) 
  input1(26) > input2(26) 
  input1(27) > input2(27) 
  input1(28) > input2(28) 
  input1(29) > input2(29) 
  input1(30) > input2(30) 
  input1(31) > input2(31) 
  input1(32) > input2(32) 
  input1(33) > input2(33) 
  input1(34) > input2(34) 
  input1(35) > input2(35) 
  input1(36) > input2(36) 
  input1(37) > input2(37) 
  input1(38) > input2(38) 
  input1(39) > input2(39) 
  input1(40) > input2(40) 
  input1(41) > input2(41) 
  input1(42) > input2(42) 
  input1(43) > input2(43) 
  input1(44) > input2(44) 
  input1(45) > input2(45) 
  input1(46) > input2(46) 
  input1(47) > input2(47) 
  input1(48) > input2(48) 
  input1(49) > input2(49) 
  input1(50) > input2(50) 
  input1(51) > input2(51) 
  input1(52) > input2(52) 
  input1(53) > input2(53) 
  input1(54) > input2(54) 
  input1(55) > input2(55) 
  input1(56) > input2(56) 
  input1(57) > input2(57) 
  input1(58) > input2(58) 
  input1(59) > input2(59) 
  input1(60) > input2(60) 
  input1(61) > input2(61) 
  input1(62) > input2(62) 
  input1(63) > input2(63) 
  input1(64) > input2(64) 
  input1(65) > input2(65) 
  input1(66) > input2(66) 
  input1(67) > input2(67) 
  input1(68) > input2(68) 
  input1(69) > input2(69) 
  input1(70) > input2(70) 
  input1(71) > input2(71) 
  input1(72) > input2(72) 
  input1(73) > input2(73) 
  input1(74) > input2(74) 
  input1(75) > input2(75) 
  input1(76) > input2(76) 
  input1(77) > input2(77) 
  input1(78) > input2(78) 
  input1(79) > input2(79) 
  input1(80) > input2(80) 
  input1(81) > input2(81) 
  input1(82) > input2(82) 
  input1(83) > input2(83) 
  input1(84) > input2(84) 
  input1(85) > input2(85) 
  input1(86) > input2(86) 
  input1(87) > input2(87) 
  input1(88) > input2(88) 
  input1(89) > input2(89) 
  input1(90) > input2(90) 
  input1(91) > input2(91) 
  input1(92) > input2(92) 
  input1(93) > input2(93) 
  input1(94) > input2(94) 
  input1(95) > input2(95) 
  input1(96) > input2(96) 
  input1(97) > input2(97) 
  input1(98) > input2(98) 
  input1(99) > input2(99) 
  input1(100) > input2(100) 
  input1(101) > input2(101) 
  input1(102) > input2(102) 
  input1(103) > input2(103) 
  input1(104) > input2(104) 
  input1(105) > input2(105) 
  input1(106) > input2(106) 
  input1(107) > input2(107) 
  input1(108) > input2(108) 
  input1(109) > input2(109) 
  input1(110) > input2(110) 
  input1(111) > input2(111) 
  input1(112) > input2(112) 

   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (112/224) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) > input2(1) 
  input1(2) > input2(2) 
  input1(3) > input2(3) 
  input1(4) > input2(4) 
  input1(5) > input2(5) 
  input1(6) > input2(6) 
  input1(7) > input2(7) 
  input1(8) > input2(8) 
  input1(9) > input2(9) 
  input1(10) > input2(10) 
  input1(11) > input2(11) 
  input1(12) > input2(12) 
  input1(13) > input2(13) 
  input1(14) > input2(14) 
  input1(15) > input2(15) 
  input1(16) > input2(16) 
  input1(17) > input2(17) 
  input1(18) > input2(18) 
  input1(19) > input2(19) 
  input1(20) > input2(20) 
  input1(21) > input2(21) 
  input1(22) > input2(22) 
  input1(23) > input2(23) 
  input1(24) > input2(24) 
  input1(25) > input2(25) 
  input1(26) > input2(26) 
  input1(27) > input2(27) 
  input1(28) > input2(28) 
  input1(29) > input2(29) 
  input1(30) > input2(30) 
  input1(31) > input2(31) 
  input1(32) > input2(32) 
  input1(33) > input2(33) 
  input1(34) > input2(34) 
  input1(35) > input2(35) 
  input1(36) > input2(36) 
  input1(37) > input2(37) 
  input1(38) > input2(38) 
  input1(39) > input2(39) 
  input1(40) > input2(40) 
  input1(41) > input2(41) 
  input1(42) > input2(42) 
  input1(43) > input2(43) 
  input1(44) > input2(44) 
  input1(45) > input2(45) 
  input1(46) > input2(46) 
  input1(47) > input2(47) 
  input1(48) > input2(48) 
  input1(49) > input2(49) 
  input1(50) > input2(50) 
  input1(51) > input2(51) 
  input1(52) > input2(52) 
  input1(53) > input2(53) 
  input1(54) > input2(54) 
  input1(55) > input2(55) 
  input1(56) > input2(56) 
  input1(57) > input2(57) 
  input1(58) > input2(58) 
  input1(59) > input2(59) 
  input1(60) > input2(60) 
  input1(61) > input2(61) 
  input1(62) > input2(62) 
  input1(63) > input2(63) 
  input1(64) > input2(64) 
  input1(65) > input2(65) 
  input1(66) > input2(66) 
  input1(67) > input2(67) 
  input1(68) > input2(68) 
  input1(69) > input2(69) 
  input1(70) > input2(70) 
  input1(71) > input2(71) 
  input1(72) > input2(72) 
  input1(73) > input2(73) 
  input1(74) > input2(74) 
  input1(75) > input2(75) 
  input1(76) > input2(76) 
  input1(77) > input2(77) 
  input1(78) > input2(78) 
  input1(79) > input2(79) 
  input1(80) > input2(80) 
  input1(81) > input2(81) 
  input1(82) > input2(82) 
  input1(83) > input2(83) 
  input1(84) > input2(84) 
  input1(85) > input2(85) 
  input1(86) > input2(86) 
  input1(87) > input2(87) 
  input1(88) > input2(88) 
  input1(89) > input2(89) 
  input1(90) > input2(90) 
  input1(91) > input2(91) 
  input1(92) > input2(92) 
  input1(93) > input2(93) 
  input1(94) > input2(94) 
  input1(95) > input2(95) 
  input1(96) > input2(96) 
  input1(97) > input2(97) 
  input1(98) > input2(98) 
  input1(99) > input2(99) 
  input1(100) > input2(100) 
  input1(101) > input2(101) 
  input1(102) > input2(102) 
  input1(103) > input2(103) 
  input1(104) > input2(104) 
  input1(105) > input2(105) 
  input1(106) > input2(106) 
  input1(107) > input2(107) 
  input1(108) > input2(108) 
  input1(109) > input2(109) 
  input1(110) > input2(110) 
  input1(111) > input2(111) 
  input1(112) > input2(112) 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (112/224) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) < input2(1) 
  input1(2) < input2(2) 
  input1(3) < input2(3) 
  input1(4) < input2(4) 
  input1(5) < input2(5) 
  input1(6) < input2(6) 
  input1(7) < input2(7) 
  input1(8) < input2(8) 
  input1(9) < input2(9) 
  input1(10) < input2(10) 
  input1(11) < input2(11) 
  input1(12) < input2(12) 
  input1(13) < input2(13) 
  input1(14) < input2(14) 
  input1(15) < input2(15) 
  input1(16) < input2(16) 
  input1(17) < input2(17) 
  input1(18) < input2(18) 
  input1(19) < input2(19) 
  input1(20) < input2(20) 
  input1(21) < input2(21) 
  input1(22) < input2(22) 
  input1(23) < input2(23) 
  input1(24) < input2(24) 
  input1(25) < input2(25) 
  input1(26) < input2(26) 
  input1(27) < input2(27) 
  input1(28) < input2(28) 
  input1(29) < input2(29) 
  input1(30) < input2(30) 
  input1(31) < input2(31) 
  input1(32) < input2(32) 
  input1(33) < input2(33) 
  input1(34) < input2(34) 
  input1(35) < input2(35) 
  input1(36) < input2(36) 
  input1(37) < input2(37) 
  input1(38) < input2(38) 
  input1(39) < input2(39) 
  input1(40) < input2(40) 
  input1(41) < input2(41) 
  input1(42) < input2(42) 
  input1(43) < input2(43) 
  input1(44) < input2(44) 
  input1(45) < input2(45) 
  input1(46) < input2(46) 
  input1(47) < input2(47) 
  input1(48) < input2(48) 
  input1(49) < input2(49) 
  input1(50) < input2(50) 
  input1(51) < input2(51) 
  input1(52) < input2(52) 
  input1(53) < input2(53) 
  input1(54) < input2(54) 
  input1(55) < input2(55) 
  input1(56) < input2(56) 
  input1(57) < input2(57) 
  input1(58) < input2(58) 
  input1(59) < input2(59) 
  input1(60) < input2(60) 
  input1(61) < input2(61) 
  input1(62) < input2(62) 
  input1(63) < input2(63) 
  input1(64) < input2(64) 
  input1(65) < input2(65) 
  input1(66) < input2(66) 
  input1(67) < input2(67) 
  input1(68) < input2(68) 
  input1(69) < input2(69) 
  input1(70) < input2(70) 
  input1(71) < input2(71) 
  input1(72) < input2(72) 
  input1(73) < input2(73) 
  input1(74) < input2(74) 
  input1(75) < input2(75) 
  input1(76) < input2(76) 
  input1(77) < input2(77) 
  input1(78) < input2(78) 
  input1(79) < input2(79) 
  input1(80) < input2(80) 
  input1(81) < input2(81) 
  input1(82) < input2(82) 
  input1(83) < input2(83) 
  input1(84) < input2(84) 
  input1(85) < input2(85) 
  input1(86) < input2(86) 
  input1(87) < input2(87) 
  input1(88) < input2(88) 
  input1(89) < input2(89) 
  input1(90) < input2(90) 
  input1(91) < input2(91) 
  input1(92) < input2(92) 
  input1(93) < input2(93) 
  input1(94) < input2(94) 
  input1(95) < input2(95) 
  input1(96) < input2(96) 
  input1(97) < input2(97) 
  input1(98) < input2(98) 
  input1(99) < input2(99) 
  input1(100) < input2(100) 
  input1(101) < input2(101) 
  input1(102) < input2(102) 
  input1(103) < input2(103) 
  input1(104) < input2(104) 
  input1(105) < input2(105) 
  input1(106) < input2(106) 
  input1(107) < input2(107) 
  input1(108) < input2(108) 
  input1(109) < input2(109) 
  input1(110) < input2(110) 
  input1(111) < input2(111) 
  input1(112) < input2(112) 

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison5"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (112/224) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) < input2(1) 
  input1(2) < input2(2) 
  input1(3) < input2(3) 
  input1(4) < input2(4) 
  input1(5) < input2(5) 
  input1(6) < input2(6) 
  input1(7) < input2(7) 
  input1(8) < input2(8) 
  input1(9) < input2(9) 
  input1(10) < input2(10) 
  input1(11) < input2(11) 
  input1(12) < input2(12) 
  input1(13) < input2(13) 
  input1(14) < input2(14) 
  input1(15) < input2(15) 
  input1(16) < input2(16) 
  input1(17) < input2(17) 
  input1(18) < input2(18) 
  input1(19) < input2(19) 
  input1(20) < input2(20) 
  input1(21) < input2(21) 
  input1(22) < input2(22) 
  input1(23) < input2(23) 
  input1(24) < input2(24) 
  input1(25) < input2(25) 
  input1(26) < input2(26) 
  input1(27) < input2(27) 
  input1(28) < input2(28) 
  input1(29) < input2(29) 
  input1(30) < input2(30) 
  input1(31) < input2(31) 
  input1(32) < input2(32) 
  input1(33) < input2(33) 
  input1(34) < input2(34) 
  input1(35) < input2(35) 
  input1(36) < input2(36) 
  input1(37) < input2(37) 
  input1(38) < input2(38) 
  input1(39) < input2(39) 
  input1(40) < input2(40) 
  input1(41) < input2(41) 
  input1(42) < input2(42) 
  input1(43) < input2(43) 
  input1(44) < input2(44) 
  input1(45) < input2(45) 
  input1(46) < input2(46) 
  input1(47) < input2(47) 
  input1(48) < input2(48) 
  input1(49) < input2(49) 
  input1(50) < input2(50) 
  input1(51) < input2(51) 
  input1(52) < input2(52) 
  input1(53) < input2(53) 
  input1(54) < input2(54) 
  input1(55) < input2(55) 
  input1(56) < input2(56) 
  input1(57) < input2(57) 
  input1(58) < input2(58) 
  input1(59) < input2(59) 
  input1(60) < input2(60) 
  input1(61) < input2(61) 
  input1(62) < input2(62) 
  input1(63) < input2(63) 
  input1(64) < input2(64) 
  input1(65) < input2(65) 
  input1(66) < input2(66) 
  input1(67) < input2(67) 
  input1(68) < input2(68) 
  input1(69) < input2(69) 
  input1(70) < input2(70) 
  input1(71) < input2(71) 
  input1(72) < input2(72) 
  input1(73) < input2(73) 
  input1(74) < input2(74) 
  input1(75) < input2(75) 
  input1(76) < input2(76) 
  input1(77) < input2(77) 
  input1(78) < input2(78) 
  input1(79) < input2(79) 
  input1(80) < input2(80) 
  input1(81) < input2(81) 
  input1(82) < input2(82) 
  input1(83) < input2(83) 
  input1(84) < input2(84) 
  input1(85) < input2(85) 
  input1(86) < input2(86) 
  input1(87) < input2(87) 
  input1(88) < input2(88) 
  input1(89) < input2(89) 
  input1(90) < input2(90) 
  input1(91) < input2(91) 
  input1(92) < input2(92) 
  input1(93) < input2(93) 
  input1(94) < input2(94) 
  input1(95) < input2(95) 
  input1(96) < input2(96) 
  input1(97) < input2(97) 
  input1(98) < input2(98) 
  input1(99) < input2(99) 
  input1(100) < input2(100) 
  input1(101) < input2(101) 
  input1(102) < input2(102) 
  input1(103) < input2(103) 
  input1(104) < input2(104) 
  input1(105) < input2(105) 
  input1(106) < input2(106) 
  input1(107) < input2(107) 
  input1(108) < input2(108) 
  input1(109) < input2(109) 
  input1(110) < input2(110) 
  input1(111) < input2(111) 
  input1(112) < input2(112) 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant1" Execution
Constant block "Constant5" Execution
DataStoreWrite block "Data Store Write" Execution

6. SubSystem block "GbNDP_ReadAllCellCapVld_flgOverWrite"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/GbNDP_ReadAllCellCapVld_flgOverWrite
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

7. SubSystem block "NDP_1D_Config_Word"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap
Child Systems: Switch Case Action Subsystem,  Switch Case Action Subsystem1,  Switch Case Action Subsystem2,  Switch Case Action Subsystem3,  Switch Case Action Subsystem4,  Switch Case Action Subsystem5,  Switch Case Action Subsystem6,  Switch Case Action Subsystem7,  Switch Case Action Subsystem8,  Switch Case Action Subsystem9

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 11
Decision NA 9% (1/11) decision outcomes
Execution NA 100% (12/12) objective outcomes

   SwitchCase block "Switch Case"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 10
Decision 9% (1/11) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  truncated input  9%
      = Enum_UDSCapSel_Default 1/1
      = Enum_UDSCapSel_CATL153Ah 0/1
      = Enum_UDSCapSel_CATL180Ah 0/1
      = Enum_UDSCapSel_CATL177Ah 0/1
      = Enum_UDSCapSel_CATL203Ah 0/1
      = Enum_UDSCapSel_CATL51Ah 0/1
      = Enum_UDSCapSel_CATL132Ah 0/1
      = Enum_UDSCapSel_XWD75Ah 0/1
      = Enum_UDSCapSel_TFE177Ah 0/1
      = Enum_UDSCapSel_CATLCTP248Ah 0/1
      = implicit-default 0/1

   Full Coverage

Model Object Metric
DataTypeConversion block "Data Type Conversion" Execution

8. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

9. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

10. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

11. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

12. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

13. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

14. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

15. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

16. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

17. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

18. SubSystem block "NDP_1D_Config_Word1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap
Child Systems: Switch Case Action Subsystem,  Switch Case Action Subsystem1,  Switch Case Action Subsystem2,  Switch Case Action Subsystem3,  Switch Case Action Subsystem4,  Switch Case Action Subsystem5,  Switch Case Action Subsystem6,  Switch Case Action Subsystem7,  Switch Case Action Subsystem8,  Switch Case Action Subsystem9

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 11
Decision NA 9% (1/11) decision outcomes
Execution NA 100% (12/12) objective outcomes

   SwitchCase block "Switch Case"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 10
Decision 9% (1/11) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  truncated input  9%
      = Enum_UDSCapSel_Default 1/1
      = Enum_UDSCapSel_CATL153Ah 0/1
      = Enum_UDSCapSel_CATL180Ah 0/1
      = Enum_UDSCapSel_CATL177Ah 0/1
      = Enum_UDSCapSel_CATL203Ah 0/1
      = Enum_UDSCapSel_CATL51Ah 0/1
      = Enum_UDSCapSel_CATL132Ah 0/1
      = Enum_UDSCapSel_XWD75Ah 0/1
      = Enum_UDSCapSel_TFE177Ah 0/1
      = Enum_UDSCapSel_CATLCTP248Ah 0/1
      = implicit-default 0/1

   Full Coverage

Model Object Metric
DataTypeConversion block "Data Type Conversion" Execution

19. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

20. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

21. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

22. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

23. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

24. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

25. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

26. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

27. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

28. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

29. SubSystem block "NDP_1D_Config_Word2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap
Child Systems: Switch Case Action Subsystem,  Switch Case Action Subsystem1,  Switch Case Action Subsystem2,  Switch Case Action Subsystem3,  Switch Case Action Subsystem4,  Switch Case Action Subsystem5,  Switch Case Action Subsystem6,  Switch Case Action Subsystem7,  Switch Case Action Subsystem8,  Switch Case Action Subsystem9

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 11
Decision NA 9% (1/11) decision outcomes
Execution NA 100% (12/12) objective outcomes

   SwitchCase block "Switch Case"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 10
Decision 9% (1/11) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  truncated input  9%
      = Enum_UDSCapSel_Default 1/1
      = Enum_UDSCapSel_CATL153Ah 0/1
      = Enum_UDSCapSel_CATL180Ah 0/1
      = Enum_UDSCapSel_CATL177Ah 0/1
      = Enum_UDSCapSel_CATL203Ah 0/1
      = Enum_UDSCapSel_CATL51Ah 0/1
      = Enum_UDSCapSel_CATL132Ah 0/1
      = Enum_UDSCapSel_XWD75Ah 0/1
      = Enum_UDSCapSel_TFE177Ah 0/1
      = Enum_UDSCapSel_CATLCTP248Ah 0/1
      = implicit-default 0/1

   Full Coverage

Model Object Metric
DataTypeConversion block "Data Type Conversion" Execution

30. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

31. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

32. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

33. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

34. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

35. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

36. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

37. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

38. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

39. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellCap/NDP_1D_Config_Word2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

40. SubSystem block "AllCellOCVSOC"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GaNDP_ReadAllCellOCVSOCVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 226
Condition NA 50% (1124/2248) condition outcomes
Decision NA 50% (225/450) decision outcomes
MCDC NA 0% (0/896) conditions reversed the outcome
Execution NA 100% (22/22) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellOCVSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (225/450) condition outcomes
MCDC 0% (0/336) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port1(1) 
  input port1(2) 
  input port1(3) 
  input port1(4) 
  input port1(5) 
  input port1(6) 
  input port1(7) 
  input port1(8) 
  input port1(9) 
  input port1(10) 
  input port1(11) 
  input port1(12) 
  input port1(13) 
  input port1(14) 
  input port1(15) 
  input port1(16) 
  input port1(17) 
  input port1(18) 
  input port1(19) 
  input port1(20) 
  input port1(21) 
  input port1(22) 
  input port1(23) 
  input port1(24) 
  input port1(25) 
  input port1(26) 
  input port1(27) 
  input port1(28) 
  input port1(29) 
  input port1(30) 
  input port1(31) 
  input port1(32) 
  input port1(33) 
  input port1(34) 
  input port1(35) 
  input port1(36) 
  input port1(37) 
  input port1(38) 
  input port1(39) 
  input port1(40) 
  input port1(41) 
  input port1(42) 
  input port1(43) 
  input port1(44) 
  input port1(45) 
  input port1(46) 
  input port1(47) 
  input port1(48) 
  input port1(49) 
  input port1(50) 
  input port1(51) 
  input port1(52) 
  input port1(53) 
  input port1(54) 
  input port1(55) 
  input port1(56) 
  input port1(57) 
  input port1(58) 
  input port1(59) 
  input port1(60) 
  input port1(61) 
  input port1(62) 
  input port1(63) 
  input port1(64) 
  input port1(65) 
  input port1(66) 
  input port1(67) 
  input port1(68) 
  input port1(69) 
  input port1(70) 
  input port1(71) 
  input port1(72) 
  input port1(73) 
  input port1(74) 
  input port1(75) 
  input port1(76) 
  input port1(77) 
  input port1(78) 
  input port1(79) 
  input port1(80) 
  input port1(81) 
  input port1(82) 
  input port1(83) 
  input port1(84) 
  input port1(85) 
  input port1(86) 
  input port1(87) 
  input port1(88) 
  input port1(89) 
  input port1(90) 
  input port1(91) 
  input port1(92) 
  input port1(93) 
  input port1(94) 
  input port1(95) 
  input port1(96) 
  input port1(97) 
  input port1(98) 
  input port1(99) 
  input port1(100) 
  input port1(101) 
  input port1(102) 
  input port1(103) 
  input port1(104) 
  input port1(105) 
  input port1(106) 
  input port1(107) 
  input port1(108) 
  input port1(109) 
  input port1(110) 
  input port1(111) 
  input port1(112) 
  input port2(1) 
  input port2(2) 
  input port2(3) 
  input port2(4) 
  input port2(5) 
  input port2(6) 
  input port2(7) 
  input port2(8) 
  input port2(9) 
  input port2(10) 
  input port2(11) 
  input port2(12) 
  input port2(13) 
  input port2(14) 
  input port2(15) 
  input port2(16) 
  input port2(17) 
  input port2(18) 
  input port2(19) 
  input port2(20) 
  input port2(21) 
  input port2(22) 
  input port2(23) 
  input port2(24) 
  input port2(25) 
  input port2(26) 
  input port2(27) 
  input port2(28) 
  input port2(29) 
  input port2(30) 
  input port2(31) 
  input port2(32) 
  input port2(33) 
  input port2(34) 
  input port2(35) 
  input port2(36) 
  input port2(37) 
  input port2(38) 
  input port2(39) 
  input port2(40) 
  input port2(41) 
  input port2(42) 
  input port2(43) 
  input port2(44) 
  input port2(45) 
  input port2(46) 
  input port2(47) 
  input port2(48) 
  input port2(49) 
  input port2(50) 
  input port2(51) 
  input port2(52) 
  input port2(53) 
  input port2(54) 
  input port2(55) 
  input port2(56) 
  input port2(57) 
  input port2(58) 
  input port2(59) 
  input port2(60) 
  input port2(61) 
  input port2(62) 
  input port2(63) 
  input port2(64) 
  input port2(65) 
  input port2(66) 
  input port2(67) 
  input port2(68) 
  input port2(69) 
  input port2(70) 
  input port2(71) 
  input port2(72) 
  input port2(73) 
  input port2(74) 
  input port2(75) 
  input port2(76) 
  input port2(77) 
  input port2(78) 
  input port2(79) 
  input port2(80) 
  input port2(81) 
  input port2(82) 
  input port2(83) 
  input port2(84) 
  input port2(85) 
  input port2(86) 
  input port2(87) 
  input port2(88) 
  input port2(89) 
  input port2(90) 
  input port2(91) 
  input port2(92) 
  input port2(93) 
  input port2(94) 
  input port2(95) 
  input port2(96) 
  input port2(97) 
  input port2(98) 
  input port2(99) 
  input port2(100) 
  input port2(101) 
  input port2(102) 
  input port2(103) 
  input port2(104) 
  input port2(105) 
  input port2(106) 
  input port2(107) 
  input port2(108) 
  input port2(109) 
  input port2(110) 
  input port2(111) 
  input port2(112) 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output(1)
      input port1(1) (TTT) (FTT)
      input port2(1) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(2)
      input port1(2) (TTT) (FTT)
      input port2(2) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(3)
      input port1(3) (TTT) (FTT)
      input port2(3) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(4)
      input port1(4) (TTT) (FTT)
      input port2(4) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(5)
      input port1(5) (TTT) (FTT)
      input port2(5) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(6)
      input port1(6) (TTT) (FTT)
      input port2(6) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(7)
      input port1(7) (TTT) (FTT)
      input port2(7) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(8)
      input port1(8) (TTT) (FTT)
      input port2(8) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(9)
      input port1(9) (TTT) (FTT)
      input port2(9) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(10)
      input port1(10) (TTT) (FTT)
      input port2(10) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(11)
      input port1(11) (TTT) (FTT)
      input port2(11) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(12)
      input port1(12) (TTT) (FTT)
      input port2(12) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(13)
      input port1(13) (TTT) (FTT)
      input port2(13) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(14)
      input port1(14) (TTT) (FTT)
      input port2(14) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(15)
      input port1(15) (TTT) (FTT)
      input port2(15) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(16)
      input port1(16) (TTT) (FTT)
      input port2(16) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(17)
      input port1(17) (TTT) (FTT)
      input port2(17) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(18)
      input port1(18) (TTT) (FTT)
      input port2(18) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(19)
      input port1(19) (TTT) (FTT)
      input port2(19) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(20)
      input port1(20) (TTT) (FTT)
      input port2(20) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(21)
      input port1(21) (TTT) (FTT)
      input port2(21) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(22)
      input port1(22) (TTT) (FTT)
      input port2(22) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(23)
      input port1(23) (TTT) (FTT)
      input port2(23) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(24)
      input port1(24) (TTT) (FTT)
      input port2(24) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(25)
      input port1(25) (TTT) (FTT)
      input port2(25) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(26)
      input port1(26) (TTT) (FTT)
      input port2(26) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(27)
      input port1(27) (TTT) (FTT)
      input port2(27) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(28)
      input port1(28) (TTT) (FTT)
      input port2(28) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(29)
      input port1(29) (TTT) (FTT)
      input port2(29) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(30)
      input port1(30) (TTT) (FTT)
      input port2(30) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(31)
      input port1(31) (TTT) (FTT)
      input port2(31) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(32)
      input port1(32) (TTT) (FTT)
      input port2(32) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(33)
      input port1(33) (TTT) (FTT)
      input port2(33) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(34)
      input port1(34) (TTT) (FTT)
      input port2(34) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(35)
      input port1(35) (TTT) (FTT)
      input port2(35) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(36)
      input port1(36) (TTT) (FTT)
      input port2(36) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(37)
      input port1(37) (TTT) (FTT)
      input port2(37) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(38)
      input port1(38) (TTT) (FTT)
      input port2(38) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(39)
      input port1(39) (TTT) (FTT)
      input port2(39) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(40)
      input port1(40) (TTT) (FTT)
      input port2(40) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(41)
      input port1(41) (TTT) (FTT)
      input port2(41) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(42)
      input port1(42) (TTT) (FTT)
      input port2(42) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(43)
      input port1(43) (TTT) (FTT)
      input port2(43) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(44)
      input port1(44) (TTT) (FTT)
      input port2(44) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(45)
      input port1(45) (TTT) (FTT)
      input port2(45) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(46)
      input port1(46) (TTT) (FTT)
      input port2(46) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(47)
      input port1(47) (TTT) (FTT)
      input port2(47) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(48)
      input port1(48) (TTT) (FTT)
      input port2(48) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(49)
      input port1(49) (TTT) (FTT)
      input port2(49) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(50)
      input port1(50) (TTT) (FTT)
      input port2(50) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(51)
      input port1(51) (TTT) (FTT)
      input port2(51) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(52)
      input port1(52) (TTT) (FTT)
      input port2(52) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(53)
      input port1(53) (TTT) (FTT)
      input port2(53) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(54)
      input port1(54) (TTT) (FTT)
      input port2(54) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(55)
      input port1(55) (TTT) (FTT)
      input port2(55) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(56)
      input port1(56) (TTT) (FTT)
      input port2(56) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(57)
      input port1(57) (TTT) (FTT)
      input port2(57) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(58)
      input port1(58) (TTT) (FTT)
      input port2(58) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(59)
      input port1(59) (TTT) (FTT)
      input port2(59) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(60)
      input port1(60) (TTT) (FTT)
      input port2(60) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(61)
      input port1(61) (TTT) (FTT)
      input port2(61) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(62)
      input port1(62) (TTT) (FTT)
      input port2(62) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(63)
      input port1(63) (TTT) (FTT)
      input port2(63) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(64)
      input port1(64) (TTT) (FTT)
      input port2(64) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(65)
      input port1(65) (TTT) (FTT)
      input port2(65) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(66)
      input port1(66) (TTT) (FTT)
      input port2(66) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(67)
      input port1(67) (TTT) (FTT)
      input port2(67) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(68)
      input port1(68) (TTT) (FTT)
      input port2(68) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(69)
      input port1(69) (TTT) (FTT)
      input port2(69) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(70)
      input port1(70) (TTT) (FTT)
      input port2(70) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(71)
      input port1(71) (TTT) (FTT)
      input port2(71) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(72)
      input port1(72) (TTT) (FTT)
      input port2(72) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(73)
      input port1(73) (TTT) (FTT)
      input port2(73) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(74)
      input port1(74) (TTT) (FTT)
      input port2(74) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(75)
      input port1(75) (TTT) (FTT)
      input port2(75) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(76)
      input port1(76) (TTT) (FTT)
      input port2(76) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(77)
      input port1(77) (TTT) (FTT)
      input port2(77) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(78)
      input port1(78) (TTT) (FTT)
      input port2(78) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(79)
      input port1(79) (TTT) (FTT)
      input port2(79) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(80)
      input port1(80) (TTT) (FTT)
      input port2(80) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(81)
      input port1(81) (TTT) (FTT)
      input port2(81) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(82)
      input port1(82) (TTT) (FTT)
      input port2(82) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(83)
      input port1(83) (TTT) (FTT)
      input port2(83) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(84)
      input port1(84) (TTT) (FTT)
      input port2(84) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(85)
      input port1(85) (TTT) (FTT)
      input port2(85) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(86)
      input port1(86) (TTT) (FTT)
      input port2(86) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(87)
      input port1(87) (TTT) (FTT)
      input port2(87) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(88)
      input port1(88) (TTT) (FTT)
      input port2(88) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(89)
      input port1(89) (TTT) (FTT)
      input port2(89) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(90)
      input port1(90) (TTT) (FTT)
      input port2(90) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(91)
      input port1(91) (TTT) (FTT)
      input port2(91) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(92)
      input port1(92) (TTT) (FTT)
      input port2(92) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(93)
      input port1(93) (TTT) (FTT)
      input port2(93) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(94)
      input port1(94) (TTT) (FTT)
      input port2(94) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(95)
      input port1(95) (TTT) (FTT)
      input port2(95) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(96)
      input port1(96) (TTT) (FTT)
      input port2(96) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(97)
      input port1(97) (TTT) (FTT)
      input port2(97) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(98)
      input port1(98) (TTT) (FTT)
      input port2(98) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(99)
      input port1(99) (TTT) (FTT)
      input port2(99) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(100)
      input port1(100) (TTT) (FTT)
      input port2(100) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(101)
      input port1(101) (TTT) (FTT)
      input port2(101) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(102)
      input port1(102) (TTT) (FTT)
      input port2(102) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(103)
      input port1(103) (TTT) (FTT)
      input port2(103) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(104)
      input port1(104) (TTT) (FTT)
      input port2(104) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(105)
      input port1(105) (TTT) (FTT)
      input port2(105) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(106)
      input port1(106) (TTT) (FTT)
      input port2(106) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(107)
      input port1(107) (TTT) (FTT)
      input port2(107) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(108)
      input port1(108) (TTT) (FTT)
      input port2(108) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(109)
      input port1(109) (TTT) (FTT)
      input port2(109) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(110)
      input port1(110) (TTT) (FTT)
      input port2(110) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(111)
      input port1(111) (TTT) (FTT)
      input port2(111) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(112)
      input port1(112) (TTT) (FTT)
      input port2(112) (TTT) (TFT)
      input port 3 (TTT) TTF


   Logic block "Logical1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellOCVSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (225/450) condition outcomes
MCDC 0% (0/336) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port1(1) 
  input port1(2) 
  input port1(3) 
  input port1(4) 
  input port1(5) 
  input port1(6) 
  input port1(7) 
  input port1(8) 
  input port1(9) 
  input port1(10) 
  input port1(11) 
  input port1(12) 
  input port1(13) 
  input port1(14) 
  input port1(15) 
  input port1(16) 
  input port1(17) 
  input port1(18) 
  input port1(19) 
  input port1(20) 
  input port1(21) 
  input port1(22) 
  input port1(23) 
  input port1(24) 
  input port1(25) 
  input port1(26) 
  input port1(27) 
  input port1(28) 
  input port1(29) 
  input port1(30) 
  input port1(31) 
  input port1(32) 
  input port1(33) 
  input port1(34) 
  input port1(35) 
  input port1(36) 
  input port1(37) 
  input port1(38) 
  input port1(39) 
  input port1(40) 
  input port1(41) 
  input port1(42) 
  input port1(43) 
  input port1(44) 
  input port1(45) 
  input port1(46) 
  input port1(47) 
  input port1(48) 
  input port1(49) 
  input port1(50) 
  input port1(51) 
  input port1(52) 
  input port1(53) 
  input port1(54) 
  input port1(55) 
  input port1(56) 
  input port1(57) 
  input port1(58) 
  input port1(59) 
  input port1(60) 
  input port1(61) 
  input port1(62) 
  input port1(63) 
  input port1(64) 
  input port1(65) 
  input port1(66) 
  input port1(67) 
  input port1(68) 
  input port1(69) 
  input port1(70) 
  input port1(71) 
  input port1(72) 
  input port1(73) 
  input port1(74) 
  input port1(75) 
  input port1(76) 
  input port1(77) 
  input port1(78) 
  input port1(79) 
  input port1(80) 
  input port1(81) 
  input port1(82) 
  input port1(83) 
  input port1(84) 
  input port1(85) 
  input port1(86) 
  input port1(87) 
  input port1(88) 
  input port1(89) 
  input port1(90) 
  input port1(91) 
  input port1(92) 
  input port1(93) 
  input port1(94) 
  input port1(95) 
  input port1(96) 
  input port1(97) 
  input port1(98) 
  input port1(99) 
  input port1(100) 
  input port1(101) 
  input port1(102) 
  input port1(103) 
  input port1(104) 
  input port1(105) 
  input port1(106) 
  input port1(107) 
  input port1(108) 
  input port1(109) 
  input port1(110) 
  input port1(111) 
  input port1(112) 
  input port2(1) 
  input port2(2) 
  input port2(3) 
  input port2(4) 
  input port2(5) 
  input port2(6) 
  input port2(7) 
  input port2(8) 
  input port2(9) 
  input port2(10) 
  input port2(11) 
  input port2(12) 
  input port2(13) 
  input port2(14) 
  input port2(15) 
  input port2(16) 
  input port2(17) 
  input port2(18) 
  input port2(19) 
  input port2(20) 
  input port2(21) 
  input port2(22) 
  input port2(23) 
  input port2(24) 
  input port2(25) 
  input port2(26) 
  input port2(27) 
  input port2(28) 
  input port2(29) 
  input port2(30) 
  input port2(31) 
  input port2(32) 
  input port2(33) 
  input port2(34) 
  input port2(35) 
  input port2(36) 
  input port2(37) 
  input port2(38) 
  input port2(39) 
  input port2(40) 
  input port2(41) 
  input port2(42) 
  input port2(43) 
  input port2(44) 
  input port2(45) 
  input port2(46) 
  input port2(47) 
  input port2(48) 
  input port2(49) 
  input port2(50) 
  input port2(51) 
  input port2(52) 
  input port2(53) 
  input port2(54) 
  input port2(55) 
  input port2(56) 
  input port2(57) 
  input port2(58) 
  input port2(59) 
  input port2(60) 
  input port2(61) 
  input port2(62) 
  input port2(63) 
  input port2(64) 
  input port2(65) 
  input port2(66) 
  input port2(67) 
  input port2(68) 
  input port2(69) 
  input port2(70) 
  input port2(71) 
  input port2(72) 
  input port2(73) 
  input port2(74) 
  input port2(75) 
  input port2(76) 
  input port2(77) 
  input port2(78) 
  input port2(79) 
  input port2(80) 
  input port2(81) 
  input port2(82) 
  input port2(83) 
  input port2(84) 
  input port2(85) 
  input port2(86) 
  input port2(87) 
  input port2(88) 
  input port2(89) 
  input port2(90) 
  input port2(91) 
  input port2(92) 
  input port2(93) 
  input port2(94) 
  input port2(95) 
  input port2(96) 
  input port2(97) 
  input port2(98) 
  input port2(99) 
  input port2(100) 
  input port2(101) 
  input port2(102) 
  input port2(103) 
  input port2(104) 
  input port2(105) 
  input port2(106) 
  input port2(107) 
  input port2(108) 
  input port2(109) 
  input port2(110) 
  input port2(111) 
  input port2(112) 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output(1)
      input port1(1) (TTT) (FTT)
      input port2(1) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(2)
      input port1(2) (TTT) (FTT)
      input port2(2) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(3)
      input port1(3) (TTT) (FTT)
      input port2(3) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(4)
      input port1(4) (TTT) (FTT)
      input port2(4) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(5)
      input port1(5) (TTT) (FTT)
      input port2(5) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(6)
      input port1(6) (TTT) (FTT)
      input port2(6) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(7)
      input port1(7) (TTT) (FTT)
      input port2(7) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(8)
      input port1(8) (TTT) (FTT)
      input port2(8) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(9)
      input port1(9) (TTT) (FTT)
      input port2(9) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(10)
      input port1(10) (TTT) (FTT)
      input port2(10) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(11)
      input port1(11) (TTT) (FTT)
      input port2(11) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(12)
      input port1(12) (TTT) (FTT)
      input port2(12) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(13)
      input port1(13) (TTT) (FTT)
      input port2(13) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(14)
      input port1(14) (TTT) (FTT)
      input port2(14) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(15)
      input port1(15) (TTT) (FTT)
      input port2(15) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(16)
      input port1(16) (TTT) (FTT)
      input port2(16) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(17)
      input port1(17) (TTT) (FTT)
      input port2(17) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(18)
      input port1(18) (TTT) (FTT)
      input port2(18) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(19)
      input port1(19) (TTT) (FTT)
      input port2(19) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(20)
      input port1(20) (TTT) (FTT)
      input port2(20) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(21)
      input port1(21) (TTT) (FTT)
      input port2(21) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(22)
      input port1(22) (TTT) (FTT)
      input port2(22) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(23)
      input port1(23) (TTT) (FTT)
      input port2(23) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(24)
      input port1(24) (TTT) (FTT)
      input port2(24) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(25)
      input port1(25) (TTT) (FTT)
      input port2(25) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(26)
      input port1(26) (TTT) (FTT)
      input port2(26) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(27)
      input port1(27) (TTT) (FTT)
      input port2(27) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(28)
      input port1(28) (TTT) (FTT)
      input port2(28) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(29)
      input port1(29) (TTT) (FTT)
      input port2(29) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(30)
      input port1(30) (TTT) (FTT)
      input port2(30) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(31)
      input port1(31) (TTT) (FTT)
      input port2(31) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(32)
      input port1(32) (TTT) (FTT)
      input port2(32) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(33)
      input port1(33) (TTT) (FTT)
      input port2(33) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(34)
      input port1(34) (TTT) (FTT)
      input port2(34) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(35)
      input port1(35) (TTT) (FTT)
      input port2(35) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(36)
      input port1(36) (TTT) (FTT)
      input port2(36) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(37)
      input port1(37) (TTT) (FTT)
      input port2(37) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(38)
      input port1(38) (TTT) (FTT)
      input port2(38) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(39)
      input port1(39) (TTT) (FTT)
      input port2(39) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(40)
      input port1(40) (TTT) (FTT)
      input port2(40) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(41)
      input port1(41) (TTT) (FTT)
      input port2(41) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(42)
      input port1(42) (TTT) (FTT)
      input port2(42) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(43)
      input port1(43) (TTT) (FTT)
      input port2(43) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(44)
      input port1(44) (TTT) (FTT)
      input port2(44) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(45)
      input port1(45) (TTT) (FTT)
      input port2(45) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(46)
      input port1(46) (TTT) (FTT)
      input port2(46) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(47)
      input port1(47) (TTT) (FTT)
      input port2(47) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(48)
      input port1(48) (TTT) (FTT)
      input port2(48) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(49)
      input port1(49) (TTT) (FTT)
      input port2(49) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(50)
      input port1(50) (TTT) (FTT)
      input port2(50) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(51)
      input port1(51) (TTT) (FTT)
      input port2(51) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(52)
      input port1(52) (TTT) (FTT)
      input port2(52) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(53)
      input port1(53) (TTT) (FTT)
      input port2(53) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(54)
      input port1(54) (TTT) (FTT)
      input port2(54) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(55)
      input port1(55) (TTT) (FTT)
      input port2(55) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(56)
      input port1(56) (TTT) (FTT)
      input port2(56) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(57)
      input port1(57) (TTT) (FTT)
      input port2(57) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(58)
      input port1(58) (TTT) (FTT)
      input port2(58) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(59)
      input port1(59) (TTT) (FTT)
      input port2(59) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(60)
      input port1(60) (TTT) (FTT)
      input port2(60) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(61)
      input port1(61) (TTT) (FTT)
      input port2(61) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(62)
      input port1(62) (TTT) (FTT)
      input port2(62) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(63)
      input port1(63) (TTT) (FTT)
      input port2(63) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(64)
      input port1(64) (TTT) (FTT)
      input port2(64) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(65)
      input port1(65) (TTT) (FTT)
      input port2(65) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(66)
      input port1(66) (TTT) (FTT)
      input port2(66) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(67)
      input port1(67) (TTT) (FTT)
      input port2(67) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(68)
      input port1(68) (TTT) (FTT)
      input port2(68) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(69)
      input port1(69) (TTT) (FTT)
      input port2(69) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(70)
      input port1(70) (TTT) (FTT)
      input port2(70) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(71)
      input port1(71) (TTT) (FTT)
      input port2(71) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(72)
      input port1(72) (TTT) (FTT)
      input port2(72) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(73)
      input port1(73) (TTT) (FTT)
      input port2(73) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(74)
      input port1(74) (TTT) (FTT)
      input port2(74) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(75)
      input port1(75) (TTT) (FTT)
      input port2(75) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(76)
      input port1(76) (TTT) (FTT)
      input port2(76) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(77)
      input port1(77) (TTT) (FTT)
      input port2(77) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(78)
      input port1(78) (TTT) (FTT)
      input port2(78) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(79)
      input port1(79) (TTT) (FTT)
      input port2(79) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(80)
      input port1(80) (TTT) (FTT)
      input port2(80) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(81)
      input port1(81) (TTT) (FTT)
      input port2(81) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(82)
      input port1(82) (TTT) (FTT)
      input port2(82) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(83)
      input port1(83) (TTT) (FTT)
      input port2(83) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(84)
      input port1(84) (TTT) (FTT)
      input port2(84) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(85)
      input port1(85) (TTT) (FTT)
      input port2(85) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(86)
      input port1(86) (TTT) (FTT)
      input port2(86) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(87)
      input port1(87) (TTT) (FTT)
      input port2(87) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(88)
      input port1(88) (TTT) (FTT)
      input port2(88) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(89)
      input port1(89) (TTT) (FTT)
      input port2(89) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(90)
      input port1(90) (TTT) (FTT)
      input port2(90) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(91)
      input port1(91) (TTT) (FTT)
      input port2(91) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(92)
      input port1(92) (TTT) (FTT)
      input port2(92) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(93)
      input port1(93) (TTT) (FTT)
      input port2(93) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(94)
      input port1(94) (TTT) (FTT)
      input port2(94) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(95)
      input port1(95) (TTT) (FTT)
      input port2(95) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(96)
      input port1(96) (TTT) (FTT)
      input port2(96) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(97)
      input port1(97) (TTT) (FTT)
      input port2(97) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(98)
      input port1(98) (TTT) (FTT)
      input port2(98) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(99)
      input port1(99) (TTT) (FTT)
      input port2(99) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(100)
      input port1(100) (TTT) (FTT)
      input port2(100) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(101)
      input port1(101) (TTT) (FTT)
      input port2(101) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(102)
      input port1(102) (TTT) (FTT)
      input port2(102) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(103)
      input port1(103) (TTT) (FTT)
      input port2(103) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(104)
      input port1(104) (TTT) (FTT)
      input port2(104) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(105)
      input port1(105) (TTT) (FTT)
      input port2(105) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(106)
      input port1(106) (TTT) (FTT)
      input port2(106) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(107)
      input port1(107) (TTT) (FTT)
      input port2(107) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(108)
      input port1(108) (TTT) (FTT)
      input port2(108) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(109)
      input port1(109) (TTT) (FTT)
      input port2(109) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(110)
      input port1(110) (TTT) (FTT)
      input port2(110) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(111)
      input port1(111) (TTT) (FTT)
      input port2(111) (TTT) (TFT)
      input port 3 (TTT) TTF
expression for output(112)
      input port1(112) (TTT) (FTT)
      input port2(112) (TTT) (TFT)
      input port 3 (TTT) TTF


   Logic block "Logical2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellOCVSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (224/448) condition outcomes
MCDC 0% (0/224) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port1(1) 
  input port1(2) 
  input port1(3) 
  input port1(4) 
  input port1(5) 
  input port1(6) 
  input port1(7) 
  input port1(8) 
  input port1(9) 
  input port1(10) 
  input port1(11) 
  input port1(12) 
  input port1(13) 
  input port1(14) 
  input port1(15) 
  input port1(16) 
  input port1(17) 
  input port1(18) 
  input port1(19) 
  input port1(20) 
  input port1(21) 
  input port1(22) 
  input port1(23) 
  input port1(24) 
  input port1(25) 
  input port1(26) 
  input port1(27) 
  input port1(28) 
  input port1(29) 
  input port1(30) 
  input port1(31) 
  input port1(32) 
  input port1(33) 
  input port1(34) 
  input port1(35) 
  input port1(36) 
  input port1(37) 
  input port1(38) 
  input port1(39) 
  input port1(40) 
  input port1(41) 
  input port1(42) 
  input port1(43) 
  input port1(44) 
  input port1(45) 
  input port1(46) 
  input port1(47) 
  input port1(48) 
  input port1(49) 
  input port1(50) 
  input port1(51) 
  input port1(52) 
  input port1(53) 
  input port1(54) 
  input port1(55) 
  input port1(56) 
  input port1(57) 
  input port1(58) 
  input port1(59) 
  input port1(60) 
  input port1(61) 
  input port1(62) 
  input port1(63) 
  input port1(64) 
  input port1(65) 
  input port1(66) 
  input port1(67) 
  input port1(68) 
  input port1(69) 
  input port1(70) 
  input port1(71) 
  input port1(72) 
  input port1(73) 
  input port1(74) 
  input port1(75) 
  input port1(76) 
  input port1(77) 
  input port1(78) 
  input port1(79) 
  input port1(80) 
  input port1(81) 
  input port1(82) 
  input port1(83) 
  input port1(84) 
  input port1(85) 
  input port1(86) 
  input port1(87) 
  input port1(88) 
  input port1(89) 
  input port1(90) 
  input port1(91) 
  input port1(92) 
  input port1(93) 
  input port1(94) 
  input port1(95) 
  input port1(96) 
  input port1(97) 
  input port1(98) 
  input port1(99) 
  input port1(100) 
  input port1(101) 
  input port1(102) 
  input port1(103) 
  input port1(104) 
  input port1(105) 
  input port1(106) 
  input port1(107) 
  input port1(108) 
  input port1(109) 
  input port1(110) 
  input port1(111) 
  input port1(112) 
  input port2(1) 
  input port2(2) 
  input port2(3) 
  input port2(4) 
  input port2(5) 
  input port2(6) 
  input port2(7) 
  input port2(8) 
  input port2(9) 
  input port2(10) 
  input port2(11) 
  input port2(12) 
  input port2(13) 
  input port2(14) 
  input port2(15) 
  input port2(16) 
  input port2(17) 
  input port2(18) 
  input port2(19) 
  input port2(20) 
  input port2(21) 
  input port2(22) 
  input port2(23) 
  input port2(24) 
  input port2(25) 
  input port2(26) 
  input port2(27) 
  input port2(28) 
  input port2(29) 
  input port2(30) 
  input port2(31) 
  input port2(32) 
  input port2(33) 
  input port2(34) 
  input port2(35) 
  input port2(36) 
  input port2(37) 
  input port2(38) 
  input port2(39) 
  input port2(40) 
  input port2(41) 
  input port2(42) 
  input port2(43) 
  input port2(44) 
  input port2(45) 
  input port2(46) 
  input port2(47) 
  input port2(48) 
  input port2(49) 
  input port2(50) 
  input port2(51) 
  input port2(52) 
  input port2(53) 
  input port2(54) 
  input port2(55) 
  input port2(56) 
  input port2(57) 
  input port2(58) 
  input port2(59) 
  input port2(60) 
  input port2(61) 
  input port2(62) 
  input port2(63) 
  input port2(64) 
  input port2(65) 
  input port2(66) 
  input port2(67) 
  input port2(68) 
  input port2(69) 
  input port2(70) 
  input port2(71) 
  input port2(72) 
  input port2(73) 
  input port2(74) 
  input port2(75) 
  input port2(76) 
  input port2(77) 
  input port2(78) 
  input port2(79) 
  input port2(80) 
  input port2(81) 
  input port2(82) 
  input port2(83) 
  input port2(84) 
  input port2(85) 
  input port2(86) 
  input port2(87) 
  input port2(88) 
  input port2(89) 
  input port2(90) 
  input port2(91) 
  input port2(92) 
  input port2(93) 
  input port2(94) 
  input port2(95) 
  input port2(96) 
  input port2(97) 
  input port2(98) 
  input port2(99) 
  input port2(100) 
  input port2(101) 
  input port2(102) 
  input port2(103) 
  input port2(104) 
  input port2(105) 
  input port2(106) 
  input port2(107) 
  input port2(108) 
  input port2(109) 
  input port2(110) 
  input port2(111) 
  input port2(112) 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output(1)
      input port1(1) (TF) FF
      input port2(1) (FT) FF
expression for output(2)
      input port1(2) (TF) FF
      input port2(2) (FT) FF
expression for output(3)
      input port1(3) (TF) FF
      input port2(3) (FT) FF
expression for output(4)
      input port1(4) (TF) FF
      input port2(4) (FT) FF
expression for output(5)
      input port1(5) (TF) FF
      input port2(5) (FT) FF
expression for output(6)
      input port1(6) (TF) FF
      input port2(6) (FT) FF
expression for output(7)
      input port1(7) (TF) FF
      input port2(7) (FT) FF
expression for output(8)
      input port1(8) (TF) FF
      input port2(8) (FT) FF
expression for output(9)
      input port1(9) (TF) FF
      input port2(9) (FT) FF
expression for output(10)
      input port1(10) (TF) FF
      input port2(10) (FT) FF
expression for output(11)
      input port1(11) (TF) FF
      input port2(11) (FT) FF
expression for output(12)
      input port1(12) (TF) FF
      input port2(12) (FT) FF
expression for output(13)
      input port1(13) (TF) FF
      input port2(13) (FT) FF
expression for output(14)
      input port1(14) (TF) FF
      input port2(14) (FT) FF
expression for output(15)
      input port1(15) (TF) FF
      input port2(15) (FT) FF
expression for output(16)
      input port1(16) (TF) FF
      input port2(16) (FT) FF
expression for output(17)
      input port1(17) (TF) FF
      input port2(17) (FT) FF
expression for output(18)
      input port1(18) (TF) FF
      input port2(18) (FT) FF
expression for output(19)
      input port1(19) (TF) FF
      input port2(19) (FT) FF
expression for output(20)
      input port1(20) (TF) FF
      input port2(20) (FT) FF
expression for output(21)
      input port1(21) (TF) FF
      input port2(21) (FT) FF
expression for output(22)
      input port1(22) (TF) FF
      input port2(22) (FT) FF
expression for output(23)
      input port1(23) (TF) FF
      input port2(23) (FT) FF
expression for output(24)
      input port1(24) (TF) FF
      input port2(24) (FT) FF
expression for output(25)
      input port1(25) (TF) FF
      input port2(25) (FT) FF
expression for output(26)
      input port1(26) (TF) FF
      input port2(26) (FT) FF
expression for output(27)
      input port1(27) (TF) FF
      input port2(27) (FT) FF
expression for output(28)
      input port1(28) (TF) FF
      input port2(28) (FT) FF
expression for output(29)
      input port1(29) (TF) FF
      input port2(29) (FT) FF
expression for output(30)
      input port1(30) (TF) FF
      input port2(30) (FT) FF
expression for output(31)
      input port1(31) (TF) FF
      input port2(31) (FT) FF
expression for output(32)
      input port1(32) (TF) FF
      input port2(32) (FT) FF
expression for output(33)
      input port1(33) (TF) FF
      input port2(33) (FT) FF
expression for output(34)
      input port1(34) (TF) FF
      input port2(34) (FT) FF
expression for output(35)
      input port1(35) (TF) FF
      input port2(35) (FT) FF
expression for output(36)
      input port1(36) (TF) FF
      input port2(36) (FT) FF
expression for output(37)
      input port1(37) (TF) FF
      input port2(37) (FT) FF
expression for output(38)
      input port1(38) (TF) FF
      input port2(38) (FT) FF
expression for output(39)
      input port1(39) (TF) FF
      input port2(39) (FT) FF
expression for output(40)
      input port1(40) (TF) FF
      input port2(40) (FT) FF
expression for output(41)
      input port1(41) (TF) FF
      input port2(41) (FT) FF
expression for output(42)
      input port1(42) (TF) FF
      input port2(42) (FT) FF
expression for output(43)
      input port1(43) (TF) FF
      input port2(43) (FT) FF
expression for output(44)
      input port1(44) (TF) FF
      input port2(44) (FT) FF
expression for output(45)
      input port1(45) (TF) FF
      input port2(45) (FT) FF
expression for output(46)
      input port1(46) (TF) FF
      input port2(46) (FT) FF
expression for output(47)
      input port1(47) (TF) FF
      input port2(47) (FT) FF
expression for output(48)
      input port1(48) (TF) FF
      input port2(48) (FT) FF
expression for output(49)
      input port1(49) (TF) FF
      input port2(49) (FT) FF
expression for output(50)
      input port1(50) (TF) FF
      input port2(50) (FT) FF
expression for output(51)
      input port1(51) (TF) FF
      input port2(51) (FT) FF
expression for output(52)
      input port1(52) (TF) FF
      input port2(52) (FT) FF
expression for output(53)
      input port1(53) (TF) FF
      input port2(53) (FT) FF
expression for output(54)
      input port1(54) (TF) FF
      input port2(54) (FT) FF
expression for output(55)
      input port1(55) (TF) FF
      input port2(55) (FT) FF
expression for output(56)
      input port1(56) (TF) FF
      input port2(56) (FT) FF
expression for output(57)
      input port1(57) (TF) FF
      input port2(57) (FT) FF
expression for output(58)
      input port1(58) (TF) FF
      input port2(58) (FT) FF
expression for output(59)
      input port1(59) (TF) FF
      input port2(59) (FT) FF
expression for output(60)
      input port1(60) (TF) FF
      input port2(60) (FT) FF
expression for output(61)
      input port1(61) (TF) FF
      input port2(61) (FT) FF
expression for output(62)
      input port1(62) (TF) FF
      input port2(62) (FT) FF
expression for output(63)
      input port1(63) (TF) FF
      input port2(63) (FT) FF
expression for output(64)
      input port1(64) (TF) FF
      input port2(64) (FT) FF
expression for output(65)
      input port1(65) (TF) FF
      input port2(65) (FT) FF
expression for output(66)
      input port1(66) (TF) FF
      input port2(66) (FT) FF
expression for output(67)
      input port1(67) (TF) FF
      input port2(67) (FT) FF
expression for output(68)
      input port1(68) (TF) FF
      input port2(68) (FT) FF
expression for output(69)
      input port1(69) (TF) FF
      input port2(69) (FT) FF
expression for output(70)
      input port1(70) (TF) FF
      input port2(70) (FT) FF
expression for output(71)
      input port1(71) (TF) FF
      input port2(71) (FT) FF
expression for output(72)
      input port1(72) (TF) FF
      input port2(72) (FT) FF
expression for output(73)
      input port1(73) (TF) FF
      input port2(73) (FT) FF
expression for output(74)
      input port1(74) (TF) FF
      input port2(74) (FT) FF
expression for output(75)
      input port1(75) (TF) FF
      input port2(75) (FT) FF
expression for output(76)
      input port1(76) (TF) FF
      input port2(76) (FT) FF
expression for output(77)
      input port1(77) (TF) FF
      input port2(77) (FT) FF
expression for output(78)
      input port1(78) (TF) FF
      input port2(78) (FT) FF
expression for output(79)
      input port1(79) (TF) FF
      input port2(79) (FT) FF
expression for output(80)
      input port1(80) (TF) FF
      input port2(80) (FT) FF
expression for output(81)
      input port1(81) (TF) FF
      input port2(81) (FT) FF
expression for output(82)
      input port1(82) (TF) FF
      input port2(82) (FT) FF
expression for output(83)
      input port1(83) (TF) FF
      input port2(83) (FT) FF
expression for output(84)
      input port1(84) (TF) FF
      input port2(84) (FT) FF
expression for output(85)
      input port1(85) (TF) FF
      input port2(85) (FT) FF
expression for output(86)
      input port1(86) (TF) FF
      input port2(86) (FT) FF
expression for output(87)
      input port1(87) (TF) FF
      input port2(87) (FT) FF
expression for output(88)
      input port1(88) (TF) FF
      input port2(88) (FT) FF
expression for output(89)
      input port1(89) (TF) FF
      input port2(89) (FT) FF
expression for output(90)
      input port1(90) (TF) FF
      input port2(90) (FT) FF
expression for output(91)
      input port1(91) (TF) FF
      input port2(91) (FT) FF
expression for output(92)
      input port1(92) (TF) FF
      input port2(92) (FT) FF
expression for output(93)
      input port1(93) (TF) FF
      input port2(93) (FT) FF
expression for output(94)
      input port1(94) (TF) FF
      input port2(94) (FT) FF
expression for output(95)
      input port1(95) (TF) FF
      input port2(95) (FT) FF
expression for output(96)
      input port1(96) (TF) FF
      input port2(96) (FT) FF
expression for output(97)
      input port1(97) (TF) FF
      input port2(97) (FT) FF
expression for output(98)
      input port1(98) (TF) FF
      input port2(98) (FT) FF
expression for output(99)
      input port1(99) (TF) FF
      input port2(99) (FT) FF
expression for output(100)
      input port1(100) (TF) FF
      input port2(100) (FT) FF
expression for output(101)
      input port1(101) (TF) FF
      input port2(101) (FT) FF
expression for output(102)
      input port1(102) (TF) FF
      input port2(102) (FT) FF
expression for output(103)
      input port1(103) (TF) FF
      input port2(103) (FT) FF
expression for output(104)
      input port1(104) (TF) FF
      input port2(104) (FT) FF
expression for output(105)
      input port1(105) (TF) FF
      input port2(105) (FT) FF
expression for output(106)
      input port1(106) (TF) FF
      input port2(106) (FT) FF
expression for output(107)
      input port1(107) (TF) FF
      input port2(107) (FT) FF
expression for output(108)
      input port1(108) (TF) FF
      input port2(108) (FT) FF
expression for output(109)
      input port1(109) (TF) FF
      input port2(109) (FT) FF
expression for output(110)
      input port1(110) (TF) FF
      input port2(110) (FT) FF
expression for output(111)
      input port1(111) (TF) FF
      input port2(111) (FT) FF
expression for output(112)
      input port1(112) (TF) FF
      input port2(112) (FT) FF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellOCVSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 112
Decision 50% (112/224) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(2)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(3)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(4)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(5)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(6)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(7)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(8)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(9)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(10)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(11)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(12)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(13)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(14)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(15)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(16)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(17)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(18)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(19)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(20)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(21)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(22)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(23)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(24)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(25)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(26)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(27)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(28)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(29)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(30)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(31)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(32)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(33)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(34)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(35)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(36)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(37)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(38)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(39)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(40)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(41)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(42)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(43)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(44)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(45)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(46)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(47)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(48)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(49)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(50)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(51)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(52)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(53)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(54)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(55)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(56)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(57)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(58)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(59)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(60)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(61)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(62)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(63)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(64)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(65)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(66)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(67)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(68)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(69)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(70)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(71)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(72)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(73)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(74)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(75)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(76)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(77)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(78)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(79)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(80)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(81)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(82)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(83)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(84)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(85)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(86)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(87)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(88)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(89)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(90)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(91)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(92)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(93)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(94)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(95)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(96)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(97)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(98)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(99)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(100)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(101)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(102)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(103)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(104)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(105)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(106)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(107)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(108)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(109)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(110)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(111)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(112)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Switch block "Switch1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellOCVSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 112
Decision 50% (112/224) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input(1)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(2)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(3)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(4)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(5)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(6)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(7)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(8)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(9)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(10)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(11)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(12)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(13)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(14)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(15)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(16)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(17)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(18)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(19)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(20)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(21)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(22)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(23)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(24)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(25)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(26)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(27)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(28)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(29)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(30)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(31)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(32)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(33)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(34)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(35)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(36)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(37)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(38)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(39)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(40)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(41)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(42)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(43)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(44)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(45)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(46)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(47)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(48)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(49)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(50)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(51)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(52)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(53)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(54)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(55)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(56)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(57)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(58)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(59)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(60)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(61)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(62)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(63)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(64)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(65)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(66)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(67)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(68)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(69)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(70)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(71)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(72)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(73)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(74)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(75)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(76)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(77)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(78)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(79)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(80)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(81)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(82)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(83)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(84)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(85)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(86)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(87)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(88)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(89)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(90)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(91)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(92)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(93)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(94)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(95)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(96)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(97)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(98)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(99)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(100)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(101)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(102)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(103)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(104)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(105)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(106)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(107)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(108)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(109)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(110)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(111)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1
  logical trigger input(112)  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellOCVSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (112/224) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) >= input2(1) 
  input1(2) >= input2(2) 
  input1(3) >= input2(3) 
  input1(4) >= input2(4) 
  input1(5) >= input2(5) 
  input1(6) >= input2(6) 
  input1(7) >= input2(7) 
  input1(8) >= input2(8) 
  input1(9) >= input2(9) 
  input1(10) >= input2(10) 
  input1(11) >= input2(11) 
  input1(12) >= input2(12) 
  input1(13) >= input2(13) 
  input1(14) >= input2(14) 
  input1(15) >= input2(15) 
  input1(16) >= input2(16) 
  input1(17) >= input2(17) 
  input1(18) >= input2(18) 
  input1(19) >= input2(19) 
  input1(20) >= input2(20) 
  input1(21) >= input2(21) 
  input1(22) >= input2(22) 
  input1(23) >= input2(23) 
  input1(24) >= input2(24) 
  input1(25) >= input2(25) 
  input1(26) >= input2(26) 
  input1(27) >= input2(27) 
  input1(28) >= input2(28) 
  input1(29) >= input2(29) 
  input1(30) >= input2(30) 
  input1(31) >= input2(31) 
  input1(32) >= input2(32) 
  input1(33) >= input2(33) 
  input1(34) >= input2(34) 
  input1(35) >= input2(35) 
  input1(36) >= input2(36) 
  input1(37) >= input2(37) 
  input1(38) >= input2(38) 
  input1(39) >= input2(39) 
  input1(40) >= input2(40) 
  input1(41) >= input2(41) 
  input1(42) >= input2(42) 
  input1(43) >= input2(43) 
  input1(44) >= input2(44) 
  input1(45) >= input2(45) 
  input1(46) >= input2(46) 
  input1(47) >= input2(47) 
  input1(48) >= input2(48) 
  input1(49) >= input2(49) 
  input1(50) >= input2(50) 
  input1(51) >= input2(51) 
  input1(52) >= input2(52) 
  input1(53) >= input2(53) 
  input1(54) >= input2(54) 
  input1(55) >= input2(55) 
  input1(56) >= input2(56) 
  input1(57) >= input2(57) 
  input1(58) >= input2(58) 
  input1(59) >= input2(59) 
  input1(60) >= input2(60) 
  input1(61) >= input2(61) 
  input1(62) >= input2(62) 
  input1(63) >= input2(63) 
  input1(64) >= input2(64) 
  input1(65) >= input2(65) 
  input1(66) >= input2(66) 
  input1(67) >= input2(67) 
  input1(68) >= input2(68) 
  input1(69) >= input2(69) 
  input1(70) >= input2(70) 
  input1(71) >= input2(71) 
  input1(72) >= input2(72) 
  input1(73) >= input2(73) 
  input1(74) >= input2(74) 
  input1(75) >= input2(75) 
  input1(76) >= input2(76) 
  input1(77) >= input2(77) 
  input1(78) >= input2(78) 
  input1(79) >= input2(79) 
  input1(80) >= input2(80) 
  input1(81) >= input2(81) 
  input1(82) >= input2(82) 
  input1(83) >= input2(83) 
  input1(84) >= input2(84) 
  input1(85) >= input2(85) 
  input1(86) >= input2(86) 
  input1(87) >= input2(87) 
  input1(88) >= input2(88) 
  input1(89) >= input2(89) 
  input1(90) >= input2(90) 
  input1(91) >= input2(91) 
  input1(92) >= input2(92) 
  input1(93) >= input2(93) 
  input1(94) >= input2(94) 
  input1(95) >= input2(95) 
  input1(96) >= input2(96) 
  input1(97) >= input2(97) 
  input1(98) >= input2(98) 
  input1(99) >= input2(99) 
  input1(100) >= input2(100) 
  input1(101) >= input2(101) 
  input1(102) >= input2(102) 
  input1(103) >= input2(103) 
  input1(104) >= input2(104) 
  input1(105) >= input2(105) 
  input1(106) >= input2(106) 
  input1(107) >= input2(107) 
  input1(108) >= input2(108) 
  input1(109) >= input2(109) 
  input1(110) >= input2(110) 
  input1(111) >= input2(111) 
  input1(112) >= input2(112) 

   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellOCVSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (112/224) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) >= input2(1) 
  input1(2) >= input2(2) 
  input1(3) >= input2(3) 
  input1(4) >= input2(4) 
  input1(5) >= input2(5) 
  input1(6) >= input2(6) 
  input1(7) >= input2(7) 
  input1(8) >= input2(8) 
  input1(9) >= input2(9) 
  input1(10) >= input2(10) 
  input1(11) >= input2(11) 
  input1(12) >= input2(12) 
  input1(13) >= input2(13) 
  input1(14) >= input2(14) 
  input1(15) >= input2(15) 
  input1(16) >= input2(16) 
  input1(17) >= input2(17) 
  input1(18) >= input2(18) 
  input1(19) >= input2(19) 
  input1(20) >= input2(20) 
  input1(21) >= input2(21) 
  input1(22) >= input2(22) 
  input1(23) >= input2(23) 
  input1(24) >= input2(24) 
  input1(25) >= input2(25) 
  input1(26) >= input2(26) 
  input1(27) >= input2(27) 
  input1(28) >= input2(28) 
  input1(29) >= input2(29) 
  input1(30) >= input2(30) 
  input1(31) >= input2(31) 
  input1(32) >= input2(32) 
  input1(33) >= input2(33) 
  input1(34) >= input2(34) 
  input1(35) >= input2(35) 
  input1(36) >= input2(36) 
  input1(37) >= input2(37) 
  input1(38) >= input2(38) 
  input1(39) >= input2(39) 
  input1(40) >= input2(40) 
  input1(41) >= input2(41) 
  input1(42) >= input2(42) 
  input1(43) >= input2(43) 
  input1(44) >= input2(44) 
  input1(45) >= input2(45) 
  input1(46) >= input2(46) 
  input1(47) >= input2(47) 
  input1(48) >= input2(48) 
  input1(49) >= input2(49) 
  input1(50) >= input2(50) 
  input1(51) >= input2(51) 
  input1(52) >= input2(52) 
  input1(53) >= input2(53) 
  input1(54) >= input2(54) 
  input1(55) >= input2(55) 
  input1(56) >= input2(56) 
  input1(57) >= input2(57) 
  input1(58) >= input2(58) 
  input1(59) >= input2(59) 
  input1(60) >= input2(60) 
  input1(61) >= input2(61) 
  input1(62) >= input2(62) 
  input1(63) >= input2(63) 
  input1(64) >= input2(64) 
  input1(65) >= input2(65) 
  input1(66) >= input2(66) 
  input1(67) >= input2(67) 
  input1(68) >= input2(68) 
  input1(69) >= input2(69) 
  input1(70) >= input2(70) 
  input1(71) >= input2(71) 
  input1(72) >= input2(72) 
  input1(73) >= input2(73) 
  input1(74) >= input2(74) 
  input1(75) >= input2(75) 
  input1(76) >= input2(76) 
  input1(77) >= input2(77) 
  input1(78) >= input2(78) 
  input1(79) >= input2(79) 
  input1(80) >= input2(80) 
  input1(81) >= input2(81) 
  input1(82) >= input2(82) 
  input1(83) >= input2(83) 
  input1(84) >= input2(84) 
  input1(85) >= input2(85) 
  input1(86) >= input2(86) 
  input1(87) >= input2(87) 
  input1(88) >= input2(88) 
  input1(89) >= input2(89) 
  input1(90) >= input2(90) 
  input1(91) >= input2(91) 
  input1(92) >= input2(92) 
  input1(93) >= input2(93) 
  input1(94) >= input2(94) 
  input1(95) >= input2(95) 
  input1(96) >= input2(96) 
  input1(97) >= input2(97) 
  input1(98) >= input2(98) 
  input1(99) >= input2(99) 
  input1(100) >= input2(100) 
  input1(101) >= input2(101) 
  input1(102) >= input2(102) 
  input1(103) >= input2(103) 
  input1(104) >= input2(104) 
  input1(105) >= input2(105) 
  input1(106) >= input2(106) 
  input1(107) >= input2(107) 
  input1(108) >= input2(108) 
  input1(109) >= input2(109) 
  input1(110) >= input2(110) 
  input1(111) >= input2(111) 
  input1(112) >= input2(112) 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellOCVSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (112/224) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) <= input2(1) 
  input1(2) <= input2(2) 
  input1(3) <= input2(3) 
  input1(4) <= input2(4) 
  input1(5) <= input2(5) 
  input1(6) <= input2(6) 
  input1(7) <= input2(7) 
  input1(8) <= input2(8) 
  input1(9) <= input2(9) 
  input1(10) <= input2(10) 
  input1(11) <= input2(11) 
  input1(12) <= input2(12) 
  input1(13) <= input2(13) 
  input1(14) <= input2(14) 
  input1(15) <= input2(15) 
  input1(16) <= input2(16) 
  input1(17) <= input2(17) 
  input1(18) <= input2(18) 
  input1(19) <= input2(19) 
  input1(20) <= input2(20) 
  input1(21) <= input2(21) 
  input1(22) <= input2(22) 
  input1(23) <= input2(23) 
  input1(24) <= input2(24) 
  input1(25) <= input2(25) 
  input1(26) <= input2(26) 
  input1(27) <= input2(27) 
  input1(28) <= input2(28) 
  input1(29) <= input2(29) 
  input1(30) <= input2(30) 
  input1(31) <= input2(31) 
  input1(32) <= input2(32) 
  input1(33) <= input2(33) 
  input1(34) <= input2(34) 
  input1(35) <= input2(35) 
  input1(36) <= input2(36) 
  input1(37) <= input2(37) 
  input1(38) <= input2(38) 
  input1(39) <= input2(39) 
  input1(40) <= input2(40) 
  input1(41) <= input2(41) 
  input1(42) <= input2(42) 
  input1(43) <= input2(43) 
  input1(44) <= input2(44) 
  input1(45) <= input2(45) 
  input1(46) <= input2(46) 
  input1(47) <= input2(47) 
  input1(48) <= input2(48) 
  input1(49) <= input2(49) 
  input1(50) <= input2(50) 
  input1(51) <= input2(51) 
  input1(52) <= input2(52) 
  input1(53) <= input2(53) 
  input1(54) <= input2(54) 
  input1(55) <= input2(55) 
  input1(56) <= input2(56) 
  input1(57) <= input2(57) 
  input1(58) <= input2(58) 
  input1(59) <= input2(59) 
  input1(60) <= input2(60) 
  input1(61) <= input2(61) 
  input1(62) <= input2(62) 
  input1(63) <= input2(63) 
  input1(64) <= input2(64) 
  input1(65) <= input2(65) 
  input1(66) <= input2(66) 
  input1(67) <= input2(67) 
  input1(68) <= input2(68) 
  input1(69) <= input2(69) 
  input1(70) <= input2(70) 
  input1(71) <= input2(71) 
  input1(72) <= input2(72) 
  input1(73) <= input2(73) 
  input1(74) <= input2(74) 
  input1(75) <= input2(75) 
  input1(76) <= input2(76) 
  input1(77) <= input2(77) 
  input1(78) <= input2(78) 
  input1(79) <= input2(79) 
  input1(80) <= input2(80) 
  input1(81) <= input2(81) 
  input1(82) <= input2(82) 
  input1(83) <= input2(83) 
  input1(84) <= input2(84) 
  input1(85) <= input2(85) 
  input1(86) <= input2(86) 
  input1(87) <= input2(87) 
  input1(88) <= input2(88) 
  input1(89) <= input2(89) 
  input1(90) <= input2(90) 
  input1(91) <= input2(91) 
  input1(92) <= input2(92) 
  input1(93) <= input2(93) 
  input1(94) <= input2(94) 
  input1(95) <= input2(95) 
  input1(96) <= input2(96) 
  input1(97) <= input2(97) 
  input1(98) <= input2(98) 
  input1(99) <= input2(99) 
  input1(100) <= input2(100) 
  input1(101) <= input2(101) 
  input1(102) <= input2(102) 
  input1(103) <= input2(103) 
  input1(104) <= input2(104) 
  input1(105) <= input2(105) 
  input1(106) <= input2(106) 
  input1(107) <= input2(107) 
  input1(108) <= input2(108) 
  input1(109) <= input2(109) 
  input1(110) <= input2(110) 
  input1(111) <= input2(111) 
  input1(112) <= input2(112) 

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellOCVSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison5"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellOCVSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (112/224) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1(1) <= input2(1) 
  input1(2) <= input2(2) 
  input1(3) <= input2(3) 
  input1(4) <= input2(4) 
  input1(5) <= input2(5) 
  input1(6) <= input2(6) 
  input1(7) <= input2(7) 
  input1(8) <= input2(8) 
  input1(9) <= input2(9) 
  input1(10) <= input2(10) 
  input1(11) <= input2(11) 
  input1(12) <= input2(12) 
  input1(13) <= input2(13) 
  input1(14) <= input2(14) 
  input1(15) <= input2(15) 
  input1(16) <= input2(16) 
  input1(17) <= input2(17) 
  input1(18) <= input2(18) 
  input1(19) <= input2(19) 
  input1(20) <= input2(20) 
  input1(21) <= input2(21) 
  input1(22) <= input2(22) 
  input1(23) <= input2(23) 
  input1(24) <= input2(24) 
  input1(25) <= input2(25) 
  input1(26) <= input2(26) 
  input1(27) <= input2(27) 
  input1(28) <= input2(28) 
  input1(29) <= input2(29) 
  input1(30) <= input2(30) 
  input1(31) <= input2(31) 
  input1(32) <= input2(32) 
  input1(33) <= input2(33) 
  input1(34) <= input2(34) 
  input1(35) <= input2(35) 
  input1(36) <= input2(36) 
  input1(37) <= input2(37) 
  input1(38) <= input2(38) 
  input1(39) <= input2(39) 
  input1(40) <= input2(40) 
  input1(41) <= input2(41) 
  input1(42) <= input2(42) 
  input1(43) <= input2(43) 
  input1(44) <= input2(44) 
  input1(45) <= input2(45) 
  input1(46) <= input2(46) 
  input1(47) <= input2(47) 
  input1(48) <= input2(48) 
  input1(49) <= input2(49) 
  input1(50) <= input2(50) 
  input1(51) <= input2(51) 
  input1(52) <= input2(52) 
  input1(53) <= input2(53) 
  input1(54) <= input2(54) 
  input1(55) <= input2(55) 
  input1(56) <= input2(56) 
  input1(57) <= input2(57) 
  input1(58) <= input2(58) 
  input1(59) <= input2(59) 
  input1(60) <= input2(60) 
  input1(61) <= input2(61) 
  input1(62) <= input2(62) 
  input1(63) <= input2(63) 
  input1(64) <= input2(64) 
  input1(65) <= input2(65) 
  input1(66) <= input2(66) 
  input1(67) <= input2(67) 
  input1(68) <= input2(68) 
  input1(69) <= input2(69) 
  input1(70) <= input2(70) 
  input1(71) <= input2(71) 
  input1(72) <= input2(72) 
  input1(73) <= input2(73) 
  input1(74) <= input2(74) 
  input1(75) <= input2(75) 
  input1(76) <= input2(76) 
  input1(77) <= input2(77) 
  input1(78) <= input2(78) 
  input1(79) <= input2(79) 
  input1(80) <= input2(80) 
  input1(81) <= input2(81) 
  input1(82) <= input2(82) 
  input1(83) <= input2(83) 
  input1(84) <= input2(84) 
  input1(85) <= input2(85) 
  input1(86) <= input2(86) 
  input1(87) <= input2(87) 
  input1(88) <= input2(88) 
  input1(89) <= input2(89) 
  input1(90) <= input2(90) 
  input1(91) <= input2(91) 
  input1(92) <= input2(92) 
  input1(93) <= input2(93) 
  input1(94) <= input2(94) 
  input1(95) <= input2(95) 
  input1(96) <= input2(96) 
  input1(97) <= input2(97) 
  input1(98) <= input2(98) 
  input1(99) <= input2(99) 
  input1(100) <= input2(100) 
  input1(101) <= input2(101) 
  input1(102) <= input2(102) 
  input1(103) <= input2(103) 
  input1(104) <= input2(104) 
  input1(105) <= input2(105) 
  input1(106) <= input2(106) 
  input1(107) <= input2(107) 
  input1(108) <= input2(108) 
  input1(109) <= input2(109) 
  input1(110) <= input2(110) 
  input1(111) <= input2(111) 
  input1(112) <= input2(112) 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellOCVSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant1" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution
Constant block "Constant6" Execution
Constant block "Constant7" Execution
DataStoreWrite block "Data Store Write" Execution

41. SubSystem block "NDP_GaNDP_ReadAllCellOCVSOCVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellOCVSOC

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/AllCellOCVSOC/NDP_GaNDP_ReadAllCellOCVSOCVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

42. SubSystem block "CellAbsvCap"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadCellAbsvCapVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 6
Condition NA 50% (14/28) condition outcomes
Decision NA 50% (5/10) decision outcomes
MCDC NA 0% (0/8) conditions reversed the outcome
Execution NA 100% (24/24) objective outcomes

   Abs block "Abs"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellAbsvCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input < 0  50%
      false 1/1
      true 0/1

   Abs block "Abs1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellAbsvCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input < 0  50%
      false 1/1
      true 0/1

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellAbsvCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Logic block "Logical1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellAbsvCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Logic block "Logical2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellAbsvCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TF) FF
      input port 2 (FT) FF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellAbsvCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Switch block "Switch1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellAbsvCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellAbsvCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellAbsvCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellAbsvCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellAbsvCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison5"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellAbsvCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellAbsvCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant1" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution
Constant block "Constant6" Execution
Constant block "Constant7" Execution
DataStoreWrite block "Data Store Write" Execution

43. SubSystem block "NDP_GbNDP_ReadCellAbsvCapVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellAbsvCap

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellAbsvCap/NDP_GbNDP_ReadCellAbsvCapVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

44. SubSystem block "CellChrgDisCap"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_1D_Config_Word,  NDP_GbNDP_ReadCellChrgDisCapVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 17
Condition NA 50% (14/28) condition outcomes
Decision NA 29% (6/21) decision outcomes
MCDC NA 0% (0/8) conditions reversed the outcome
Execution NA 100% (34/34) objective outcomes

   Abs block "Abs"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input < 0  50%
      false 1/1
      true 0/1

   Abs block "Abs1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  input < 0  50%
      false 1/1
      true 0/1

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Logic block "Logical1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Logic block "Logical2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TF) FF
      input port 2 (FT) FF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Switch block "Switch1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison5"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant1" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution
Constant block "Constant7" Execution
DataStoreWrite block "Data Store Write" Execution

45. SubSystem block "NDP_1D_Config_Word"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap
Child Systems: Switch Case Action Subsystem,  Switch Case Action Subsystem1,  Switch Case Action Subsystem2,  Switch Case Action Subsystem3,  Switch Case Action Subsystem4,  Switch Case Action Subsystem5,  Switch Case Action Subsystem6,  Switch Case Action Subsystem7,  Switch Case Action Subsystem8,  Switch Case Action Subsystem9

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 11
Decision NA 9% (1/11) decision outcomes
Execution NA 100% (12/12) objective outcomes

   SwitchCase block "Switch Case"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap/NDP_1D_Config_Word
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 10
Decision 9% (1/11) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  truncated input  9%
      = Enum_UDSCapSel_Default 1/1
      = Enum_UDSCapSel_CATL153Ah 0/1
      = Enum_UDSCapSel_CATL180Ah 0/1
      = Enum_UDSCapSel_CATL177Ah 0/1
      = Enum_UDSCapSel_CATL203Ah 0/1
      = Enum_UDSCapSel_CATL51Ah 0/1
      = Enum_UDSCapSel_CATL132Ah 0/1
      = Enum_UDSCapSel_XWD75Ah 0/1
      = Enum_UDSCapSel_TFE177Ah 0/1
      = Enum_UDSCapSel_CATLCTP248Ah 0/1
      = implicit-default 0/1

   Full Coverage

Model Object Metric
DataTypeConversion block "Data Type Conversion" Execution

46. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap/NDP_1D_Config_Word

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

47. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap/NDP_1D_Config_Word

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

48. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap/NDP_1D_Config_Word

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

49. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap/NDP_1D_Config_Word

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

50. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap/NDP_1D_Config_Word

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

51. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap/NDP_1D_Config_Word

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

52. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap/NDP_1D_Config_Word

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

53. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap/NDP_1D_Config_Word

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

54. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap/NDP_1D_Config_Word

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

55. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap/NDP_1D_Config_Word

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Execution NA 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
Constant block "Constant0" Execution

56. SubSystem block "NDP_GbNDP_ReadCellChrgDisCapVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/CellChrgDisCap/NDP_GbNDP_ReadCellChrgDisCapVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

57. SubSystem block "DCNegChrgCtlLoadOpenCnt"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadACChrgCtlLoadOpenCntVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCNegChrgCtlLoadOpenCnt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCNegChrgCtlLoadOpenCnt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCNegChrgCtlLoadOpenCnt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCNegChrgCtlLoadOpenCnt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCNegChrgCtlLoadOpenCnt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

58. SubSystem block "NDP_GbNDP_ReadACChrgCtlLoadOpenCntVld_fl..."

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCNegChrgCtlLoadOpenCnt

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCNegChrgCtlLoadOpenCnt/NDP_GbNDP_ReadACChrgCtlLoadOpenCntVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

59. SubSystem block "DCNegChrgCtlLoadOpenCurr"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadACChrgCtlLoadOpenCurrVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCNegChrgCtlLoadOpenCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCNegChrgCtlLoadOpenCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCNegChrgCtlLoadOpenCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCNegChrgCtlLoadOpenCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCNegChrgCtlLoadOpenCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

60. SubSystem block "NDP_GbNDP_ReadACChrgCtlLoadOpenCurrVld_f..."

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCNegChrgCtlLoadOpenCurr

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCNegChrgCtlLoadOpenCurr/NDP_GbNDP_ReadACChrgCtlLoadOpenCurrVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

61. SubSystem block "DCPosChrgCtlLoadOpenCnt"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadDCPosChrgCtlLoadOpenCntVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCPosChrgCtlLoadOpenCnt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCPosChrgCtlLoadOpenCnt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCPosChrgCtlLoadOpenCnt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCPosChrgCtlLoadOpenCnt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCPosChrgCtlLoadOpenCnt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

62. SubSystem block "NDP_GbNDP_ReadDCPosChrgCtlLoadOpenCntVld..."

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCPosChrgCtlLoadOpenCnt

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCPosChrgCtlLoadOpenCnt/NDP_GbNDP_ReadDCPosChrgCtlLoadOpenCntVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

63. SubSystem block "DCPosChrgCtlLoadOpenCurr"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadDCPosChrgCtlLoadOpenCurrVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCPosChrgCtlLoadOpenCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCPosChrgCtlLoadOpenCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCPosChrgCtlLoadOpenCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCPosChrgCtlLoadOpenCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCPosChrgCtlLoadOpenCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

64. SubSystem block "NDP_GbNDP_ReadDCPosChrgCtlLoadOpenCurrVl..."

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCPosChrgCtlLoadOpenCurr

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DCPosChrgCtlLoadOpenCurr/NDP_GbNDP_ReadDCPosChrgCtlLoadOpenCurrVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

65. SubSystem block "DispSOC"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadDispSOCVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 4
Condition NA 50% (14/28) condition outcomes
Decision NA 50% (3/6) decision outcomes
MCDC NA 0% (0/8) conditions reversed the outcome
Execution NA 100% (22/22) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DispSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Logic block "Logical1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DispSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Logic block "Logical2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DispSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TF) FF
      input port 2 (FT) FF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DispSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Switch block "Switch1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DispSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DispSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DispSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DispSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DispSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison5"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DispSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DispSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution
Constant block "Constant6" Execution
Constant block "Constant7" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

66. SubSystem block "NDP_GbNDP_ReadDispSOCVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DispSOC

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/DispSOC/NDP_GbNDP_ReadDispSOCVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

67. SubSystem block "HVIsoValue"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadHVIsoValueVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/HVIsoValue
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/HVIsoValue
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/HVIsoValue
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/HVIsoValue
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/HVIsoValue
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

68. SubSystem block "NDP_GbNDP_ReadHVIsoValueVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/HVIsoValue

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/HVIsoValue/NDP_GbNDP_ReadHVIsoValueVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

69. SubSystem block "MaxCellSOC"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadMaxCellSOCVld_flg1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 4
Condition NA 50% (14/28) condition outcomes
Decision NA 50% (3/6) decision outcomes
MCDC NA 0% (0/8) conditions reversed the outcome
Execution NA 100% (22/22) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Logic block "Logical1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Logic block "Logical2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TF) FF
      input port 2 (FT) FF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Switch block "Switch1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison5"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant1" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution
Constant block "Constant6" Execution
Constant block "Constant7" Execution
DataStoreWrite block "Data Store Write" Execution

70. SubSystem block "NDP_GbNDP_ReadMaxCellSOCVld_flg1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxCellSOC

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxCellSOC/NDP_GbNDP_ReadMaxCellSOCVld_flg1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

71. SubSystem block "MaxCellVolt"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadMaxCellVoltVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxCellVolt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) (TTF)


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxCellVolt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxCellVolt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxCellVolt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxCellVolt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

72. SubSystem block "NDP_GbNDP_ReadMaxCellVoltVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxCellVolt

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxCellVolt/NDP_GbNDP_ReadMaxCellVoltVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

73. SubSystem block "MaxPackCurr"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadMaxPackCurrVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxPackCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxPackCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxPackCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxPackCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxPackCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

74. SubSystem block "NDP_GbNDP_ReadMaxPackCurrVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxPackCurr

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MaxPackCurr/NDP_GbNDP_ReadMaxPackCurrVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

75. SubSystem block "MinCellSOC"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadMinCellSOCVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 4
Condition NA 50% (14/28) condition outcomes
Decision NA 50% (3/6) decision outcomes
MCDC NA 0% (0/8) conditions reversed the outcome
Execution NA 100% (22/22) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MinCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Logic block "Logical1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MinCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Logic block "Logical2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MinCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TF) FF
      input port 2 (FT) FF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MinCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Switch block "Switch1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MinCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MinCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MinCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MinCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison5"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MinCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MinCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison7"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MinCellSOC
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant1" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant5" Execution
Constant block "Constant6" Execution
Constant block "Constant7" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

76. SubSystem block "NDP_GbNDP_ReadMinCellSOCVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MinCellSOC

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MinCellSOC/NDP_GbNDP_ReadMinCellSOCVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

77. SubSystem block "MinCellVolt"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadMinCellVoltVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MinCellVolt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) (TTF)


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MinCellVolt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MinCellVolt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MinCellVolt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MinCellVolt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

78. SubSystem block "NDP_GbNDP_ReadMinCellVoltVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MinCellVolt

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/MinCellVolt/NDP_GbNDP_ReadMinCellVoltVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

79. SubSystem block "NDP_GbNDP_ReadShutdownTimeVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NDP_GbNDP_ReadShutdownTimeVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

80. SubSystem block "NVMOCVCorrdSign"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadNVMOCVCorrdSignVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 4
Condition NA 50% (16/32) condition outcomes
Decision NA 50% (3/6) decision outcomes
MCDC NA 0% (0/8) conditions reversed the outcome
Execution NA 100% (24/24) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSign
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
(C1 || C2) && C3
      C1 (Logical1 In1) (TFT) (FFT)
      C2 (Logical1 In2) (FTT) (FFT)
      C3 (Logical In2) (TFT) TFF


   Logic block "Logical1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSign
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

   Logic block "Logical2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSign
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
(C1 || C2) && C3
      C1 (Logical3 In1) (TFT) (FFT)
      C2 (Logical3 In2) (FTT) (FFT)
      C3 (Logical2 In2) (TFT) TFF


   Logic block "Logical3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSign
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical2
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

   Logic block "Logical4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSign
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TF) FF
      input port 2 (FT) FF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSign
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Switch block "Switch1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSign
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSign
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSign
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSign
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSign
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison5"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSign
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSign
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant1" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution
Constant block "Constant6" Execution
Constant block "Constant7" Execution
DataStoreWrite block "Data Store Write" Execution

81. SubSystem block "NDP_GbNDP_ReadNVMOCVCorrdSignVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSign

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSign/NDP_GbNDP_ReadNVMOCVCorrdSignVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

82. SubSystem block "NVMOCVCorrdSumTi"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadNVMOCVCorrdSumTiVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 4
Condition NA 50% (14/28) condition outcomes
Decision NA 50% (3/6) decision outcomes
MCDC NA 0% (0/8) conditions reversed the outcome
Execution NA 100% (22/22) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSumTi
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Logic block "Logical1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSumTi
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Logic block "Logical2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSumTi
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TF) FF
      input port 2 (FT) FF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSumTi
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Switch block "Switch1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSumTi
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSumTi
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSumTi
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSumTi
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSumTi
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison5"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSumTi
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSumTi
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant1" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution
Constant block "Constant6" Execution
Constant block "Constant7" Execution
DataStoreWrite block "Data Store Write" Execution

83. SubSystem block "NDP_GbNDP_ReadNVMOCVCorrdSumTiVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSumTi

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMOCVCorrdSumTi/NDP_GbNDP_ReadNVMOCVCorrdSumTiVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

84. SubSystem block "NVMPreChrgFail"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadNVMPreChrgFailVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 4
Condition NA 50% (16/32) condition outcomes
Decision NA 50% (3/6) decision outcomes
MCDC NA 0% (0/8) conditions reversed the outcome
Execution NA 100% (24/24) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMPreChrgFail
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
(C1 || C2) && C3
      C1 (Logical1 In1) (TFT) (FFT)
      C2 (Logical1 In2) (FTT) (FFT)
      C3 (Logical In2) (TFT) TFF


   Logic block "Logical1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMPreChrgFail
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

   Logic block "Logical2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMPreChrgFail
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
(C1 || C2) && C3
      C1 (Logical3 In1) (TFT) (FFT)
      C2 (Logical3 In2) (FTT) (FFT)
      C3 (Logical2 In2) (TFT) TFF


   Logic block "Logical3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMPreChrgFail
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical2
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

   Logic block "Logical4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMPreChrgFail
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TF) FF
      input port 2 (FT) FF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMPreChrgFail
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Switch block "Switch1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMPreChrgFail
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMPreChrgFail
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMPreChrgFail
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMPreChrgFail
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMPreChrgFail
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison5"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMPreChrgFail
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMPreChrgFail
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant1" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution
Constant block "Constant6" Execution
Constant block "Constant7" Execution
DataStoreWrite block "Data Store Write" Execution

85. SubSystem block "NDP_GbNDP_ReadNVMPreChrgFailVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMPreChrgFail

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMPreChrgFail/NDP_GbNDP_ReadNVMPreChrgFailVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

86. SubSystem block "NVMVld_State"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 0
Condition NA 50% (18/36) condition outcomes
MCDC NA 0% (0/8) conditions reversed the outcome
Execution NA 100% (25/25) objective outcomes

   Logic block "Logical1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMVld_State
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 TF (FF)
      input port 2 (FT) (FF)


   Logic block "Logical2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMVld_State
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
(C1 || C2) && C3
      C1 (Logical4 In1) (TFT) (FFT)
      C2 (Logical4 In2) (FTT) (FFT)
      C3 (Logical2 In2) (TFT) TFF


   Logic block "Logical3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMVld_State
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
(C1 || C2) && C3
      C1 (Logical5 In1) (TFT) (FFT)
      C2 (Logical5 In2) (FTT) (FFT)
      C3 (Logical3 In2) (TFT) TFF


   Logic block "Logical4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMVld_State
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical2
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

   Logic block "Logical5"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMVld_State
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical3
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMVld_State
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMVld_State
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMVld_State
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMVld_State
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison7"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMVld_State
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison8"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMVld_State
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMVld_State
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 ~= input2 

   RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NVMVld_State
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 ~= input2 

   Full Coverage

Model Object Metric
DataTypeConversion block "Data Type Conversion" Execution
DataTypeConversion block "Data Type Conversion1" Execution
DataTypeConversion block "Data Type Conversion2" Execution
DataTypeConversion block "Data Type Conversion3" Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution
Constant block "Constant8" Execution
Constant block "Constant9" Execution

87. SubSystem block "NegCtlLoadOpenCnt"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadNegCtlLoadOpenCntVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NegCtlLoadOpenCnt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NegCtlLoadOpenCnt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NegCtlLoadOpenCnt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NegCtlLoadOpenCnt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NegCtlLoadOpenCnt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

88. SubSystem block "NDP_GbNDP_ReadNegCtlLoadOpenCntVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NegCtlLoadOpenCnt

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NegCtlLoadOpenCnt/NDP_GbNDP_ReadNegCtlLoadOpenCntVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

89. SubSystem block "NegCtlLoadOpenCurr"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadNegCtlLoadOpenCurrVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NegCtlLoadOpenCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NegCtlLoadOpenCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NegCtlLoadOpenCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NegCtlLoadOpenCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NegCtlLoadOpenCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

90. SubSystem block "NDP_GbNDP_ReadNegCtlLoadOpenCurrVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NegCtlLoadOpenCurr

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/NegCtlLoadOpenCurr/NDP_GbNDP_ReadNegCtlLoadOpenCurrVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

91. SubSystem block "PosCtlLoadOpenCnt"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadPosCtlLoadOpenCntVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/PosCtlLoadOpenCnt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/PosCtlLoadOpenCnt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/PosCtlLoadOpenCnt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/PosCtlLoadOpenCnt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/PosCtlLoadOpenCnt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

92. SubSystem block "NDP_GbNDP_ReadPosCtlLoadOpenCntVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/PosCtlLoadOpenCnt

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/PosCtlLoadOpenCnt/NDP_GbNDP_ReadPosCtlLoadOpenCntVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

93. SubSystem block "PosCtlLoadOpenCurr"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadPosCtlLoadOpenCurrVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/PosCtlLoadOpenCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/PosCtlLoadOpenCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/PosCtlLoadOpenCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/PosCtlLoadOpenCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/PosCtlLoadOpenCurr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

94. SubSystem block "NDP_GbNDP_ReadPosCtlLoadOpenCurrVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/PosCtlLoadOpenCurr

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/PosCtlLoadOpenCurr/NDP_GbNDP_ReadPosCtlLoadOpenCurrVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

95. SubSystem block "SOCCorrdMaxCellVolt"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadSOCCorrdMaxCellVoltVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOCCorrdMaxCellVolt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) (TTF)


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOCCorrdMaxCellVolt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOCCorrdMaxCellVolt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOCCorrdMaxCellVolt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOCCorrdMaxCellVolt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

96. SubSystem block "NDP_GbNDP_ReadSOCCorrdMaxCellVoltVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOCCorrdMaxCellVolt

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOCCorrdMaxCellVolt/NDP_GbNDP_ReadSOCCorrdMaxCellVoltVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

97. SubSystem block "SOCCorrdMinCellVolt"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadSOCCorrdMinCellVoltVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOCCorrdMinCellVolt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) (TTF)


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOCCorrdMinCellVolt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOCCorrdMinCellVolt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOCCorrdMinCellVolt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOCCorrdMinCellVolt
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

98. SubSystem block "NDP_GbNDP_ReadSOCCorrdMinCellVoltVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOCCorrdMinCellVolt

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOCCorrdMinCellVolt/NDP_GbNDP_ReadSOCCorrdMinCellVoltVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

99. SubSystem block "SOH2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadMaxCellSOCVld_flg1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 4
Condition NA 50% (14/28) condition outcomes
Decision NA 50% (3/6) decision outcomes
MCDC NA 0% (0/8) conditions reversed the outcome
Execution NA 100% (22/22) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) (TTF)


   Logic block "Logical1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) (TTF)


   Logic block "Logical2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TF) FF
      input port 2 (FT) FF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Switch block "Switch1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison5"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant1" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution
Constant block "Constant6" Execution
Constant block "Constant7" Execution
DataStoreWrite block "Data Store Write" Execution

100. SubSystem block "NDP_GbNDP_ReadMaxCellSOCVld_flg1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH2

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH2/NDP_GbNDP_ReadMaxCellSOCVld_flg1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

101. SubSystem block "SOH3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadMaxCellSOCVld_flg1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 4
Condition NA 50% (14/28) condition outcomes
Decision NA 50% (3/6) decision outcomes
MCDC NA 0% (0/8) conditions reversed the outcome
Execution NA 100% (22/22) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH3
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) (TTF)


   Logic block "Logical1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH3
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) (TTF)


   Logic block "Logical2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH3
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TF) FF
      input port 2 (FT) FF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH3
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Switch block "Switch1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH3
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH3
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH3
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH3
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH3
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   RelationalOperator block "Comparison5"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH3
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH3
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant1" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution
Constant block "Constant6" Execution
Constant block "Constant7" Execution
DataStoreWrite block "Data Store Write" Execution

102. SubSystem block "NDP_GbNDP_ReadMaxCellSOCVld_flg1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH3

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/SOH3/NDP_GbNDP_ReadMaxCellSOCVld_flg1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

103. SubSystem block "ShutdownTimeDay"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadTotalDischrgPwrVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeDay
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) (TTF)


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeDay
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeDay
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeDay
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeDay
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

104. SubSystem block "NDP_GbNDP_ReadTotalDischrgPwrVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeDay

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeDay/NDP_GbNDP_ReadTotalDischrgPwrVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

105. SubSystem block "ShutdownTimeHr"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadTotalDischrgPwrVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeHr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeHr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeHr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeHr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeHr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

106. SubSystem block "NDP_GbNDP_ReadTotalDischrgPwrVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeHr

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeHr/NDP_GbNDP_ReadTotalDischrgPwrVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

107. SubSystem block "ShutdownTimeMint"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadTotalDischrgPwrVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeMint
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeMint
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeMint
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeMint
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeMint
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

108. SubSystem block "NDP_GbNDP_ReadTotalDischrgPwrVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeMint

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeMint/NDP_GbNDP_ReadTotalDischrgPwrVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

109. SubSystem block "ShutdownTimeMonth"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadTotalDischrgPwrVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeMonth
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) (TTF)


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeMonth
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeMonth
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeMonth
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeMonth
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

110. SubSystem block "NDP_GbNDP_ReadTotalDischrgPwrVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeMonth

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeMonth/NDP_GbNDP_ReadTotalDischrgPwrVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

111. SubSystem block "ShutdownTimeSec"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadTotalDischrgPwrVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeSec
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeSec
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeSec
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeSec
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeSec
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

112. SubSystem block "NDP_GbNDP_ReadTotalDischrgPwrVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeSec

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeSec/NDP_GbNDP_ReadTotalDischrgPwrVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

113. SubSystem block "ShutdownTimeSec1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadTotalDischrgPwrVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeSec1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeSec1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeSec1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeSec1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeSec1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

114. SubSystem block "NDP_GbNDP_ReadTotalDischrgPwrVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeSec1

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeSec1/NDP_GbNDP_ReadTotalDischrgPwrVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

115. SubSystem block "ShutdownTimeYr"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadTotalDischrgPwrVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeYr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) (TTF)


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeYr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeYr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeYr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeYr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

116. SubSystem block "NDP_GbNDP_ReadTotalDischrgPwrVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeYr

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/ShutdownTimeYr/NDP_GbNDP_ReadTotalDischrgPwrVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

117. SubSystem block "TotalChrgCap"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadTotalChrgCapVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalChrgCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalChrgCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalChrgCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalChrgCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalChrgCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

118. SubSystem block "NDP_GbNDP_ReadTotalChrgCapVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalChrgCap

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalChrgCap/NDP_GbNDP_ReadTotalChrgCapVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

119. SubSystem block "TotalChrgPwr"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadTotalChrgPwrVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalChrgPwr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalChrgPwr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalChrgPwr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalChrgPwr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalChrgPwr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

120. SubSystem block "NDP_GbNDP_ReadTotalChrgPwrVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalChrgPwr

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalChrgPwr/NDP_GbNDP_ReadTotalChrgPwrVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

121. SubSystem block "TotalDischrgCap"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadTotalDischrgCapVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalDischrgCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalDischrgCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalDischrgCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalDischrgCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalDischrgCap
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

122. SubSystem block "NDP_GbNDP_ReadTotalDischrgCapVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalDischrgCap

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalDischrgCap/NDP_GbNDP_ReadTotalDischrgCapVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

123. SubSystem block "TotalDischrgPwr"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys
Child Systems: NDP_GbNDP_ReadTotalDischrgPwrVld_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 3
Condition NA 50% (6/12) condition outcomes
Decision NA 50% (2/4) decision outcomes
MCDC NA 0% (0/3) conditions reversed the outcome
Execution NA 100% (13/13) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalDischrgPwr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (3/6) condition outcomes
MCDC 0% (0/3) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
  input port 2 
  input port 3 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TTT) (FTT)
      input port 2 (TTT) (TFT)
      input port 3 (TTT) TTF


   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalDischrgPwr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalDischrgPwr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalDischrgPwr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalDischrgPwr
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 

   Full Coverage

Model Object Metric
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant8" Execution
DataStoreWrite block "Data Store Write" Execution

124. SubSystem block "NDP_GbNDP_ReadTotalDischrgPwrVld_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalDischrgPwr

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/TotalDischrgPwr/NDP_GbNDP_ReadTotalDischrgPwrVld_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

125. SubSystem block "bNDP_NVMDatStrFlt_flgOverWrite"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataRead_Init/NvmDataRead_Init_sys/bNDP_NVMDatStrFlt_flgOverWrite
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1/1
      true (output is from 1st input port) 0/1

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

126. SubSystem block "NvmDataWrite_10ms"

Justify or Exclude
Parent: NDP_UT/NDP
Child Systems: NvmDataWrite_10ms_sys

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 123
Condition NA 50% (27/54) condition outcomes
Decision 100% (1/1) decision outcomes 7% (8/112) decision outcomes
MCDC NA 0% (0/20) conditions reversed the outcome
Execution NA 58% (133/231) objective outcomes

  Decisions analyzed
  Function call  100%
      executed 1001/1001

   Full Coverage

Model Object Metric
SignalConversion block "Signal Conversion" Execution
SignalConversion block "Signal Conversion1" Execution
SignalConversion block "Signal Conversion2" Execution
SignalConversion block "Signal Conversion3" Execution

127. SubSystem block "NvmDataWrite_10ms_sys"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms
Child Systems: NDP_GbNDP_ShutDowmNvmChange_flg,  RunNvmDataWrite_10ms,  RunNvmDataWrite_flg,  ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 122
Condition NA 50% (27/54) condition outcomes
Decision NA 6% (7/111) decision outcomes
MCDC NA 0% (0/20) conditions reversed the outcome
Execution NA 57% (129/227) objective outcomes

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 
1001 

   Full Coverage

Model Object Metric
DataTypeConversion block "Data Type Conversion" Execution
Constant block "Constant1" Execution

128. SubSystem block "NDP_GbNDP_ShutDowmNvmChange_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/NDP_GbNDP_ShutDowmNvmChange_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1001/1001
      true (output is from 1st input port) 0/1001

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

129. SubSystem block "RunNvmDataWrite_10ms"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys
Child Systems: NDP_GaNDP_RunAllCellCap_Ah,  NDP_GaNDP_RunAllCellOCVSOC_pct,  NDP_GcNDP_RunCellAbsvCap_Ah,  NDP_GcNDP_RunCellAbsvCap_Ah1,  NDP_GcNDP_RunCellAbsvCap_Ah2,  NDP_GcNDP_RunCellChrgDisCap_Ah,  NDP_GcNDP_RunDispSOC_pct,  NDP_GcNDP_RunMaxCellSOC_pct,  NDP_GcNDP_RunMinCellSOC_pct,  NDP_GcNDP_RunNVMOCVCorrdSign_numb,  NDP_GcNDP_RunNVMOCVCorrdSumTi_ms,  NDP_GcNDP_RunNVMPreChrgFail_numb
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 2 26
Decision 50% (1/2) decision outcomes 4% (1/26) decision outcomes
Execution NA 50% (24/48) objective outcomes

  Decisions analyzed
  enable logical value  50%
      false 1001/1001
      true 0/1001

   DataStoreRead block "Data Store Read"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read10"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read21"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read22"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read23"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read24"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read25"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read36"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

130. SubSystem block "NDP_GaNDP_RunAllCellCap_Ah"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms/NDP_GaNDP_RunAllCellCap_Ah
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

131. SubSystem block "NDP_GaNDP_RunAllCellOCVSOC_pct"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms/NDP_GaNDP_RunAllCellOCVSOC_pct
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

132. SubSystem block "NDP_GcNDP_RunCellAbsvCap_Ah"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms/NDP_GcNDP_RunCellAbsvCap_Ah
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

133. SubSystem block "NDP_GcNDP_RunCellAbsvCap_Ah1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms/NDP_GcNDP_RunCellAbsvCap_Ah1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

134. SubSystem block "NDP_GcNDP_RunCellAbsvCap_Ah2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms/NDP_GcNDP_RunCellAbsvCap_Ah2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

135. SubSystem block "NDP_GcNDP_RunCellChrgDisCap_Ah"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms/NDP_GcNDP_RunCellChrgDisCap_Ah
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

136. SubSystem block "NDP_GcNDP_RunDispSOC_pct"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms/NDP_GcNDP_RunDispSOC_pct
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

137. SubSystem block "NDP_GcNDP_RunMaxCellSOC_pct"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms/NDP_GcNDP_RunMaxCellSOC_pct
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

138. SubSystem block "NDP_GcNDP_RunMinCellSOC_pct"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms/NDP_GcNDP_RunMinCellSOC_pct
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

139. SubSystem block "NDP_GcNDP_RunNVMOCVCorrdSign_numb"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms/NDP_GcNDP_RunNVMOCVCorrdSign_numb
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

140. SubSystem block "NDP_GcNDP_RunNVMOCVCorrdSumTi_ms"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms/NDP_GcNDP_RunNVMOCVCorrdSumTi_ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

141. SubSystem block "NDP_GcNDP_RunNVMPreChrgFail_numb"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_10ms/NDP_GcNDP_RunNVMPreChrgFail_numb
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

142. SubSystem block "RunNvmDataWrite_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys
Child Systems: EdgeRising2,  EdgeRising3,  EdgeRising4,  NDP_GbNDP_RunNvmChange_flg,  RunNVMStore

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 18
Condition NA 50% (26/52) condition outcomes
Decision NA 57% (4/7) decision outcomes
MCDC NA 0% (0/20) conditions reversed the outcome
Execution NA 100% (25/25) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  1001 
  input port 2 
1001 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
~C1 && C2
      C1 (OR1 In1) (FT) (TT)
      C2 (AND In2) (FT) FF


   Logic block "Logical1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1001 
  input port 2 
1001 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TF) FF
      input port 2 (FT) FF


   Logic block "OR1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see AND
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1001 

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 
1001 

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 
1001 

   Full Coverage

Model Object Metric
DataTypeConversion block "Data Type Conversion" Execution
DataTypeConversion block "Data Type Conversion1" Execution
Constant block "Constant1" Execution
Constant block "Constant2" Execution
DataStoreRead block "Data Store Read" Execution
DataStoreRead block "Data Store Read1" Execution
DataStoreRead block "Data Store Read3" Execution
UnitDelay block "Unit Delay" Execution

143. SubSystem block "EdgeRising2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 1
Condition NA 50% (3/6) condition outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 100% (3/3) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg/EdgeRising2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1001 
  input port 2  1001 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
C1 && ~C2
      C1 (AND In1) (TF) FF
      C2 (OR1 In1) (TF) (TT)


   Logic block "OR1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg/EdgeRising2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see AND
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1001 

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

144. SubSystem block "EdgeRising3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 1
Condition NA 50% (3/6) condition outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 100% (3/3) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg/EdgeRising3
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1001 
  input port 2  1001 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
C1 && ~C2
      C1 (AND In1) (TF) FF
      C2 (OR1 In1) (TF) (TT)


   Logic block "OR1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg/EdgeRising3
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see AND
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1001 

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

145. SubSystem block "EdgeRising4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 1
Condition NA 50% (3/6) condition outcomes
MCDC NA 0% (0/2) conditions reversed the outcome
Execution NA 100% (3/3) objective outcomes

   Logic block "AND"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg/EdgeRising4
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1001 
  input port 2  1001 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
C1 && ~C2
      C1 (AND In1) (TF) FF
      C2 (OR1 In1) (TF) (TT)


   Logic block "OR1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg/EdgeRising4
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
MCDC see AND
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
1001 

   Full Coverage

Model Object Metric
UnitDelay block "Unit Delay" Execution

146. SubSystem block "NDP_GbNDP_RunNvmChange_flg"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg/NDP_GbNDP_RunNvmChange_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 1001/1001
      true (output is from 1st input port) 0/1001

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

147. SubSystem block "RunNVMStore"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg
Child Systems: NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg/RunNVMStore

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 13
Condition NA 50% (10/20) condition outcomes
Decision NA 60% (3/5) decision outcomes
MCDC NA 0% (0/10) conditions reversed the outcome

148. Chart "NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_..."

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg/RunNVMStore
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 2 12
Condition NA 50% (10/20) condition outcomes
Decision 67% (2/3) decision outcomes 60% (3/5) decision outcomes
MCDC NA 0% (0/10) conditions reversed the outcome

  Decisions analyzed
  Substate executed  67%
      State "InitValueUpdate" 1/1000
      State "RunNVMFlag" 0/1000
      State "TimeSum" 999/1000

   Transition "[LcNDP_RunMaxCellSOC_pct - EcNVM_MaxCell..." from "TimeSum" to "RunNVMFlag"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/RunNvmDataWrite_flg/RunNVMStore
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 10
Condition 50% (10/20) condition outcomes
Decision 50% (1/2) decision outcomes
MCDC 0% (0/10) conditions reversed the outcome

  Decisions analyzed
  Transition trigger expression  50%
      false 999/999
      true 0/999

  Conditions analyzed
Description True False
  Condition 1, "LcNDP_RunMaxCellSOC_pct - EcNVM_MaxCellSOC_pct>=CcNDP_DeltaRunMaxSOC_pct" 
999 
  Condition 2, "EcNVM_MaxCellSOC_pct - LcNDP_RunMaxCellSOC_pct>=CcNDP_DeltaRunMaxSOC_pct" 
999 
  Condition 3, "LcNDP_RunMinCellSOC_pct - EcNVM_MinCellSOC_pct>=CcNDP_DeltaRunMinSOC_pct" 
999 
  Condition 4, "EcNVM_MinCellSOC_pct - LcNDP_RunMinCellSOC_pct>=CcNDP_DeltaRunMinSOC_pct" 
999 
  Condition 5, "LcNDP_RunDispSOC_pct - EcNVM_DispSOC_pct>=CcNDP_DeltaRunDispSOC_pct" 
999 
  Condition 6, "EcNVM_DispSOC_pct - LcNDP_RunDispSOC_pct>=CcNDP_DeltaRunDispSOC_pct" 
999 
  Condition 7, "LcNDP_RunDataSumTi_ms>=CcNDP_RunDataSumTi_ms" 
999 
  Condition 8, "LbNDP_ChrgFinish_flg" 
999 
  Condition 9, "LbNDP_ShutDown_flg" 
999 
  Condition 10, "LbNDP_HVPowerDown_flg" 
999 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
Transition trigger expression
      Condition 1, "LcNDP_RunMaxCellSOC_pct - EcNVM_MaxCellSOC_pct>=CcNDP_DeltaRunMaxSOC_pct" (Txxxxxxxxx) FFFFFFFFFF
      Condition 2, "EcNVM_MaxCellSOC_pct - LcNDP_RunMaxCellSOC_pct>=CcNDP_DeltaRunMaxSOC_pct" (FTxxxxxxxx) FFFFFFFFFF
      Condition 3, "LcNDP_RunMinCellSOC_pct - EcNVM_MinCellSOC_pct>=CcNDP_DeltaRunMinSOC_pct" (FFTxxxxxxx) FFFFFFFFFF
      Condition 4, "EcNVM_MinCellSOC_pct - LcNDP_RunMinCellSOC_pct>=CcNDP_DeltaRunMinSOC_pct" (FFFTxxxxxx) FFFFFFFFFF
      Condition 5, "LcNDP_RunDispSOC_pct - EcNVM_DispSOC_pct>=CcNDP_DeltaRunDispSOC_pct" (FFFFTxxxxx) FFFFFFFFFF
      Condition 6, "EcNVM_DispSOC_pct - LcNDP_RunDispSOC_pct>=CcNDP_DeltaRunDispSOC_pct" (FFFFFTxxxx) FFFFFFFFFF
      Condition 7, "LcNDP_RunDataSumTi_ms>=CcNDP_RunDataSumTi_ms" (FFFFFFTxxx) FFFFFFFFFF
      Condition 8, "LbNDP_ChrgFinish_flg" (FFFFFFFTxx) FFFFFFFFFF
      Condition 9, "LbNDP_ShutDown_flg" (FFFFFFFFTx) FFFFFFFFFF
      Condition 10, "LbNDP_HVPowerDown_flg" (FFFFFFFFFT) FFFFFFFFFF


149. SubSystem block "ShutDownNvmDataWrite_10ms"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys
Child Systems: NDP_GaNDP_ShutDownAllCellCap_Ah,  NDP_GaNDP_ShutDownAllCellOCVSOC_pct,  NDP_GcNDP_RunCellAbsvCap_Ah1,  NDP_GcNDP_RunCellAbsvCap_Ah2,  NDP_GcNDP_RunCellAbsvCap_Ah3,  NDP_GcNDP_RunCellAbsvCap_Ah4,  NDP_GcNDP_RunCellAbsvCap_Ah5,  NDP_GcNDP_RunCellAbsvCap_Ah6,  NDP_GcNDP_RunCellAbsvCap_Ah7,  NDP_GcNDP_RunCellAbsvCap_Ah8,  NDP_GcNDP_RunCellAbsvCap_Ah9,  NDP_GcNDP_ShutDownCellAbsvCap_Ah,  NDP_GcNDP_ShutDownCellChrgDisCap_Ah,  NDP_GcNDP_ShutDownDCNegChrgCtlLoadOpenCnt_numb,  NDP_GcNDP_ShutDownDCNegChrgCtlLoadOpenCurr_A,  NDP_GcNDP_ShutDownDCPosChrgCtlLoadOpenCnt_numb,  NDP_GcNDP_ShutDownDCPosChrgCtlLoadOpenCurr_A,  NDP_GcNDP_ShutDownDispSOC_pct,  NDP_GcNDP_ShutDownHVIsoValue_kohm,  NDP_GcNDP_ShutDownMaxCellSOC_pct,  NDP_GcNDP_ShutDownMaxCellVolt_mV,  NDP_GcNDP_ShutDownMaxPackCurr_A,  NDP_GcNDP_ShutDownMinCellSOC_pct,  NDP_GcNDP_ShutDownMinCellVolt_mV,  NDP_GcNDP_ShutDownNVMOCVCorrdSign_numb,  NDP_GcNDP_ShutDownNVMOCVCorrdSumTi_ms,  NDP_GcNDP_ShutDownNVMPreChrgFail_numb,  NDP_GcNDP_ShutDownNegCtlLoadOpenCnt_numb,  NDP_GcNDP_ShutDownNegCtlLoadOpenCurr_A,  NDP_GcNDP_ShutDownPosCtlLoadOpenCnt_numb,  NDP_GcNDP_ShutDownPosCtlLoadOpenCurr_A,  NDP_GcNDP_ShutDownSOCCorrdMaxCellVolt_mV,  NDP_GcNDP_ShutDownSOCCorrdMinCellVolt_mV,  NDP_GcNDP_ShutDownTotalChrgCap_Ah,  NDP_GcNDP_ShutDownTotalChrgPwr_kWh,  NDP_GcNDP_ShutDownTotalDischrgCap_Ah,  NDP_GcNDP_ShutDownTotalDischrgPwr_kWh
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 2 76
Decision 50% (1/2) decision outcomes 1% (1/76) decision outcomes
Execution NA 50% (74/148) objective outcomes

  Decisions analyzed
  enable logical value  50%
      false 1001/1001
      true 0/1001

   DataStoreRead block "Data Store Read"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read10"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read11"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read12"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read13"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read14"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read15"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read16"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read17"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read18"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read19"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read20"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read21"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read22"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read23"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read24"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read25"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read26"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read27"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read28"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read29"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read30"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read31"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read32"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read33"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read34"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read35"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read36"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read5"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read7"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read8"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

   DataStoreRead block "Data Store Read9"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Execution 0% (0/1) objective outcomes

150. SubSystem block "NDP_GaNDP_ShutDownAllCellCap_Ah"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GaNDP_ShutDownAllCellCap_Ah
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

151. SubSystem block "NDP_GaNDP_ShutDownAllCellOCVSOC_pct"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GaNDP_ShutDownAllCellOCVSOC_pct
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

152. SubSystem block "NDP_GcNDP_RunCellAbsvCap_Ah1"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_RunCellAbsvCap_Ah1
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

153. SubSystem block "NDP_GcNDP_RunCellAbsvCap_Ah2"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_RunCellAbsvCap_Ah2
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

154. SubSystem block "NDP_GcNDP_RunCellAbsvCap_Ah3"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_RunCellAbsvCap_Ah3
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

155. SubSystem block "NDP_GcNDP_RunCellAbsvCap_Ah4"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_RunCellAbsvCap_Ah4
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

156. SubSystem block "NDP_GcNDP_RunCellAbsvCap_Ah5"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_RunCellAbsvCap_Ah5
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

157. SubSystem block "NDP_GcNDP_RunCellAbsvCap_Ah6"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_RunCellAbsvCap_Ah6
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

158. SubSystem block "NDP_GcNDP_RunCellAbsvCap_Ah7"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_RunCellAbsvCap_Ah7
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

159. SubSystem block "NDP_GcNDP_RunCellAbsvCap_Ah8"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_RunCellAbsvCap_Ah8
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

160. SubSystem block "NDP_GcNDP_RunCellAbsvCap_Ah9"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_RunCellAbsvCap_Ah9
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

161. SubSystem block "NDP_GcNDP_ShutDownCellAbsvCap_Ah"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownCellAbsvCap_Ah
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

162. SubSystem block "NDP_GcNDP_ShutDownCellChrgDisCap_Ah"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownCellChrgDisCap_Ah
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

163. SubSystem block "NDP_GcNDP_ShutDownDCNegChrgCtlLoadOpenCn..."

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownDCNegChrgCtlLoadOpenCnt_numb
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

164. SubSystem block "NDP_GcNDP_ShutDownDCNegChrgCtlLoadOpenCu..."

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownDCNegChrgCtlLoadOpenCurr_A
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

165. SubSystem block "NDP_GcNDP_ShutDownDCPosChrgCtlLoadOpenCn..."

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownDCPosChrgCtlLoadOpenCnt_numb
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

166. SubSystem block "NDP_GcNDP_ShutDownDCPosChrgCtlLoadOpenCu..."

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownDCPosChrgCtlLoadOpenCurr_A
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

167. SubSystem block "NDP_GcNDP_ShutDownDispSOC_pct"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownDispSOC_pct
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

168. SubSystem block "NDP_GcNDP_ShutDownHVIsoValue_kohm"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownHVIsoValue_kohm
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

169. SubSystem block "NDP_GcNDP_ShutDownMaxCellSOC_pct"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownMaxCellSOC_pct
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

170. SubSystem block "NDP_GcNDP_ShutDownMaxCellVolt_mV"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownMaxCellVolt_mV
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

171. SubSystem block "NDP_GcNDP_ShutDownMaxPackCurr_A"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownMaxPackCurr_A
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

172. SubSystem block "NDP_GcNDP_ShutDownMinCellSOC_pct"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownMinCellSOC_pct
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

173. SubSystem block "NDP_GcNDP_ShutDownMinCellVolt_mV"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownMinCellVolt_mV
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

174. SubSystem block "NDP_GcNDP_ShutDownNVMOCVCorrdSign_numb"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownNVMOCVCorrdSign_numb
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

175. SubSystem block "NDP_GcNDP_ShutDownNVMOCVCorrdSumTi_ms"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownNVMOCVCorrdSumTi_ms
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

176. SubSystem block "NDP_GcNDP_ShutDownNVMPreChrgFail_numb"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownNVMPreChrgFail_numb
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

177. SubSystem block "NDP_GcNDP_ShutDownNegCtlLoadOpenCnt_numb"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownNegCtlLoadOpenCnt_numb
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

178. SubSystem block "NDP_GcNDP_ShutDownNegCtlLoadOpenCurr_A"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownNegCtlLoadOpenCurr_A
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

179. SubSystem block "NDP_GcNDP_ShutDownPosCtlLoadOpenCnt_numb"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownPosCtlLoadOpenCnt_numb
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

180. SubSystem block "NDP_GcNDP_ShutDownPosCtlLoadOpenCurr_A"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownPosCtlLoadOpenCurr_A
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

181. SubSystem block "NDP_GcNDP_ShutDownSOCCorrdMaxCellVolt_mV"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownSOCCorrdMaxCellVolt_mV
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

182. SubSystem block "NDP_GcNDP_ShutDownSOCCorrdMinCellVolt_mV"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownSOCCorrdMinCellVolt_mV
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

183. SubSystem block "NDP_GcNDP_ShutDownTotalChrgCap_Ah"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownTotalChrgCap_Ah
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

184. SubSystem block "NDP_GcNDP_ShutDownTotalChrgPwr_kWh"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownTotalChrgPwr_kWh
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

185. SubSystem block "NDP_GcNDP_ShutDownTotalDischrgCap_Ah"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownTotalDischrgCap_Ah
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

186. SubSystem block "NDP_GcNDP_ShutDownTotalDischrgPwr_kWh"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 0% (0/2) decision outcomes
Execution NA 67% (2/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: NDP_UT/NDP/NvmDataWrite_10ms/NvmDataWrite_10ms_sys/ShutDownNvmDataWrite_10ms/NDP_GcNDP_ShutDownTotalDischrgPwr_kWh
Uncovered Links:  Previous uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 0% (0/2) decision outcomes
Execution 0% (0/1) objective outcomes

  Decisions analyzed
  logical trigger input  0%
      false (output is from 3rd input port) --
      true (output is from 1st input port) --

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution