Coverage Report for HVL_UT

Table of Contents

  1. Analysis Information
  2. Tests
  3. Summary
  4. Details

Analysis Information

Model Information

  Model version   'M100C100'
  Author   xigkd
  Last saved   Thu Apr 08 15:45:56 2021

Harness information

  Harness model(s)   UT_HVL_0001
  Harness model owner   HVL_UT

Simulation Optimization Options

  Default parameter behavior   inlined
  Block reduction   forced off
  Conditional branch optimization   on

Coverage Options

  Analyzed model   HVL_UT
  Logic block short circuiting   off
  MCDC mode   masking

Tests

Test# Started execution Ended execution
Test 1 12-Apr-2021 13:45:04 12-Apr-2021 13:45:05

Summary

Model Hierarchy/Complexity Test 1  
Decision Condition MCDC Execution  
1. HVL_UT 23 65%
   
59%
   
0%
   
100%
   
 
2. . . . HVIL_20ms_sys 18 65%
   
59%
   
0%
   
100%
   
 
3. . . . . . . HVLSelfCheck_Enable 6 88%
   
90%
   
0%
   
100%
   
 
4. . . . . . . . . . BMSDelay 4 83%
   
75%
   
NA 100%
   
 
5. . . . . . . . . . . . . Unit Delay Resettable 2 75%
   
NA NA 100%
   
 
6. . . . . . . HVL_GbHVL_HvilLFlt_flg 2 50%
   
NA NA 100%
   
 
7. . . . . . . HVL_GbHVL_HvilSTG_flg 2 50%
   
NA NA 100%
   
 
8. . . . . . . HVL_GbHVL_HvilSTV_flg 2 50%
   
NA NA 100%
   
 
9. . . . . . . HVL_GbHVL_HvilSelfCheck_flg 2 50%
   
NA NA 100%
   
 
10. . . . . . . HVL_GcHVL_HvilDutySet_pct 2 50%
   
NA NA 100%
   
 
11. . . . . . . HVL_GcHVL_HvilPerSet_us 2 50%
   
NA NA 100%
   
 

Details

1. Model "HVL_UT"

Child Systems: HVIL_20ms_sys

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 23
Condition NA 59% (60/102) condition outcomes
Decision NA 65% (13/20) decision outcomes
MCDC NA 0% (0/20) conditions reversed the outcome
Execution NA 100% (87/87) objective outcomes

2. SubSystem block "HVIL_20ms_sys"

Justify or Exclude
Parent: /HVL_UT
Child Systems: HVLSelfCheck_Enable,  HVL_GbHVL_HvilLFlt_flg,  HVL_GbHVL_HvilSTG_flg,  HVL_GbHVL_HvilSTV_flg,  HVL_GbHVL_HvilSelfCheck_flg,  HVL_GcHVL_HvilDutySet_pct,  HVL_GcHVL_HvilPerSet_us

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 18
Condition NA 59% (60/102) condition outcomes
Decision NA 65% (13/20) decision outcomes
MCDC NA 0% (0/20) conditions reversed the outcome
Execution NA 100% (87/87) objective outcomes

   Logic block "Logical"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/4) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
801 
  input port 2 
801 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 3 blocks
Decision/Condition True Out False Out
(C1 && C2) && (C3 && C4)
      C1 (Logical5 In1) (TTTT) (FTTT)
      C2 (Logical5 In2) (TTTT) (TFTT)
      C3 (Logical6 In1) (TTTT) (TTFT)
      C4 (Logical6 In2) (TTTT) (TTTF)


   Logic block "Logical1"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical8
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
801 
  input port 2 
801 

   Logic block "Logical10"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical2
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  801 
  input port 2  801 

   Logic block "Logical11"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical2
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
801 
  input port 2 
801 

   Logic block "Logical12"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical2
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
801 
  input port 2 
801 

   Logic block "Logical2"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/6) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  801 
  input port 2 
801 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 5 blocks
Decision/Condition True Out False Out
((C1 && C2) && C3) && ((C4 || C5) && C6)
      C1 (Logical9 In1) (TTTTTT) (FTTTTT)
      C2 (Logical9 In2) (TTTTTT) (TFTTTT)
      C3 (Logical10 In2) (TTTTTT) (TTFTTT)
      C4 (Logical12 In1) (TTTTFT) (TTTFFT)
      C5 (Logical12 In2) (TTTFTT) (TTTFFT)
      C6 (Logical11 In2) (TTTTTT) (TTTTTF)


   Logic block "Logical4"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/2) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
801 
  input port 2 
801 

  MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition True Out False Out
expression for output
      input port 1 (TF) FF
      input port 2 (FT) FF


   Logic block "Logical5"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
801 
  input port 2 
801 

   Logic block "Logical6"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
801 
  input port 2 
801 

   Logic block "Logical7"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical8
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
801 
  input port 2 
801 

   Logic block "Logical8"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC 0% (0/4) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 
801 
  input port 2 
801 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 3 blocks
Decision/Condition True Out False Out
(C1 && C2) && (C3 && C4)
      C1 (Logical1 In1) (TTTT) (FTTT)
      C2 (Logical1 In2) (TTTT) (TFTT)
      C3 (Logical7 In1) (TTTT) (TTFT)
      C4 (Logical7 In2) (TTTT) (TTTF)


   Logic block "Logical9"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (2/4) condition outcomes
MCDC see Logical2
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  801 
  input port 2  801 

   RelationalOperator block "Comparison"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
801 

   RelationalOperator block "Comparison1"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 
801 

   RelationalOperator block "Comparison10"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
801 

   RelationalOperator block "Comparison11"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 < input2 
801 

   RelationalOperator block "Comparison12"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 < input2 
801 

   RelationalOperator block "Comparison13"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 <= input2  801 

   RelationalOperator block "Comparison14"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 >= input2  801 

   RelationalOperator block "Comparison15"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2  801 

   RelationalOperator block "Comparison2"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 
801 

   RelationalOperator block "Comparison3"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 
801 

   RelationalOperator block "Comparison4"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 
801 

   RelationalOperator block "Comparison5"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 < input2 
801 

   RelationalOperator block "Comparison6"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
801 

   RelationalOperator block "Comparison7"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 < input2 
801 

   RelationalOperator block "Comparison8"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 > input2 
801 

   RelationalOperator block "Comparison9"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input1 == input2 
801 

   Full Coverage

Model Object Metric
DataTypeConversion block "Data Type Conversion1" Execution
DataTypeConversion block "Data Type Conversion2" Execution
RelationalOperator block "Relational Operator" Condition, Execution
S-Function block "Bitwise Logical Operator" Execution
Constant block "Constant" Execution
Constant block "Constant1" Execution
Constant block "Constant10" Execution
Constant block "Constant11" Execution
Constant block "Constant12" Execution
Constant block "Constant13" Execution
Constant block "Constant14" Execution
Constant block "Constant15" Execution
Constant block "Constant16" Execution
Constant block "Constant17" Execution
Constant block "Constant19" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant5" Execution
Constant block "Constant6" Execution
Constant block "Constant7" Execution
Constant block "Constant8" Execution
Constant block "Constant9" Execution

3. SubSystem block "HVLSelfCheck_Enable"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys
Child Systems: BMSDelay

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 2 6
Condition NA 90% (18/20) condition outcomes
Decision 100% (2/2) decision outcomes 88% (7/8) decision outcomes
MCDC NA 0% (0/4) conditions reversed the outcome
Execution NA 100% (18/18) objective outcomes

  Decisions analyzed
  enable logical value  100%
      false 501/801
      true 300/801

   Logic block "Logical Operator"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys/HVLSelfCheck_Enable
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 75% (3/4) condition outcomes
MCDC 0% (0/4) conditions reversed the outcome
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1  285  15 
  input port 2 
300 

  MC/DC analysis (combinations in parentheses did not occur)
  Includes 2 blocks
Decision/Condition True Out False Out
C1 && ((C2 && C3) && C4)
      C1 (Logical Operator In1) (TTTT) (FTTT)
      C2 (Logical3 In1) (TTTT) TFTT
      C3 (Logical3 In2) (TTTT) TTFT
      C4 (Logical3 In3) (TTTT) TTTF


   Logic block "Logical3"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys/HVLSelfCheck_Enable

Metric Coverage
Cyclomatic Complexity 0
Condition 100% (6/6) condition outcomes
MCDC see Logical Operator
Execution 100% (1/1) objective outcomes

   Full Coverage

Model Object Metric
RelationalOperator block "Relational Operator1" Condition, Execution
RelationalOperator block "Relational Operator2" Condition, Execution
RelationalOperator block "Relational Operator5" Condition, Execution
Constant block "Constant1" Execution
Constant block "Constant2" Execution
Constant block "Constant3" Execution
Constant block "Constant4" Execution
Constant block "Constant7" Execution
Constant block "Constant8" Execution

4. SubSystem block "BMSDelay"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys/HVLSelfCheck_Enable
Child Systems: Unit Delay Resettable

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 4
Condition NA 75% (3/4) condition outcomes
Decision NA 83% (5/6) decision outcomes
Execution NA 100% (7/7) objective outcomes

   Logic block "Logical Operator"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys/HVLSelfCheck_Enable/BMSDelay
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 0
Condition 50% (1/2) condition outcomes
Execution 100% (1/1) objective outcomes

  Conditions analyzed
Description True False
  input port 1 

   Full Coverage

Model Object Metric
Switch block "Switch" Decision, Execution
Sum block "Add" Execution
RelationalOperator block "Relational Operator" Condition, Execution
Constant block "Constant" Execution

5. SubSystem block "Unit Delay Resettable"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys/HVLSelfCheck_Enable/BMSDelay

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 0 2
Decision NA 75% (3/4) decision outcomes
Execution NA 100% (2/2) objective outcomes

   Switch block "Reset"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys/HVLSelfCheck_Enable/BMSDelay/Unit Delay Resettable
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 300/300
      true (output is from 1st input port) 0/300

   Full Coverage

Model Object Metric
Switch block "Init" Decision, Execution

6. SubSystem block "HVL_GbHVL_HvilLFlt_flg"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys/HVL_GbHVL_HvilLFlt_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 801/801
      true (output is from 1st input port) 0/801

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

7. SubSystem block "HVL_GbHVL_HvilSTG_flg"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys/HVL_GbHVL_HvilSTG_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 801/801
      true (output is from 1st input port) 0/801

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

8. SubSystem block "HVL_GbHVL_HvilSTV_flg"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys/HVL_GbHVL_HvilSTV_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 801/801
      true (output is from 1st input port) 0/801

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

9. SubSystem block "HVL_GbHVL_HvilSelfCheck_flg"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys/HVL_GbHVL_HvilSelfCheck_flg
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 801/801
      true (output is from 1st input port) 0/801

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

10. SubSystem block "HVL_GcHVL_HvilDutySet_pct"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys/HVL_GcHVL_HvilDutySet_pct
Uncovered Links:  Previous uncovered object Next uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 2/2
      true (output is from 1st input port) 0/2

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution

11. SubSystem block "HVL_GcHVL_HvilPerSet_us"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys

Metric Coverage (this object) Coverage (inc. descendants)
Cyclomatic Complexity 1 2
Decision NA 50% (1/2) decision outcomes
Execution NA 100% (3/3) objective outcomes

   Switch block "Switch"

Justify or Exclude
Parent: HVL_UT/HVIL_20ms_sys/HVL_GcHVL_HvilPerSet_us
Uncovered Links:  Previous uncovered object

Metric Coverage
Cyclomatic Complexity 1
Decision 50% (1/2) decision outcomes
Execution 100% (1/1) objective outcomes

  Decisions analyzed
  logical trigger input  50%
      false (output is from 3rd input port) 2/2
      true (output is from 1st input port) 0/2

   Full Coverage

Model Object Metric
Constant block "Constant" Execution
Constant block "Constant1" Execution