| Model version | 'M101C100' |
| Author | xigkd |
| Last saved | Fri Apr 09 14:28:53 2021 |
| Harness model(s) | Copy_of_FSD_Harness2 |
| Harness model owner | Copy_of_FSD |
| Default parameter behavior | inlined |
| Block reduction | forced off |
| Conditional branch optimization | on |
| Analyzed model | Copy_of_FSD |
| Logic block short circuiting | off |
| MCDC mode | masking |
| Test# | Started execution | Ended execution |
| Test 1 | 09-Apr-2021 14:32:48 | 09-Apr-2021 14:32:48 |
| Model Hierarchy/Complexity | Test 1 | |||||||||||||||||||||||||
| Decision | Condition | MCDC | Execution | |||||||||||||||||||||||
| 1. Copy_of_FSD | 14 | 64% |
|
50% |
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0% |
|
100% |
|
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| 2. . . . Chart | 2 | 100% |
|
NA | NA | NA | ||||||||||||||||||||
| 3. . . . . . . SF: Chart | 1 | 100% |
|
NA | NA | NA | ||||||||||||||||||||
| 4. . . . . . . . . . SF: OS | 1 | 100% |
|
NA | NA | NA | ||||||||||||||||||||
| 5. . . . FSD | 7 | 56% |
|
50% |
|
0% |
|
100% |
|
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| 6. . . . . . . FuseDiag_100ms | 7 | 56% |
|
50% |
|
0% |
|
100% |
|
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| 7. . . . . . . . . . FuseDiag_100ms_sys | 6 | 50% |
|
50% |
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0% |
|
100% |
|
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| 8. . . . . . . . . . . . . BMSDelay | 4 | 50% |
|
50% |
|
NA | 100% |
|
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| 9. . . . . . . . . . . . . . . . Unit Delay Resettable | 2 | 50% |
|
NA | NA | 100% |
|
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| 10. . . . . . . . . . . . . FSD_GbFSD_MSDOpenFlt_flg | 2 | 50% |
|
NA | NA | 100% |
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Decisions analyzed
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Conditions analyzed
MC/DC analysis (combinations in parentheses did not occur)
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