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| Model Advisor Report - SOP.slx | |
| Simulink version: 9.0 | Model version: 'M110C115R104' |
| System: SOP | Current run: 2021/04/10 20:16:48 |
| Model Advisor configuration: ...Model_Guidelines_Check.mat | |
| Treat as Referenced Model: off | |
| Pass | Fail | Warning | Not Run | Total |
|---|---|---|---|---|
|
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|
|
66 |
Identify file names with incorrect characters or formatting.
Passed
All files have correct names.
Identify folders using incorrect characters and formatting.
Passed
All folder names have correct formatting.
Identify subsystem names that use characters that are not correct in C code.
Warning
The following subsystem names contain incorrect characters:
| Error | Subsystem block |
|---|---|
| Name contains incorrect characters. | ..../PeakPwrCacl/ChrgContPwr/3D_Config_Word |
| Name contains incorrect characters. | ..../PeakPwrCacl/ChrgContPwr/3D_Config_Word1 |
| Name contains incorrect characters. | ..../PeakPwrCacl/ChrgContPwr/3D_Config_Word2 |
| Name contains incorrect characters. | ..../PeakPwrCacl/ChrgContPwr/3D_Config_Word3 |
| Name contains incorrect characters. | ..../PeakPwrCacl/ChrgPeakPwr/3D_Config_Word |
| Name contains incorrect characters. | ..../PeakPwrCacl/ChrgPeakPwr/3D_Config_Word1 |
| Name contains incorrect characters. | ..../PeakPwrCacl/ChrgPeakPwr/3D_Config_Word2 |
| Name contains incorrect characters. | ..../PeakPwrCacl/ChrgPeakPwr/3D_Config_Word3 |
| Name contains incorrect characters. | ..../DisChrgContPwr/3D_Config_Word |
| Name contains incorrect characters. | ..../DisChrgContPwr/3D_Config_Word2 |
| Name contains incorrect characters. | ..../DisChrgContPwr/3D_Config_Word3 |
| Name contains incorrect characters. | ..../DisChrgContPwr/3D_Config_Word4 |
| Name contains incorrect characters. | ..../DisChrgPeakPwr/3D_Config_Word |
| Name contains incorrect characters. | ..../DisChrgPeakPwr/3D_Config_Word1 |
| Name contains incorrect characters. | ..../DisChrgPeakPwr/3D_Config_Word2 |
| Name contains incorrect characters. | ..../DisChrgPeakPwr/3D_Config_Word3 |
| Name contains incorrect characters. | ..../Unit Delay External IC |
| Name contains incorrect characters. | ..../MaxChrgCurr/MaxDCChrgCurr/3D_Config_Word |
| Name contains incorrect characters. | ..../MaxDCChrgCurr/3D_Config_Word1 |
| Name contains incorrect characters. | ..../MaxDCChrgCurr/3D_Config_Word2 |
| Name contains incorrect characters. | ..../MaxDCChrgCurr/3D_Config_Word3 |
| Name contains incorrect characters. | ..../PwrLimitFlg/3D_Config_Word |
Identify names of Inport or Outport blocks that use characters that are not correct in C code.
Passed
All the Inport or Outport block names use correct characters.
Identify signal labels that are not correct for C variable names.
Passed
All signal labels use correct characters.
Identify block names that use characters that are not correct in C code.
Warning
The following block names use characters that are not correct for C code:
Identify levels in the model that include basic blocks and subsystems. Each level of a model must be designed with blocks of the same level (for example, only subsystems or only basic blocks).
Warning
The following level(s) in the model include basic blocks and subsystems:
Identify nonstandard display attributes in Simulink diagrams.
_________________________________________________________________________________________
Check format settings
Identify incorrect model-level format options.
Warning
The following format display options are incorrect.
| Display Attribute | Recommended Value | Actual Value |
|---|---|---|
| Display > Signals & Ports > Wide Nonscalar Lines | on | off |
| Display > Signals & Ports > Port Data Types | off | on |
| Display > Signals & Ports > Signal Dimensions | off | on |
| Display > Library Links | none | disabled |
Check block colors
Identify blocks using nonstandard colors.
Warning
The following blocks use nonstandard colors:
Check canvas colors
Identify canvases that are not white.
Passed
All diagrams use a white canvas.
_________________________________________________________________________________________
Check diagram zoom
Identify diagrams that do not have zoom factor set to 100 %.
Note: Zoom factors can differ for each instance of a model diagram opened in Simulink Editor
Warning
The following diagrams do not have zoom factor set to 100 percent:
Identify inconsistent formatting of text.
Warning
Font formatting is not consistent.
The following font characteristics are used in the model/subsystem. Font characteristics are sorted by number of occurrences. The most common characteristics are bold.
| Font Name | Font Size | Font Style |
|---|---|---|
|
Helvetica
|
10
|
normal
|
| Name | Value |
|---|---|
| Font Name | Common |
| Font Size | Common |
| Font Style | Common |
Identify input and output ports with incorrect positioning and configurations.
_________________________________________________________________________________________
Check Inport blocks position
Identify Inport blocks that result in left-flowing signals.
Warning
The following Inport blocks are too far to the right, resulting in left-flowing signals:
Check Outport block position
Identify Outport blocks that result in left-flowing signals.
Passed
There are no Outport blocks in the model that result in left-flowing signals.
_________________________________________________________________________________________
Check port orientation
Identify port blocks with nondefault orientation.
Warning
The following ports do not have the default orientation:
Check for duplicate Inports blocks
Identify duplicate Inport blocks.
Passed
All Inport blocks in the model are used once.
Identify port block names that are not uniformly displayed. The block names must all be displayed or none displayed. Library blocks are an exception to this rule. This check ignores masked and subsystem blocks.
_________________________________________________________________________________________
Check for incorrect port name display
Identify ports that are incorrectly displaying names.
Passed
Subsystem blocks are correctly displayed.
_________________________________________________________________________________________
Check for incorrect subsystem port name display
Identify subsystems that are incorrectly displaying names.
Passed
Subsystem blocks are correctly displayed.
| Name | Value |
|---|---|
| Display all port names (Diagram > Format > Show Block Name). | true |
Identify Inport and Outport blocks that do not specify Port number for the Icon display block parameter.
Passed
All port blocks display the port number.
Identify blocks where the name is not displayed below the block.
Warning
The following blocks have names that do not display below the blocks:
Identify whether to display block names.
_________________________________________________________________________________________
Check for blocks with hidden names and obvious function
Identify block names that are displayed but can be hidden due to obvious behavior.
Passed
All blocks with obvious behavior have hidden names.
_________________________________________________________________________________________
Check for non-descriptive displayed block names
Identify block names that are displayed but should be hidden due to a lack of a descriptive name.
Passed
All displayed names provide descriptive information.
_________________________________________________________________________________________
Check for missing block names
Identify block names that are hidden but should be displayed to show a descriptive name.
Warning
The following blocks have descriptive names, however, the names are hidden:
Identify Trigger and Enable blocks that are not located at the top of the subsystem diagram.
Passed
The model does not contain Trigger and Enable blocks, or the blocks are located at the top of the subsystem diagram.
Identify blocks that use and fail to display nondefault values.
Warning
The following blocks use and fail to display nondefault values:
Identify mismatches between names of ports and corresponding signals.
Warning
The following ports have names that differ from corresponding signals:
Match the name of the Trigger and Enable blocks to the name of the signal that triggers the subsystem. If the signal is not named, use any name for the block.
_________________________________________________________________________________________
Check Trigger block names
Identify Trigger blocks that do not match the names of the signals to which they are connected.
Passed
All Trigger blocks in the system are correctly named.
_________________________________________________________________________________________
Check for root level Trigger block
Identify Trigger blocks placed at the root level of the model.
Passed
No Trigger blocks where found at the root level.
_________________________________________________________________________________________
Check Enable block names
Identify Enable blocks that do not match the names of the signals to which they are connected.
Passed
All Enable blocks in the system are correctly named.
_________________________________________________________________________________________
Check for root level Enable block
Identify Enable blocks placed at the root level of the model.
Passed
No Enable blocks where found at the root level.
Identify propagated labels on signal lines.
_________________________________________________________________________________________
Check subsystem block input labels
Identify inputs to subsystem blocks to verify that the signals have labels.
Warning
The following subsystem-level Inport block signals should propagate signal labels from the parent system.
Check subsystem output labels
Identify outputs from subsystems that are labeled and display signal propagation.
Passed
All outputs from the subsystem have labels and display propagated signals.
_________________________________________________________________________________________
Signal propagation for nonsubsystem blocks
Identify the signal propagation status for both transformative and nontransformative blocks.
Passed
All outputs from non subsystem blocks correctly use labels and display propagated signals.
Identify unconnected block input ports, output ports, and signal lines.
Warning
The following blocks have unconnected ports and lines:
Identify blocks that are not allowed in discrete controllers. Prohibited blocks include all continuous blocks and some source and sink blocks.
Passed
All blocks in the model are allowed in discrete controllers.
Identify sink blocks that must be removed prior to code generation.
Passed
There are no prohibited blocks in the subsystem.
Identify incorrect scoping of From and Goto blocks. For signal flows, From and Goto blocks must use local scope. Control flow can use global scope.
Passed
All From and Goto blocks are used correctly.
Identify Switch blocks that do not use Boolean inputs for the switch condition (input 2), and do not use u2 ~= 0 for the Criteria for passing first input block parameter.
_________________________________________________________________________________________
Check Switch block parameters
Identify Switch blocks with the parameter Criteria for passing first input not set to u2 ~= 0.
Passed
The block parameter Criteria for passing first input is correctly configured.
_________________________________________________________________________________________
Check for Boolean switch condition
Identify blocks that do not use Boolean signal switch conditions (input 2).
Warning
The following Switch blocks use non-Boolean signals for the switch condition:
Identify Relational Operator blocks that connect to constants with the first (upper) input value.
Passed
All Relational Operator blocks with constant input values are configured correct.
Identify blocks with inconsistent indexing. To increase code efficiency, use zero-based indexing.
Passed
All blocks in the system use a consistent indexing method.
Identify tunable parameters used to specify expressions, data type conversions, or indexing operations.
Passed
Tunable parameters are not used in the model.
Check for subsystems that do not have the correct orientation. Blocks with the correct orientation have inputs on the left and outputs on the right.
Warning
The following subsystem blocks do not have the correct orientation:
Identify Stateflow charts and substates that incorrectly use or define exclusive and default states.
_________________________________________________________________________________________
Check Stateflow charts for exclusive states
Identify Stateflow charts that have singular exclusive (OR) states.
Passed
The Stateflow charts do not have singular exclusive (OR) states.
_________________________________________________________________________________________
Check Stateflow charts for undefined default states
Identify Stateflow charts that do not define default states.
Passed
Each Stateflow chart defines a default state.
_________________________________________________________________________________________
Check for multiple states assigned as the default state
At the root level in the Stateflow hierarchy only one state should be assigned as the default.
Passed
The root level of the chart has only one default state assigned.
_________________________________________________________________________________________
Check for substates with singular OR states
States configured as OR should always be part of a group of states.
Passed
No singular OR states were detected.
_________________________________________________________________________________________
Check for substates without default states defined
At every level in the Stateflow hierarchy a default state should be assigned.
Passed
All substates have default states assigned.
_________________________________________________________________________________________
Check for substates with multiple default states defined
At every level in the Stateflow hierarchy only one state should be assigned as the default.
Passed
All levels of the chart have only one default state assigned.
Identify transitions in Stateflow flow charts that are drawn incorrectly.
_________________________________________________________________________________________
Check for conditions drawn horizontally
Condition expressions should be drawn on the horizontal segments of flow charts.
Passed
All condition expressions were drawn horizontally.
_________________________________________________________________________________________
Check for action transitions drawn vertically
Transition actions should be drawn on the vertical segments of flow charts.
Passed
All transition actions were drawn vertically.
_________________________________________________________________________________________
Check for junctions for default transitions
All Junctions in a flow chart should have a default exit transition.
Passed
All Junctions have a default exit transition.
_________________________________________________________________________________________
Check for transitions that combine condition and action
Flow charts should not combine condition evaluations and action expressions in a single transition.
Passed
No combined expressions were found in the chart.
Identify missing line breaks between entry action (en), during action (du), and exit action (ex) entries in states. Identify missing line breaks after semicolons (;) in statements.
Passed
All state entries found are correctly formatted.
Identify graphical functions with multiple assignments of return values in Stateflow charts.
Passed
No multiple assignments of return values were found.
Identify all groupings of states that do not have a default transition or do not have the default state as the top-most state.
_________________________________________________________________________________________
Identify states that do not have default transitions.
Passed
All groupings of states have default transitions.
_________________________________________________________________________________________
Identify states where the default transition is not the top-most state.
Passed
The default states are in the correct position.
_________________________________________________________________________________________
Identify default transitions not connected to the top of the state.
Passed
All default transitions connect to the top of the state.
_________________________________________________________________________________________
Identify states with multiple default transitions.
Passed
All states have only one default transition.
Identify whether Stateflow charts have Use Strong Data Typing with Simulink I/O cleared.
Passed
Use Strong Data Typing with Simulink I/O is selected.
Identify Stateflow data objects with local scope that are not scoped at the chart level or below.
Passed
All Stateflow data objects are properly scoped.
Identify calls to graphical functions that are used in conditional expressions.
Passed
No conditional expressions containing calls to graphical functions were found.
Identify Stateflow objects that use MATLAB expressions that are not suitable for code generation.
Note: This check applies only to Stateflow charts that use C as the action language.
Passed
No Stateflow objects that use MATLAB expressions were found.
Identify pointer operations on custom code variables.
Note: This check applies only to Stateflow charts that use C as the action language.
Passed
No pointer operations were found.
Identify missing line breaks between transition actions.
Passed
All transition actions are formatted correctly.
Check the model for blocks configured for one-based indexing
Passed
All blocks in the model use zero-based indexing.
_________________________________________________________________________________________
These settings can lead to inefficient code generation when inputs always fall within the range of valid breakpoint values for lookup table blocks, including Lookup Table blocks, Prelookup blocks and Interpolation blocks.
Passed
The lookup table blocks have been configured to generate range-checking free code.
Identify unconnected lines, input ports, and output ports in the model
Warning
The following lines, input ports, or output ports are not properly connected in system: SOP
Check for constructs in the model that are not recommended for production code generation
Identify blocks that are not recommended to be used for code generation.
Passed
Constructs that are not recommended for production code generation were not found in the model or subsystem
Identify usage of Math Operation blocks in Simulink that might impact safety
Check usage of Abs blocks
Identify Absolute Value blocks that might produce unreachable code or overflows
Passed
All Abs blocks use data types that will not produce unreachable code or overflows.
_________________________________________________________________________________________
Check usage of Gain blocks
Identify Gain blocks whose value equals 1
Passed
No Gain blocks with value equal to 1 in the model or subsystem
_________________________________________________________________________________________
Check Usage of Assignment blocks
Identify Assignment blocks with possibly incomplete array initialization that do not have the simulation run-time diagnostic Action if any output element is not assigned set to:
Check consistent usage of vector indexing methods across the model or subsystem
Passed
All the blocks in the model use 'zero-based' vector indexing.
Identify Inport blocks in the top-level of the model with missing or inherited sample times, data types, or port dimensions. Inport block properties are specified with block parameters or Simulink signal data objects that explicitly resolve to the connected signal lines.
Warning
The following Inport blocks have undefined or inherited sample times, data types or port dimensions
| Inport | Link | Signal Object | Conditions |
|---|---|---|---|
| 2 | SOP/GcCDP_MaxCellTemp_C | - |
Missing signal data type Missing port dimension |
| 3 | SOP/GcCDP_MinCellTemp_C | - |
Missing signal data type Missing port dimension |
| 4 | SOP/GcSOC_MaxCellSOC_pct | - |
Missing signal data type Missing port dimension |
| 5 | SOP/GcSOC_MinCellSOC_pct | - |
Missing signal data type Missing port dimension |
| 6 | SOP/GeCTC_CtrCtlConnMode_enum | - |
Missing signal data type Missing port dimension |
| 7 | SOP/GcCDP_MaxCellVolt_mV | - |
Missing signal data type Missing port dimension |
| 8 | SOP/GcCDP_MinCellVolt_mV | - |
Missing signal data type Missing port dimension |
| 9 | SOP/GcHDP_PackVolt_V | - |
Missing signal data type Missing port dimension |
| 10 | SOP/GcCDP_SumCellVolt_V | - |
Missing signal data type Missing port dimension |
| 11 | SOP/GbCDP_SumCellVoltVld_flg | - |
Missing signal data type Missing port dimension |
| 12 | SOP/GeMSM_BMUState_enum | - |
Missing signal data type Missing port dimension |
| 13 | SOP/GcHDP_PackCrnt_A | - |
Missing signal data type Missing port dimension |
| 14 | SOP/GeFTC_FltLevel_enum | - |
Missing signal data type Missing port dimension |
| 15 | SOP/GeCTC_CtrCtlState_enum | - |
Missing signal data type Missing port dimension |
| 16 | SOP/GcACC_ACChrgCrntRqst_A | - |
Missing signal data type Missing port dimension |
| 17 | SOP/GcDCC_DCChrgCrntRqst_A | - |
Missing signal data type Missing port dimension |
| 18 | SOP/GbISP_OpenContactor_flg | - |
Missing signal data type Missing port dimension |
| 19 | SOP/GbISP_PowerDown_flg | - |
Missing signal data type Missing port dimension |
| 20 | SOP/GbISP_DischrgPwrLimitLevel3_flg | - |
Missing signal data type Missing port dimension |
| 21 | SOP/GbISP_RegenPwrLimitLevel3_flg | - |
Missing signal data type Missing port dimension |
| 22 | SOP/GbISP_DischrgPwrLimitLevel2_flg | - |
Missing signal data type Missing port dimension |
| 23 | SOP/GbISP_RegenPwrLimitLevel2_flg | - |
Missing signal data type Missing port dimension |
| 24 | SOP/GbISP_DCChrgCurrLimitLevel2_flg | - |
Missing signal data type Missing port dimension |
| 25 | SOP/GbISP_ACChrgCurrLimitLevel2_flg | - |
Missing signal data type Missing port dimension |
| 26 | SOP/GbISP_DischrgPwrLimitLevel1_flg | - |
Missing signal data type Missing port dimension |
| 27 | SOP/GbISP_RegenPwrLimitLevel1_flg | - |
Missing signal data type Missing port dimension |
| 28 | SOP/GcSOH_PackSOH_pct | - |
Missing signal data type Missing port dimension |
| 29 | SOP/GeUDS_CapSel_enum | - |
Missing signal data type Missing port dimension |
| 30 | SOP/GeUDS_AreaSel_enum | - |
Missing signal data type Missing port dimension |
| 31 | SOP/GbUDS_TestMode1_flg | - |
Missing signal data type Missing port dimension |