# Coverage Report for CDP_UT

## Table of Contents

1. Analysis Information
2. Tests
3. Summary
4. Details

## Analysis Information

### Model Information

Model version | 'M110C20'
Author | xigkd
Last saved | Fri Apr 09 20:08:30 2021

### Harness information

Harness model(s) | CDP_UT_Harness
Harness model owner | CDP_UT

### Simulation Optimization Options

Default parameter behavior | inlined
Block reduction | forced off
Conditional branch optimization | on

### Coverage Options

Analyzed model | CDP_UT
Logic block short circuiting | off
MCDC mode | masking

### Blocks Eliminated from Coverage Analysis

# Model Object | Rationale
CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/Comparison1 | It might not be executed because of Conditional input branch optimization
CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/Logical Operator1 | It might not be executed because of Conditional input branch optimization
CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/Comparison4 | It might not be executed because of Conditional input branch optimization
CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/Logical | It might not be executed because of Conditional input branch optimization
CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/Comparison4 | It might not be executed because of Conditional input branch optimization
CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/Logical | It might not be executed because of Conditional input branch optimization
CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/Comparison1 | It might not be executed because of Conditional input branch optimization
CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/Logical Operator1 | It might not be executed because of Conditional input branch optimization
CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/Comparison1 | It might not be executed because of Conditional input branch optimization
CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/Logical Operator1 | It might not be executed because of Conditional input branch optimization

## Tests

Test# | Started execution | Ended execution
Test 1 | 09-Apr-2021 20:11:23 | 09-Apr-2021 20:17:02

## Summary

Model Hierarchy/Complexity | Test 1 |
|  | Decision | Condition | MCDC | Execution |
1. CDP_UT | 960 | 46% |
| 46% |
| 0% |
| 87% |
2. . . . CellDataPrc_20ms_sys | 955 | 46% |
| 46% |
| 0% |
| 87% |
3. . . . . . . BalDiag_20ms_sys | 6 | 50% |
| NA | NA | 100% |
4. . . . . . . . . . CDP_GaCDP_CellBalcOpLine_flg | 2 | 50% |
| NA | NA | 100% |
5. . . . . . . . . . CDP_GaCDP_CellBalcShrt_flg | 2 | 50% |
| NA | NA | 100% |
6. . . . . . . . . . CDP_GaCDP_CellBalc_flg | 2 | 50% |
| NA | NA | 100% |
7. . . . . . . CellVoltFltDet | 89 | 20% |
| 50% |
| 0% |
| 81% |
8. . . . . . . . . . CellFltLevel_Switch | 66 | 9% |
| NA | NA | 26% |
9. . . . . . . . . . . . . CDP_2D_Config_Word | 11 | 9% |
| NA | NA | 25% |
10. . . . . . . . . . . . . . . . Switch Case Action Subsystem |  | NA | NA | NA | 100% |
11. . . . . . . . . . . . . . . . Switch Case Action Subsystem1 |  | NA | NA | NA | 0% |
12. . . . . . . . . . . . . . . . Switch Case Action Subsystem2 |  | NA | NA | NA | 0% |
13. . . . . . . . . . . . . . . . Switch Case Action Subsystem3 |  | NA | NA | NA | 0% |
14. . . . . . . . . . . . . . . . Switch Case Action Subsystem4 |  | NA | NA | NA | 0% |
15. . . . . . . . . . . . . . . . Switch Case Action Subsystem5 |  | NA | NA | NA | 0% |
16. . . . . . . . . . . . . . . . Switch Case Action Subsystem6 |  | NA | NA | NA | 0% |
17. . . . . . . . . . . . . . . . Switch Case Action Subsystem7 |  | NA | NA | NA | 0% |
18. . . . . . . . . . . . . . . . Switch Case Action Subsystem8 |  | NA | NA | NA | 0% |
19. . . . . . . . . . . . . . . . Switch Case Action Subsystem9 |  | NA | NA | NA | 0% |
20. . . . . . . . . . . . . CDP_2D_Config_Word1 | 11 | 9% |
| NA | NA | 25% |
21. . . . . . . . . . . . . . . . Switch Case Action Subsystem |  | NA | NA | NA | 100% |
22. . . . . . . . . . . . . . . . Switch Case Action Subsystem1 |  | NA | NA | NA | 0% |
23. . . . . . . . . . . . . . . . Switch Case Action Subsystem2 |  | NA | NA | NA | 0% |
24. . . . . . . . . . . . . . . . Switch Case Action Subsystem3 |  | NA | NA | NA | 0% |
25. . . . . . . . . . . . . . . . Switch Case Action Subsystem4 |  | NA | NA | NA | 0% |
26. . . . . . . . . . . . . . . . Switch Case Action Subsystem5 |  | NA | NA | NA | 0% |
27. . . . . . . . . . . . . . . . Switch Case Action Subsystem6 |  | NA | NA | NA | 0% |
28. . . . . . . . . . . . . . . . Switch Case Action Subsystem7 |  | NA | NA | NA | 0% |
29. . . . . . . . . . . . . . . . Switch Case Action Subsystem8 |  | NA | NA | NA | 0% |
30. . . . . . . . . . . . . . . . Switch Case Action Subsystem9 |  | NA | NA | NA | 0% |
31. . . . . . . . . . . . . CDP_2D_Config_Word2 | 11 | 9% |
| NA | NA | 25% |
32. . . . . . . . . . . . . . . . Switch Case Action Subsystem |  | NA | NA | NA | 100% |
33. . . . . . . . . . . . . . . . Switch Case Action Subsystem1 |  | NA | NA | NA | 0% |
34. . . . . . . . . . . . . . . . Switch Case Action Subsystem2 |  | NA | NA | NA | 0% |
35. . . . . . . . . . . . . . . . Switch Case Action Subsystem3 |  | NA | NA | NA | 0% |
36. . . . . . . . . . . . . . . . Switch Case Action Subsystem4 |  | NA | NA | NA | 0% |
37. . . . . . . . . . . . . . . . Switch Case Action Subsystem5 |  | NA | NA | NA | 0% |
38. . . . . . . . . . . . . . . . Switch Case Action Subsystem6 |  | NA | NA | NA | 0% |
39. . . . . . . . . . . . . . . . Switch Case Action Subsystem7 |  | NA | NA | NA | 0% |
40. . . . . . . . . . . . . . . . Switch Case Action Subsystem8 |  | NA | NA | NA | 0% |
41. . . . . . . . . . . . . . . . Switch Case Action Subsystem9 |  | NA | NA | NA | 0% |
42. . . . . . . . . . . . . CDP_2D_Config_Word3 | 11 | 9% |
| NA | NA | 25% |
43. . . . . . . . . . . . . . . . Switch Case Action Subsystem |  | NA | NA | NA | 100% |
44. . . . . . . . . . . . . . . . Switch Case Action Subsystem1 |  | NA | NA | NA | 0% |
45. . . . . . . . . . . . . . . . Switch Case Action Subsystem2 |  | NA | NA | NA | 0% |
46. . . . . . . . . . . . . . . . Switch Case Action Subsystem3 |  | NA | NA | NA | 0% |
47. . . . . . . . . . . . . . . . Switch Case Action Subsystem4 |  | NA | NA | NA | 0% |
48. . . . . . . . . . . . . . . . Switch Case Action Subsystem5 |  | NA | NA | NA | 0% |
49. . . . . . . . . . . . . . . . Switch Case Action Subsystem6 |  | NA | NA | NA | 0% |
50. . . . . . . . . . . . . . . . Switch Case Action Subsystem7 |  | NA | NA | NA | 0% |
51. . . . . . . . . . . . . . . . Switch Case Action Subsystem8 |  | NA | NA | NA | 0% |
52. . . . . . . . . . . . . . . . Switch Case Action Subsystem9 |  | NA | NA | NA | 0% |
53. . . . . . . . . . . . . CDP_2D_Config_Word4 | 11 | 9% |
| NA | NA | 25% |
54. . . . . . . . . . . . . . . . Switch Case Action Subsystem |  | NA | NA | NA | 100% |
55. . . . . . . . . . . . . . . . Switch Case Action Subsystem1 |  | NA | NA | NA | 0% |
56. . . . . . . . . . . . . . . . Switch Case Action Subsystem2 |  | NA | NA | NA | 0% |
57. . . . . . . . . . . . . . . . Switch Case Action Subsystem3 |  | NA | NA | NA | 0% |
58. . . . . . . . . . . . . . . . Switch Case Action Subsystem4 |  | NA | NA | NA | 0% |
59. . . . . . . . . . . . . . . . Switch Case Action Subsystem5 |  | NA | NA | NA | 0% |
60. . . . . . . . . . . . . . . . Switch Case Action Subsystem6 |  | NA | NA | NA | 0% |
61. . . . . . . . . . . . . . . . Switch Case Action Subsystem7 |  | NA | NA | NA | 0% |
62. . . . . . . . . . . . . . . . Switch Case Action Subsystem8 |  | NA | NA | NA | 0% |
63. . . . . . . . . . . . . . . . Switch Case Action Subsystem9 |  | NA | NA | NA | 0% |
64. . . . . . . . . . . . . CDP_2D_Config_Word5 | 11 | 9% |
| NA | NA | 25% |
65. . . . . . . . . . . . . . . . Switch Case Action Subsystem |  | NA | NA | NA | 100% |
66. . . . . . . . . . . . . . . . Switch Case Action Subsystem1 |  | NA | NA | NA | 0% |
67. . . . . . . . . . . . . . . . Switch Case Action Subsystem2 |  | NA | NA | NA | 0% |
68. . . . . . . . . . . . . . . . Switch Case Action Subsystem3 |  | NA | NA | NA | 0% |
69. . . . . . . . . . . . . . . . Switch Case Action Subsystem4 |  | NA | NA | NA | 0% |
70. . . . . . . . . . . . . . . . Switch Case Action Subsystem5 |  | NA | NA | NA | 0% |
71. . . . . . . . . . . . . . . . Switch Case Action Subsystem6 |  | NA | NA | NA | 0% |
72. . . . . . . . . . . . . . . . Switch Case Action Subsystem7 |  | NA | NA | NA | 0% |
73. . . . . . . . . . . . . . . . Switch Case Action Subsystem8 |  | NA | NA | NA | 0% |
74. . . . . . . . . . . . . . . . Switch Case Action Subsystem9 |  | NA | NA | NA | 0% |
75. . . . . . . . . . DiffCellVoltDet | 7 | 50% |
| 50% |
| 0% |
| 100% |
76. . . . . . . . . . . . . DiffCellVolt_SateSwitch_Sys | 6 | 50% |
| 50% |
| 0% |
| 100% |
77. . . . . . . . . . . . . . . . CellVoltDiffFltLv1Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
78. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
79. . . . . . . . . . . . . . . . CellVoltDiffFltLv2Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
80. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
81. . . . . . . . . . . . . . . . CellVoltDiffFltLv3Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
82. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
83. . . . . . . . . . . . . DiffVoltCheck_Condition | 1 | 50% |
| 50% |
| 0% |
| 100% |
84. . . . . . . . . . MaxCellVoltDet | 6 | 50% |
| 50% |
| 0% |
| 100% |
85. . . . . . . . . . . . . CellVoltHiFltDet | 6 | 50% |
| 50% |
| 0% |
| 100% |
86. . . . . . . . . . . . . . . . CellVoltHiFltLv1Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
87. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
88. . . . . . . . . . . . . . . . CellVoltHiFltLv2Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
89. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
90. . . . . . . . . . . . . . . . CellVoltHiFltLv3Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
91. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
92. . . . . . . . . . . . . MaxVoltCheck_Condition |  | NA | 50% |
| 0% |
| 100% |
93. . . . . . . . . . MinCellVoltDet | 6 | 50% |
| 50% |
| 0% |
| 100% |
94. . . . . . . . . . . . . CellVoltLowFltDet | 6 | 50% |
| 50% |
| 0% |
| 100% |
95. . . . . . . . . . . . . . . . CellVoltLowFltLv1Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
96. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
97. . . . . . . . . . . . . . . . CellVoltLowFltLv2Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
98. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
99. . . . . . . . . . . . . . . . CellVoltLowFltLv3Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
100. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
101. . . . . . . . . . . . . MinVoltCheck_Condition |  | NA | 50% |
| 0% |
| 100% |
102. . . . . . . . . . RngCellVoltDet | 4 | 50% |
| 50% |
| 0% |
| 100% |
103. . . . . . . . . . . . . CellVoltRngHiCheck_Condition |  | NA | 50% |
| 0% |
| 100% |
104. . . . . . . . . . . . . CellVoltRngHiFltDet | 2 | 50% |
| 50% |
| 0% |
| 100% |
105. . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
106. . . . . . . . . . . . . CellVoltRngLowCheck_Condition |  | NA | 50% |
| 0% |
| 100% |
107. . . . . . . . . . . . . CellVoltRngLowFltDet | 2 | 50% |
| 50% |
| 0% |
| 100% |
108. . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
109. . . . . . . ChrgWkUpDet |  | NA | 50% |
| 0% |
| 100% |
110. . . . . . . TempDataPrc_20ms_sys | 440 | 41% |
| 40% |
| 0% |
| 73% |
111. . . . . . . . . . AFETempVld_Output | 2 | 50% |
| 50% |
| 0% |
| 100% |
112. . . . . . . . . . . . . CDP_GaCDP_CMUPCBTempVld_flg | 2 | 50% |
| NA | NA | 100% |
113. . . . . . . . . . AFETemp_Flt | 5 | 50% |
| 50% |
| NA | 100% |
114. . . . . . . . . . . . . CDP_GbCDP_CMUTempHighFlt_flg | 2 | 50% |
| NA | NA | 100% |
115. . . . . . . . . . . . . Hysteresis | 3 | 50% |
| 50% |
| NA | 100% |
116. . . . . . . . . . AFETemp_Output | 10 | 50% |
| 50% |
| 0% |
| 100% |
117. . . . . . . . . . . . . CDP_GaCDP_CMUPCBTemp_C | 2 | 50% |
| NA | NA | 100% |
118. . . . . . . . . . BusbarTempVld_Output | 2 | 50% |
| 50% |
| 0% |
| 100% |
119. . . . . . . . . . . . . OverWrite4 | 2 | 50% |
| NA | NA | 100% |
120. . . . . . . . . . BusbarTemp_Output | 80 | 45% |
| 50% |
| 0% |
| 100% |
121. . . . . . . . . . . . . BusbarTemp_SignalFilt | 26 | 30% |
| 50% |
| NA | 100% |
122. . . . . . . . . . . . . . . . 1D_Config_Word | 11 | 9% |
| NA | NA | 100% |
123. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem |  | NA | NA | NA | 100% |
124. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem1 |  | NA | NA | NA | 100% |
125. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem2 |  | NA | NA | NA | 100% |
126. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem3 |  | NA | NA | NA | 100% |
127. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem4 |  | NA | NA | NA | 100% |
128. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem5 |  | NA | NA | NA | 100% |
129. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem6 |  | NA | NA | NA | 100% |
130. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem7 |  | NA | NA | NA | 100% |
131. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem8 |  | NA | NA | NA | 100% |
132. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem9 |  | NA | NA | NA | 100% |
133. . . . . . . . . . . . . . . . InputValueCalc | 6 | 50% |
| NA | NA | NA |
134. . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/InputValueCalc | 5 | 50% |
| NA | NA | NA |
135. . . . . . . . . . . . . . . . . . . . . . SF: Default | 1 | 50% |
| NA | NA | NA |
136. . . . . . . . . . . . . . . . . . . . . . SF: Update | 2 | 25% |
| NA | NA | NA |
137. . . . . . . . . . . . . . . . MaxValue_sort | 9 | 31% |
| NA | NA | NA |
138. . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/MaxValue_sort | 8 | 31% |
| NA | NA | NA |
139. . . . . . . . . . . . . . . . . . . . . . SF: sort | 8 | 31% |
| NA | NA | NA |
140. . . . . . . . . . . . . OverWrite2 | 2 | 50% |
| NA | NA | 100% |
141. . . . . . . . . . . . . ValidValueFilter_BusbarTemp | 3 | 75% |
| NA | NA | NA |
142. . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/ValidValueFilter_BusbarTemp | 2 | 75% |
| NA | NA | NA |
143. . . . . . . . . . . . . . . . . . . SF: VldValueFilter | 2 | 75% |
| NA | NA | NA |
144. . . . . . . . . . CDP_GaCDP_ModuleTempHighFlt_flg | 2 | 50% |
| NA | NA | 100% |
145. . . . . . . . . . CMUPCBTemp_Flt | 5 | 50% |
| 50% |
| NA | 100% |
146. . . . . . . . . . . . . CDP_GbCDP_CMUTempHighFlt_flg | 2 | 50% |
| NA | NA | 100% |
147. . . . . . . . . . . . . Hysteresis | 3 | 50% |
| 50% |
| NA | 100% |
148. . . . . . . . . . CMUTempVld_Output | 2 | 50% |
| 50% |
| 0% |
| 100% |
149. . . . . . . . . . . . . CDP_GaCDP_CMUPCBTempVld_flg | 2 | 50% |
| NA | NA | 100% |
150. . . . . . . . . . CMUTemp_Output | 34 | 50% |
| 50% |
| 0% |
| 100% |
151. . . . . . . . . . . . . CDP_GaCDP_CMUPCBTemp_C | 2 | 50% |
| NA | NA | 100% |
152. . . . . . . . . . CellTemp_SelfCheck | 2 | 50% |
| 50% |
| 0% |
| 100% |
153. . . . . . . . . . . . . OverWrite | 2 | 50% |
| NA | NA | 100% |
154. . . . . . . . . . MaxMin_AFETemp_Get | 24 | 10% |
| 13% |
| 0% |
| 34% |
155. . . . . . . . . . . . . AllAFETemp_FaultCheck | 1 | 100% |
| 50% |
| 0% |
| 100% |
156. . . . . . . . . . . . . . . . AFETempVld | 1 | 100% |
| 50% |
| 0% |
| 100% |
157. . . . . . . . . . . . . MaxMin_AFETemp_Get_Sys | 23 | 4% |
| 0% |
| 0% |
| 28% |
158. . . . . . . . . . . . . . . . CDP_GcCDP_MaxCMUPCBTempNumb_numb | 2 | 0% |
| NA | NA | 67% |
159. . . . . . . . . . . . . . . . CDP_GcCDP_MaxCMUPCBTemp_C | 2 | 0% |
| NA | NA | 67% |
160. . . . . . . . . . . . . . . . CDP_GcCDP_MinCMUPCBTempNumb_numb | 2 | 0% |
| NA | NA | 67% |
161. . . . . . . . . . . . . . . . CDP_GcCDP_MinCMUPCBTemp_C | 2 | 0% |
| NA | NA | 67% |
162. . . . . . . . . . . . . . . . MinAFETemp_ForIterator | 13 | 0% |
| 0% |
| 0% |
| 7% |
163. . . . . . . . . . . . . . . . . . . MaxAFETemp_ForIterator | 6 | 0% |
| 0% |
| 0% |
| 8% |
164. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC | 2 | 0% |
| NA | NA | 0% |
165. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC2 | 2 | 0% |
| NA | NA | 0% |
166. . . . . . . . . . . . . . . . . . . MinAFETemp_ForIterator | 6 | 0% |
| 0% |
| 0% |
| 8% |
167. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC1 | 2 | 0% |
| NA | NA | 0% |
168. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC2 | 2 | 0% |
| NA | NA | 0% |
169. . . . . . . . . . MaxMin_BusbarTemp_Get | 83 | 39% |
| 24% |
| 0% |
| 67% |
170. . . . . . . . . . . . . AllBusbarTemp_FaultCheck | 4 | 50% |
| 49% |
| 0% |
| 62% |
171. . . . . . . . . . . . . . . . BusbarTempVld | 1 | 50% |
| 0% |
| 0% |
| 0% |
172. . . . . . . . . . . . . . . . OverWrite | 2 | 50% |
| NA | NA | 100% |
173. . . . . . . . . . . . . BusbarTempMax_SignalFilt | 25 | 52% |
| NA | NA | 100% |
174. . . . . . . . . . . . . . . . 1D_Config_Word | 11 | 9% |
| NA | NA | 100% |
175. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem |  | NA | NA | NA | 100% |
176. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem1 |  | NA | NA | NA | 100% |
177. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem2 |  | NA | NA | NA | 100% |
178. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem3 |  | NA | NA | NA | 100% |
179. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem4 |  | NA | NA | NA | 100% |
180. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem5 |  | NA | NA | NA | 100% |
181. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem6 |  | NA | NA | NA | 100% |
182. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem7 |  | NA | NA | NA | 100% |
183. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem8 |  | NA | NA | NA | 100% |
184. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem9 |  | NA | NA | NA | 100% |
185. . . . . . . . . . . . . . . . InputValueCalc | 4 | 60% |
| NA | NA | NA |
186. . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/InputValueCalc | 3 | 60% |
| NA | NA | NA |
187. . . . . . . . . . . . . . . . . . . . . . SF: VldValueFilter | 3 | 60% |
| NA | NA | NA |
188. . . . . . . . . . . . . . . . MaxValue_sort | 6 | 90% |
| NA | NA | NA |
189. . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/MaxValue_sort | 5 | 90% |
| NA | NA | NA |
190. . . . . . . . . . . . . . . . . . . . . . SF: sort | 5 | 90% |
| NA | NA | NA |
191. . . . . . . . . . . . . . . . ValueCalc |  | NA | NA | NA | 100% |
192. . . . . . . . . . . . . . . . ValueIndexCalc | 4 | 60% |
| NA | NA | 100% |
193. . . . . . . . . . . . . . . . . . . InputValueCalc1 | 4 | 60% |
| NA | NA | NA |
194. . . . . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/ValueIndexCalc/InputValueCalc1 | 3 | 60% |
| NA | NA | NA |
195. . . . . . . . . . . . . . . . . . . . . . . . . SF: VldValueFilter | 3 | 60% |
| NA | NA | NA |
196. . . . . . . . . . . . . BusbarTempMin_SignalFilt | 25 | 52% |
| NA | NA | 100% |
197. . . . . . . . . . . . . . . . 1D_Config_Word | 11 | 9% |
| NA | NA | 100% |
198. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem |  | NA | NA | NA | 100% |
199. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem1 |  | NA | NA | NA | 100% |
200. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem2 |  | NA | NA | NA | 100% |
201. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem3 |  | NA | NA | NA | 100% |
202. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem4 |  | NA | NA | NA | 100% |
203. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem5 |  | NA | NA | NA | 100% |
204. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem6 |  | NA | NA | NA | 100% |
205. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem7 |  | NA | NA | NA | 100% |
206. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem8 |  | NA | NA | NA | 100% |
207. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem9 |  | NA | NA | NA | 100% |
208. . . . . . . . . . . . . . . . InputValueCalc | 4 | 60% |
| NA | NA | NA |
209. . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/InputValueCalc | 3 | 60% |
| NA | NA | NA |
210. . . . . . . . . . . . . . . . . . . . . . SF: VldValueFilter | 3 | 60% |
| NA | NA | NA |
211. . . . . . . . . . . . . . . . MaxValue_sort | 6 | 90% |
| NA | NA | NA |
212. . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/MaxValue_sort | 5 | 90% |
| NA | NA | NA |
213. . . . . . . . . . . . . . . . . . . . . . SF: sort | 5 | 90% |
| NA | NA | NA |
214. . . . . . . . . . . . . . . . ValueCalc |  | NA | NA | NA | 100% |
215. . . . . . . . . . . . . . . . ValueIndexCalc | 4 | 60% |
| NA | NA | 100% |
216. . . . . . . . . . . . . . . . . . . InputValueCalc1 | 4 | 60% |
| NA | NA | NA |
217. . . . . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/ValueIndexCalc/InputValueCalc1 | 3 | 60% |
| NA | NA | NA |
218. . . . . . . . . . . . . . . . . . . . . . . . . SF: VldValueFilter | 3 | 60% |
| NA | NA | NA |
219. . . . . . . . . . . . . MaxMin_BusbarAvgTemp_Get_Sys | 5 | 17% |
| NA | NA | 29% |
220. . . . . . . . . . . . . . . . MinBusbarTemp_ForIterator | 1 | 0% |
| NA | NA | 0% |
221. . . . . . . . . . . . . . . . OverWrite1 | 2 | 0% |
| NA | NA | 67% |
222. . . . . . . . . . . . . MaxMin_BusbarTemp_Get_Sys | 16 | 5% |
| 0% |
| 0% |
| 13% |
223. . . . . . . . . . . . . . . . MinBusbarTemp_ForIterator | 13 | 0% |
| 0% |
| 0% |
| 7% |
224. . . . . . . . . . . . . . . . . . . MaxBusbarTemp_ForIterator | 6 | 0% |
| 0% |
| 0% |
| 8% |
225. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC | 2 | 0% |
| NA | NA | 0% |
226. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC2 | 2 | 0% |
| NA | NA | 0% |
227. . . . . . . . . . . . . . . . . . . MinBusbarTemp_ForIterator | 6 | 0% |
| 0% |
| 0% |
| 8% |
228. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC1 | 2 | 0% |
| NA | NA | 0% |
229. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC2 | 2 | 0% |
| NA | NA | 0% |
230. . . . . . . . . . . . . OverWrite | 2 | 50% |
| NA | NA | 100% |
231. . . . . . . . . . . . . OverWrite1 | 2 | 50% |
| NA | NA | 100% |
232. . . . . . . . . . . . . OverWrite2 | 2 | 50% |
| NA | NA | 100% |
233. . . . . . . . . . . . . OverWrite3 | 2 | 50% |
| NA | NA | 100% |
234. . . . . . . . . . MaxMin_CMUTemp_Get | 24 | 10% |
| 13% |
| 0% |
| 34% |
235. . . . . . . . . . . . . AllCMUPCBTemp_FaultCheck | 1 | 100% |
| 50% |
| 0% |
| 100% |
236. . . . . . . . . . . . . . . . CMUTempVld | 1 | 100% |
| 50% |
| 0% |
| 100% |
237. . . . . . . . . . . . . MaxMin_CMUPCBTemp_Get_Sys | 23 | 4% |
| 0% |
| 0% |
| 28% |
238. . . . . . . . . . . . . . . . CDP_GcCDP_MaxCMUPCBTempNumb_numb | 2 | 0% |
| NA | NA | 67% |
239. . . . . . . . . . . . . . . . CDP_GcCDP_MaxCMUPCBTemp_C | 2 | 0% |
| NA | NA | 67% |
240. . . . . . . . . . . . . . . . CDP_GcCDP_MinCMUPCBTempNumb_numb | 2 | 0% |
| NA | NA | 67% |
241. . . . . . . . . . . . . . . . CDP_GcCDP_MinCMUPCBTemp_C | 2 | 0% |
| NA | NA | 67% |
242. . . . . . . . . . . . . . . . MinCMUTemp_ForIterator | 13 | 0% |
| 0% |
| 0% |
| 7% |
243. . . . . . . . . . . . . . . . . . . MaxCMUTemp_ForIterator | 6 | 0% |
| 0% |
| 0% |
| 8% |
244. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC | 2 | 0% |
| NA | NA | 0% |
245. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC2 | 2 | 0% |
| NA | NA | 0% |
246. . . . . . . . . . . . . . . . . . . MinCMUTemp_ForIterator | 6 | 0% |
| 0% |
| 0% |
| 8% |
247. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC1 | 2 | 0% |
| NA | NA | 0% |
248. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC2 | 2 | 0% |
| NA | NA | 0% |
249. . . . . . . . . . MaxMin_CellTemp_Get | 83 | 39% |
| 24% |
| 0% |
| 67% |
250. . . . . . . . . . . . . AllCellTemp_FaultCheck | 4 | 50% |
| 49% |
| 0% |
| 62% |
251. . . . . . . . . . . . . . . . CellTempVld | 1 | 50% |
| 0% |
| 0% |
| 0% |
252. . . . . . . . . . . . . . . . OverWrite | 2 | 50% |
| NA | NA | 100% |
253. . . . . . . . . . . . . CellTempMax_SignalFilt | 25 | 52% |
| NA | NA | 100% |
254. . . . . . . . . . . . . . . . 1D_Config_Word | 11 | 9% |
| NA | NA | 100% |
255. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem |  | NA | NA | NA | 100% |
256. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem1 |  | NA | NA | NA | 100% |
257. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem2 |  | NA | NA | NA | 100% |
258. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem3 |  | NA | NA | NA | 100% |
259. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem4 |  | NA | NA | NA | 100% |
260. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem5 |  | NA | NA | NA | 100% |
261. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem6 |  | NA | NA | NA | 100% |
262. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem7 |  | NA | NA | NA | 100% |
263. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem8 |  | NA | NA | NA | 100% |
264. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem9 |  | NA | NA | NA | 100% |
265. . . . . . . . . . . . . . . . InputValueCalc | 4 | 60% |
| NA | NA | NA |
266. . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/InputValueCalc | 3 | 60% |
| NA | NA | NA |
267. . . . . . . . . . . . . . . . . . . . . . SF: VldValueFilter | 3 | 60% |
| NA | NA | NA |
268. . . . . . . . . . . . . . . . MaxValue_sort | 6 | 90% |
| NA | NA | NA |
269. . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/MaxValue_sort | 5 | 90% |
| NA | NA | NA |
270. . . . . . . . . . . . . . . . . . . . . . SF: sort | 5 | 90% |
| NA | NA | NA |
271. . . . . . . . . . . . . . . . ValueCalc |  | NA | NA | NA | 100% |
272. . . . . . . . . . . . . . . . ValueIndexCalc | 4 | 60% |
| NA | NA | 100% |
273. . . . . . . . . . . . . . . . . . . InputValueCalc1 | 4 | 60% |
| NA | NA | NA |
274. . . . . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/ValueIndexCalc/InputValueCalc1 | 3 | 60% |
| NA | NA | NA |
275. . . . . . . . . . . . . . . . . . . . . . . . . SF: VldValueFilter | 3 | 60% |
| NA | NA | NA |
276. . . . . . . . . . . . . CellTempMin_SignalFilt | 25 | 52% |
| NA | NA | 100% |
277. . . . . . . . . . . . . . . . 1D_Config_Word | 11 | 9% |
| NA | NA | 100% |
278. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem |  | NA | NA | NA | 100% |
279. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem1 |  | NA | NA | NA | 100% |
280. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem2 |  | NA | NA | NA | 100% |
281. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem3 |  | NA | NA | NA | 100% |
282. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem4 |  | NA | NA | NA | 100% |
283. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem5 |  | NA | NA | NA | 100% |
284. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem6 |  | NA | NA | NA | 100% |
285. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem7 |  | NA | NA | NA | 100% |
286. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem8 |  | NA | NA | NA | 100% |
287. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem9 |  | NA | NA | NA | 100% |
288. . . . . . . . . . . . . . . . InputValueCalc | 4 | 60% |
| NA | NA | NA |
289. . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/InputValueCalc | 3 | 60% |
| NA | NA | NA |
290. . . . . . . . . . . . . . . . . . . . . . SF: VldValueFilter | 3 | 60% |
| NA | NA | NA |
291. . . . . . . . . . . . . . . . MaxValue_sort | 6 | 90% |
| NA | NA | NA |
292. . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/MaxValue_sort | 5 | 90% |
| NA | NA | NA |
293. . . . . . . . . . . . . . . . . . . . . . SF: sort | 5 | 90% |
| NA | NA | NA |
294. . . . . . . . . . . . . . . . ValueCalc |  | NA | NA | NA | 100% |
295. . . . . . . . . . . . . . . . ValueIndexCalc | 4 | 60% |
| NA | NA | 100% |
296. . . . . . . . . . . . . . . . . . . InputValueCalc1 | 4 | 60% |
| NA | NA | NA |
297. . . . . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/ValueIndexCalc/InputValueCalc1 | 3 | 60% |
| NA | NA | NA |
298. . . . . . . . . . . . . . . . . . . . . . . . . SF: VldValueFilter | 3 | 60% |
| NA | NA | NA |
299. . . . . . . . . . . . . MaxMin_CellAvgTemp_Get_Sys | 5 | 17% |
| NA | NA | 29% |
300. . . . . . . . . . . . . . . . MinCellTemp_ForIterator | 1 | 0% |
| NA | NA | 0% |
301. . . . . . . . . . . . . . . . OverWrite1 | 2 | 0% |
| NA | NA | 67% |
302. . . . . . . . . . . . . MaxMin_CellTemp_Get_Sys | 16 | 5% |
| 0% |
| 0% |
| 13% |
303. . . . . . . . . . . . . . . . MinCellTemp_ForIterator | 13 | 0% |
| 0% |
| 0% |
| 7% |
304. . . . . . . . . . . . . . . . . . . MaxCellTemp_ForIterator | 6 | 0% |
| 0% |
| 0% |
| 8% |
305. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC | 2 | 0% |
| NA | NA | 0% |
306. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC2 | 2 | 0% |
| NA | NA | 0% |
307. . . . . . . . . . . . . . . . . . . MinCellTemp_ForIterator | 6 | 0% |
| 0% |
| 0% |
| 8% |
308. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC1 | 2 | 0% |
| NA | NA | 0% |
309. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC2 | 2 | 0% |
| NA | NA | 0% |
310. . . . . . . . . . . . . OverWrite | 2 | 50% |
| NA | NA | 100% |
311. . . . . . . . . . . . . OverWrite1 | 2 | 50% |
| NA | NA | 100% |
312. . . . . . . . . . . . . OverWrite2 | 2 | 50% |
| NA | NA | 100% |
313. . . . . . . . . . . . . OverWrite3 | 2 | 50% |
| NA | NA | 100% |
314. . . . . . . . . . NTCTempVld_Output | 2 | 50% |
| 50% |
| 0% |
| 100% |
315. . . . . . . . . . . . . OverWrite4 | 2 | 50% |
| NA | NA | 100% |
316. . . . . . . . . . NTCTemp_Output | 80 | 45% |
| 50% |
| 0% |
| 100% |
317. . . . . . . . . . . . . CellTemp_SignalFilt | 26 | 30% |
| 50% |
| NA | 100% |
318. . . . . . . . . . . . . . . . 1D_Config_Word | 11 | 9% |
| NA | NA | 100% |
319. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem |  | NA | NA | NA | 100% |
320. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem1 |  | NA | NA | NA | 100% |
321. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem2 |  | NA | NA | NA | 100% |
322. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem3 |  | NA | NA | NA | 100% |
323. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem4 |  | NA | NA | NA | 100% |
324. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem5 |  | NA | NA | NA | 100% |
325. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem6 |  | NA | NA | NA | 100% |
326. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem7 |  | NA | NA | NA | 100% |
327. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem8 |  | NA | NA | NA | 100% |
328. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem9 |  | NA | NA | NA | 100% |
329. . . . . . . . . . . . . . . . InputValueCalc | 6 | 50% |
| NA | NA | NA |
330. . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/InputValueCalc | 5 | 50% |
| NA | NA | NA |
331. . . . . . . . . . . . . . . . . . . . . . SF: Default | 1 | 50% |
| NA | NA | NA |
332. . . . . . . . . . . . . . . . . . . . . . SF: Update | 2 | 25% |
| NA | NA | NA |
333. . . . . . . . . . . . . . . . MaxValue_sort | 9 | 31% |
| NA | NA | NA |
334. . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/MaxValue_sort | 8 | 31% |
| NA | NA | NA |
335. . . . . . . . . . . . . . . . . . . . . . SF: sort | 8 | 31% |
| NA | NA | NA |
336. . . . . . . . . . . . . OverWrite2 | 2 | 50% |
| NA | NA | 100% |
337. . . . . . . . . . . . . ValidValueFilter_CellTemp | 3 | 75% |
| NA | NA | NA |
338. . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/ValidValueFilter_CellTemp | 2 | 75% |
| NA | NA | NA |
339. . . . . . . . . . . . . . . . . . . SF: VldValueFilter | 2 | 75% |
| NA | NA | NA |
340. . . . . . . TempFltDet | 52 | 50% |
| 50% |
| 0% |
| 100% |
341. . . . . . . . . . BusbarTempDiffFltDet | 4 | 50% |
| 50% |
| 0% |
| 100% |
342. . . . . . . . . . . . . BusbarTempDiffFltDet_Sys | 4 | 50% |
| 50% |
| 0% |
| 100% |
343. . . . . . . . . . . . . . . . BusbarTempDiffFltLv1Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
344. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
345. . . . . . . . . . . . . . . . BusbarTempDiffFltLv2Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
346. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
347. . . . . . . . . . . . . DiffTempCheck_Condition |  | NA | 50% |
| 0% |
| 100% |
348. . . . . . . . . . BusbarTempHiFltDet | 6 | 50% |
| 50% |
| 0% |
| 100% |
349. . . . . . . . . . . . . BusbarTempHiFltDet_sys | 6 | 50% |
| 50% |
| 0% |
| 100% |
350. . . . . . . . . . . . . . . . BusbarTempHiFltLv1Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
351. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
352. . . . . . . . . . . . . . . . BusbarTempHiFltLv2Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
353. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
354. . . . . . . . . . . . . . . . BusbarTempHiFltLv3Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
355. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
356. . . . . . . . . . . . . MaxBusbarTempCheck_Condition |  | NA | 50% |
| 0% |
| 100% |
357. . . . . . . . . . BusbarTempLowFltDet | 6 | 50% |
| 50% |
| 0% |
| 100% |
358. . . . . . . . . . . . . BusbarTempLowFltDet_sys | 6 | 50% |
| 50% |
| 0% |
| 100% |
359. . . . . . . . . . . . . . . . BusbarTempLowFltLv1Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
360. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
361. . . . . . . . . . . . . . . . BusbarTempLowFltLv2Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
362. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
363. . . . . . . . . . . . . . . . BusbarTempLowFltLv3Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
364. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
365. . . . . . . . . . . . . MinBusbarTempCheck_Condition |  | NA | 50% |
| 0% |
| 100% |
366. . . . . . . . . . BusbarTempRngFltDet | 4 | 50% |
| 50% |
| 0% |
| 100% |
367. . . . . . . . . . . . . BusbarTempRngHiFltDet_sys | 2 | 50% |
| 50% |
| 0% |
| 100% |
368. . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
369. . . . . . . . . . . . . BusbarTempRngLowFltDet_sys | 2 | 50% |
| 50% |
| 0% |
| 100% |
370. . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
371. . . . . . . . . . . . . TempRngHiCheck_Condition |  | NA | 50% |
| NA | 100% |
372. . . . . . . . . . . . . TempRngLowCheck_Condition |  | NA | 50% |
| NA | 100% |
373. . . . . . . . . . CellTempDiffFltDet | 4 | 50% |
| 50% |
| 0% |
| 100% |
374. . . . . . . . . . . . . CellTempDiffFltDet_Sys | 4 | 50% |
| 50% |
| 0% |
| 100% |
375. . . . . . . . . . . . . . . . CellTempDiffFltLv1Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
376. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
377. . . . . . . . . . . . . . . . CellTempDiffFltLv2Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
378. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
379. . . . . . . . . . . . . DiffTempCheck_Condition |  | NA | 50% |
| 0% |
| 100% |
380. . . . . . . . . . CellTempHiFltDet | 6 | 50% |
| 50% |
| 0% |
| 100% |
381. . . . . . . . . . . . . CellTempHiFltDet_sys | 6 | 50% |
| 50% |
| 0% |
| 100% |
382. . . . . . . . . . . . . . . . CellTempHiFltLv1Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
383. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
384. . . . . . . . . . . . . . . . CellTempHiFltLv2Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
385. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
386. . . . . . . . . . . . . . . . CellTempHiFltLv3Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
387. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
388. . . . . . . . . . . . . MaxTempCheck_Condition |  | NA | 50% |
| 0% |
| 100% |
389. . . . . . . . . . CellTempHiFltDet_Chrg | 6 | 50% |
| 50% |
| 0% |
| 100% |
390. . . . . . . . . . . . . ChrgCellTempHiFltDet_sys | 6 | 50% |
| 50% |
| 0% |
| 100% |
391. . . . . . . . . . . . . . . . CellTempHiFltLv1Det_Chrg | 2 | 50% |
| 50% |
| 0% |
| 100% |
392. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
393. . . . . . . . . . . . . . . . CellTempHiFltLv2Det_Chrg | 2 | 50% |
| 50% |
| 0% |
| 100% |
394. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
395. . . . . . . . . . . . . . . . CellTempHiFltLv3Det_Chrg | 2 | 50% |
| 50% |
| 0% |
| 100% |
396. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
397. . . . . . . . . . . . . ChrgMaxTempCheck_Condition |  | NA | 50% |
| 0% |
| 100% |
398. . . . . . . . . . CellTempLowFltDet | 6 | 50% |
| 50% |
| 0% |
| 100% |
399. . . . . . . . . . . . . MinCellTemp_SateSwitch_Sys | 6 | 50% |
| 50% |
| 0% |
| 100% |
400. . . . . . . . . . . . . . . . CellTempLowFltLv1Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
401. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
402. . . . . . . . . . . . . . . . CellTempLowFltLv2Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
403. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
404. . . . . . . . . . . . . . . . CellTempLowFltLv3Det | 2 | 50% |
| 50% |
| 0% |
| 100% |
405. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
406. . . . . . . . . . . . . MinTempCheck_Condition |  | NA | 50% |
| 0% |
| 100% |
407. . . . . . . . . . CellTempLowFlt_Chrg | 6 | 50% |
| 50% |
| 0% |
| 100% |
408. . . . . . . . . . . . . ChrgMinCellTemp_SateSwitch_Sys | 6 | 50% |
| 50% |
| 0% |
| 100% |
409. . . . . . . . . . . . . . . . CellTempLowFltLv1Det_Chrg | 2 | 50% |
| 50% |
| 0% |
| 100% |
410. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
411. . . . . . . . . . . . . . . . CellTempLowFltLv2Det_Chrg | 2 | 50% |
| 50% |
| 0% |
| 100% |
412. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
413. . . . . . . . . . . . . . . . CellTempLowFltLv3Det_Chrg | 2 | 50% |
| 50% |
| 0% |
| 100% |
414. . . . . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
415. . . . . . . . . . . . . ChrgMinTempCheck_Condition |  | NA | 50% |
| 0% |
| 100% |
416. . . . . . . . . . CellTempRngFltDet | 4 | 50% |
| 50% |
| 0% |
| 100% |
417. . . . . . . . . . . . . CellTempRngHiFltDet_sys | 2 | 50% |
| 50% |
| 0% |
| 100% |
418. . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
419. . . . . . . . . . . . . CellTempRngLowFltDet_sys | 2 | 50% |
| 50% |
| 0% |
| 100% |
420. . . . . . . . . . . . . . . . CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg | 2 | 50% |
| NA | NA | 100% |
421. . . . . . . . . . . . . TempRngHiCheck_Condition |  | NA | 50% |
| NA | 100% |
422. . . . . . . . . . . . . TempRngLowCheck_Condition |  | NA | 50% |
| NA | 100% |
423. . . . . . . VoltDataPrc_20ms_sys | 368 | 54% |
| 50% |
| 0% |
| 100% |
424. . . . . . . . . . CellVoltVld_Output | 2 | 50% |
| 50% |
| 0% |
| 100% |
425. . . . . . . . . . . . . OverWrite5 | 2 | 50% |
| NA | NA | 100% |
426. . . . . . . . . . CellVolt_Output | 141 | 47% |
| 50% |
| 0% |
| 100% |
427. . . . . . . . . . . . . CellVolt_SignalFilt | 28 | 31% |
| 50% |
| NA | 100% |
428. . . . . . . . . . . . . . . . 1D_Config_Word | 11 | 9% |
| NA | NA | 100% |
429. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem |  | NA | NA | NA | 100% |
430. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem1 |  | NA | NA | NA | 100% |
431. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem2 |  | NA | NA | NA | 100% |
432. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem3 |  | NA | NA | NA | 100% |
433. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem4 |  | NA | NA | NA | 100% |
434. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem5 |  | NA | NA | NA | 100% |
435. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem6 |  | NA | NA | NA | 100% |
436. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem7 |  | NA | NA | NA | 100% |
437. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem8 |  | NA | NA | NA | 100% |
438. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem9 |  | NA | NA | NA | 100% |
439. . . . . . . . . . . . . . . . InputValueCalc | 6 | 50% |
| NA | NA | NA |
440. . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/InputValueCalc | 5 | 50% |
| NA | NA | NA |
441. . . . . . . . . . . . . . . . . . . . . . SF: Default | 1 | 50% |
| NA | NA | NA |
442. . . . . . . . . . . . . . . . . . . . . . SF: Update | 2 | 25% |
| NA | NA | NA |
443. . . . . . . . . . . . . . . . MaxValue_sort | 9 | 31% |
| NA | NA | NA |
444. . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/MaxValue_sort | 8 | 31% |
| NA | NA | NA |
445. . . . . . . . . . . . . . . . . . . . . . SF: sort | 8 | 31% |
| NA | NA | NA |
446. . . . . . . . . . . . . . . . OverWrite | 2 | 50% |
| NA | NA | 100% |
447. . . . . . . . . . CellVolt_SelfCheck | 2 | 50% |
| 50% |
| 0% |
| 100% |
448. . . . . . . . . . . . . OverWrite | 2 | 50% |
| NA | NA | 100% |
449. . . . . . . . . . MaxMinSum_CellVolt_Get | 83 | 57% |
| 50% |
| 0% |
| 100% |
450. . . . . . . . . . . . . CellVoltMax_SignalFilt | 25 | 52% |
| NA | NA | 100% |
451. . . . . . . . . . . . . . . . 1D_Config_Word | 11 | 9% |
| NA | NA | 100% |
452. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem |  | NA | NA | NA | 100% |
453. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem1 |  | NA | NA | NA | 100% |
454. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem2 |  | NA | NA | NA | 100% |
455. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem3 |  | NA | NA | NA | 100% |
456. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem4 |  | NA | NA | NA | 100% |
457. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem5 |  | NA | NA | NA | 100% |
458. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem6 |  | NA | NA | NA | 100% |
459. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem7 |  | NA | NA | NA | 100% |
460. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem8 |  | NA | NA | NA | 100% |
461. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem9 |  | NA | NA | NA | 100% |
462. . . . . . . . . . . . . . . . InputValueCalc | 4 | 60% |
| NA | NA | NA |
463. . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/InputValueCalc | 3 | 60% |
| NA | NA | NA |
464. . . . . . . . . . . . . . . . . . . . . . SF: VldValueFilter | 3 | 60% |
| NA | NA | NA |
465. . . . . . . . . . . . . . . . MaxValue_sort | 6 | 90% |
| NA | NA | NA |
466. . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/MaxValue_sort | 5 | 90% |
| NA | NA | NA |
467. . . . . . . . . . . . . . . . . . . . . . SF: sort | 5 | 90% |
| NA | NA | NA |
468. . . . . . . . . . . . . . . . ValueCalc |  | NA | NA | NA | 100% |
469. . . . . . . . . . . . . . . . ValueIndexCalc | 4 | 60% |
| NA | NA | 100% |
470. . . . . . . . . . . . . . . . . . . InputValueCalc1 | 4 | 60% |
| NA | NA | NA |
471. . . . . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/ValueIndexCalc/InputValueCalc1 | 3 | 60% |
| NA | NA | NA |
472. . . . . . . . . . . . . . . . . . . . . . . . . SF: VldValueFilter | 3 | 60% |
| NA | NA | NA |
473. . . . . . . . . . . . . CellVoltMin_SignalFilt | 25 | 52% |
| NA | NA | 100% |
474. . . . . . . . . . . . . . . . 1D_Config_Word | 11 | 9% |
| NA | NA | 100% |
475. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem |  | NA | NA | NA | 100% |
476. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem1 |  | NA | NA | NA | 100% |
477. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem2 |  | NA | NA | NA | 100% |
478. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem3 |  | NA | NA | NA | 100% |
479. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem4 |  | NA | NA | NA | 100% |
480. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem5 |  | NA | NA | NA | 100% |
481. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem6 |  | NA | NA | NA | 100% |
482. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem7 |  | NA | NA | NA | 100% |
483. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem8 |  | NA | NA | NA | 100% |
484. . . . . . . . . . . . . . . . . . . Switch Case Action Subsystem9 |  | NA | NA | NA | 100% |
485. . . . . . . . . . . . . . . . InputValueCalc | 4 | 60% |
| NA | NA | NA |
486. . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/InputValueCalc | 3 | 60% |
| NA | NA | NA |
487. . . . . . . . . . . . . . . . . . . . . . SF: VldValueFilter | 3 | 60% |
| NA | NA | NA |
488. . . . . . . . . . . . . . . . MinValue_sort | 6 | 90% |
| NA | NA | NA |
489. . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/MinValue_sort | 5 | 90% |
| NA | NA | NA |
490. . . . . . . . . . . . . . . . . . . . . . SF: sort | 5 | 90% |
| NA | NA | NA |
491. . . . . . . . . . . . . . . . ValueCalc |  | NA | NA | NA | 100% |
492. . . . . . . . . . . . . . . . ValueIndexCalc | 4 | 60% |
| NA | NA | 100% |
493. . . . . . . . . . . . . . . . . . . InputValueCalc1 | 4 | 60% |
| NA | NA | NA |
494. . . . . . . . . . . . . . . . . . . . . . SF: CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/ValueIndexCalc/InputValueCalc1 | 3 | 60% |
| NA | NA | NA |
495. . . . . . . . . . . . . . . . . . . . . . . . . SF: VldValueFilter | 3 | 60% |
| NA | NA | NA |
496. . . . . . . . . . . . . MaxMin_CellVolt_Get_Sys | 14 | 70% |
| 50% |
| 0% |
| 100% |
497. . . . . . . . . . . . . . . . MaxMin_CellVolt_ForIterator | 11 | 75% |
| 50% |
| 0% |
| 100% |
498. . . . . . . . . . . . . . . . . . . MaxCellVoltNumb_ForIterator | 4 | 67% |
| 50% |
| 0% |
| 100% |
499. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC1 | 2 | 100% |
| NA | NA | 100% |
500. . . . . . . . . . . . . . . . . . . MinCellVoltNumb_ForIterator | 6 | 75% |
| 50% |
| 0% |
| 100% |
501. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC1 | 2 | 100% |
| NA | NA | 100% |
502. . . . . . . . . . . . . . . . . . . . . . Unit Delay External IC2 | 2 | 100% |
| NA | NA | 100% |
503. . . . . . . . . . . . . OverWrite | 2 | 50% |
| NA | NA | 100% |
504. . . . . . . . . . . . . OverWrite1 | 2 | 50% |
| NA | NA | 100% |
505. . . . . . . . . . . . . OverWrite2 | 2 | 50% |
| NA | NA | 100% |
506. . . . . . . . . . . . . OverWrite3 | 2 | 50% |
| NA | NA | 100% |
507. . . . . . . . . . . . . SumCellVoltVld | 4 | 67% |
| 50% |
| 0% |
| 100% |
508. . . . . . . . . . . . . . . . CellVoltVld | 1 | 100% |
| 70% |
| 0% |
| 100% |
509. . . . . . . . . . . . . . . . OverWrite | 2 | 50% |
| NA | NA | 100% |
510. . . . . . . . . . . . . Sum_CellVolt_Get_Sys | 7 | 63% |
| NA | NA | 100% |
511. . . . . . . . . . . . . . . . SumCellVot_Calculation | 4 | 50% |
| NA | NA | 100% |
512. . . . . . . . . . . . . . . . . . . OverWrite1 | 2 | 50% |
| NA | NA | 100% |
513. . . . . . . . . . . . . . . . . . . OverWrite2 | 2 | 50% |
| NA | NA | 100% |
514. . . . . . . . . . . . . . . . Sum_CellVolt_ForIterator | 1 | 100% |
| NA | NA | 100% |
515. . . . . . . . . . StackVolt | 140 | 60% |
| 57% |
| NA | 100% |
516. . . . . . . . . . . . . BMSDelay | 49 | 50% |
| 50% |
| NA | 100% |
517. . . . . . . . . . . . . . . . Unit Delay Resettable | 32 | 50% |
| NA | NA | 100% |
518. . . . . . . . . . . . . BMSDelay1 | 49 | 83% |
| 75% |
| NA | 100% |
519. . . . . . . . . . . . . . . . Unit Delay Resettable | 32 | 75% |
| NA | NA | 100% |
520. . . . . . . . . . . . . CDP_GaCDP_StackVoltHighFlt_flg | 2 | 50% |
| NA | NA | 100% |
521. . . . . . . . . . . . . CDP_GaCDP_StackVoltLowFlt_flg | 2 | 50% |
| NA | NA | 100% |
522. . . . . . . . . . . . . OverWrite | 2 | 50% |
| NA | NA | 100% |
523. . . . . . . . . . . . . OverWrite2 | 2 | 50% |
| NA | NA | 100% |
524. . . . . . . . . . . . . SumModellVot_Calc | 2 | 50% |
| NA | NA | 100% |
525. . . . . . . . . . . . . . . . OverWrite2 | 2 | 50% |
| NA | NA | 100% |
526. . . . . . . . . . . . . Sum_ModelVolt_ForIterator | 1 | 100% |
| NA | NA | 100% |

## Details

### 1. Model "CDP_UT"

Child Systems: | CellDataPrc_20ms_sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 960
Condition | NA | 46% (3541/7686) condition outcomes
Decision | NA | 46% (655/1431) decision outcomes
MCDC | NA | 0% (0/2446) conditions reversed the outcome
Execution | NA | 87% (1305/1493) objective outcomes

### 2. SubSystem block "CellDataPrc_20ms_sys"

Justify or Exclude
Parent: | /CDP_UT
Child Systems: | VoltDataPrc_20ms_sys, BalDiag_20ms_sys, CellVoltFltDet, ChrgWkUpDet, TempDataPrc_20ms_sys, TempFltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 955
Condition | NA | 46% (3541/7686) condition outcomes
Decision | NA | 46% (655/1431) decision outcomes
MCDC | NA | 0% (0/2446) conditions reversed the outcome
Execution | NA | 87% (1305/1493) objective outcomes

#### Full Coverage

Model Object | Metric
SignalConversion block "Signal Conversion" | Execution
SignalConversion block "Signal Conversion1" | Execution
SignalConversion block "Signal Conversion10" | Execution
SignalConversion block "Signal Conversion11" | Execution
SignalConversion block "Signal Conversion12" | Execution
SignalConversion block "Signal Conversion13" | Execution
SignalConversion block "Signal Conversion14" | Execution
SignalConversion block "Signal Conversion15" | Execution
SignalConversion block "Signal Conversion16" | Execution
SignalConversion block "Signal Conversion2" | Execution
SignalConversion block "Signal Conversion3" | Execution
SignalConversion block "Signal Conversion4" | Execution
SignalConversion block "Signal Conversion5" | Execution
SignalConversion block "Signal Conversion6" | Execution
SignalConversion block "Signal Conversion7" | Execution
SignalConversion block "Signal Conversion8" | Execution
SignalConversion block "Signal Conversion9" | Execution

### 3. SubSystem block "BalDiag_20ms_sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys
Child Systems: | CDP_GaCDP_CellBalcOpLine_flg, CDP_GaCDP_CellBalcShrt_flg, CDP_GaCDP_CellBalc_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Decision | NA | 50% (3/6) decision outcomes
Execution | NA | 100% (9/9) objective outcomes

### 4. SubSystem block "CDP_GaCDP_CellBalcOpLine_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/BalDiag_20ms_sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/BalDiag_20ms_sys/CDP_GaCDP_CellBalcOpLine_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 5. SubSystem block "CDP_GaCDP_CellBalcShrt_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/BalDiag_20ms_sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/BalDiag_20ms_sys/CDP_GaCDP_CellBalcShrt_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 6. SubSystem block "CDP_GaCDP_CellBalc_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/BalDiag_20ms_sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/BalDiag_20ms_sys/CDP_GaCDP_CellBalc_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 7. SubSystem block "CellVoltFltDet"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys
Child Systems: | CellFltLevel_Switch, DiffCellVoltDet, MaxCellVoltDet, MinCellVoltDet, RngCellVoltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 89
Condition | NA | 50% (128/256) condition outcomes
Decision | NA | 20% (18/90) decision outcomes
MCDC | NA | 0% (0/56) conditions reversed the outcome
Execution | NA | 81% (236/290) objective outcomes

### 8. SubSystem block "CellFltLevel_Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet
Child Systems: | CDP_2D_Config_Word, CDP_2D_Config_Word1, CDP_2D_Config_Word2, CDP_2D_Config_Word3, CDP_2D_Config_Word4, CDP_2D_Config_Word5
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 66
Decision | NA | 9% (6/66) decision outcomes
Execution | NA | 26% (19/73) objective outcomes

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution

### 9. SubSystem block "CDP_2D_Config_Word"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch
Child Systems: | Switch Case Action Subsystem, Switch Case Action Subsystem1, Switch Case Action Subsystem2, Switch Case Action Subsystem3, Switch Case Action Subsystem4, Switch Case Action Subsystem5, Switch Case Action Subsystem6, Switch Case Action Subsystem7, Switch Case Action Subsystem8, Switch Case Action Subsystem9
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 11
Decision | NA | 9% (1/11) decision outcomes
Execution | NA | 25% (3/12) objective outcomes

#### SwitchCase block "Switch Case"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 10
Decision | 9% (1/11) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
truncated input | 9%
= Enum_UDSCapSel_Default | 1001/1001
= Enum_UDSCapSel_CATL153Ah | 0/1001
= Enum_UDSCapSel_CATL180Ah | 0/1001
= Enum_UDSCapSel_CATL177Ah | 0/1001
= Enum_UDSCapSel_CATL203Ah | 0/1001
= Enum_UDSCapSel_CATL51Ah | 0/1001
= Enum_UDSCapSel_CATL132Ah | 0/1001
= Enum_UDSCapSel_XWD75Ah | 0/1001
= Enum_UDSCapSel_TFE177Ah | 0/1001
= Enum_UDSCapSel_CATLCTP248Ah | 0/1001
= implicit-default | 0/1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution

### 10. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Lookup_n-D block "1-D_Lookup_Table" | Execution

### 11. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word/Switch Case Action Subsystem1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 12. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word/Switch Case Action Subsystem2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 13. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word/Switch Case Action Subsystem3
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 14. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word/Switch Case Action Subsystem4
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 15. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word/Switch Case Action Subsystem5
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 16. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word/Switch Case Action Subsystem6
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 17. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word/Switch Case Action Subsystem7
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 18. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word/Switch Case Action Subsystem8
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 19. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word/Switch Case Action Subsystem9
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 20. SubSystem block "CDP_2D_Config_Word1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch
Child Systems: | Switch Case Action Subsystem, Switch Case Action Subsystem1, Switch Case Action Subsystem2, Switch Case Action Subsystem3, Switch Case Action Subsystem4, Switch Case Action Subsystem5, Switch Case Action Subsystem6, Switch Case Action Subsystem7, Switch Case Action Subsystem8, Switch Case Action Subsystem9
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 11
Decision | NA | 9% (1/11) decision outcomes
Execution | NA | 25% (3/12) objective outcomes

#### SwitchCase block "Switch Case"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 10
Decision | 9% (1/11) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
truncated input | 9%
= Enum_UDSCapSel_Default | 1001/1001
= Enum_UDSCapSel_CATL153Ah | 0/1001
= Enum_UDSCapSel_CATL180Ah | 0/1001
= Enum_UDSCapSel_CATL177Ah | 0/1001
= Enum_UDSCapSel_CATL203Ah | 0/1001
= Enum_UDSCapSel_CATL51Ah | 0/1001
= Enum_UDSCapSel_CATL132Ah | 0/1001
= Enum_UDSCapSel_XWD75Ah | 0/1001
= Enum_UDSCapSel_TFE177Ah | 0/1001
= Enum_UDSCapSel_CATLCTP248Ah | 0/1001
= implicit-default | 0/1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution

### 21. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Lookup_n-D block "1-D_Lookup_Table" | Execution

### 22. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word1/Switch Case Action Subsystem1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 23. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word1/Switch Case Action Subsystem2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 24. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word1/Switch Case Action Subsystem3
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 25. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word1/Switch Case Action Subsystem4
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 26. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word1/Switch Case Action Subsystem5
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 27. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word1/Switch Case Action Subsystem6
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 28. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word1/Switch Case Action Subsystem7
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 29. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word1/Switch Case Action Subsystem8
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 30. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word1/Switch Case Action Subsystem9
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 31. SubSystem block "CDP_2D_Config_Word2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch
Child Systems: | Switch Case Action Subsystem, Switch Case Action Subsystem1, Switch Case Action Subsystem2, Switch Case Action Subsystem3, Switch Case Action Subsystem4, Switch Case Action Subsystem5, Switch Case Action Subsystem6, Switch Case Action Subsystem7, Switch Case Action Subsystem8, Switch Case Action Subsystem9
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 11
Decision | NA | 9% (1/11) decision outcomes
Execution | NA | 25% (3/12) objective outcomes

#### SwitchCase block "Switch Case"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 10
Decision | 9% (1/11) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
truncated input | 9%
= Enum_UDSCapSel_Default | 1001/1001
= Enum_UDSCapSel_CATL153Ah | 0/1001
= Enum_UDSCapSel_CATL180Ah | 0/1001
= Enum_UDSCapSel_CATL177Ah | 0/1001
= Enum_UDSCapSel_CATL203Ah | 0/1001
= Enum_UDSCapSel_CATL51Ah | 0/1001
= Enum_UDSCapSel_CATL132Ah | 0/1001
= Enum_UDSCapSel_XWD75Ah | 0/1001
= Enum_UDSCapSel_TFE177Ah | 0/1001
= Enum_UDSCapSel_CATLCTP248Ah | 0/1001
= implicit-default | 0/1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution

### 32. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Lookup_n-D block "1-D_Lookup_Table" | Execution

### 33. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word2/Switch Case Action Subsystem1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 34. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word2/Switch Case Action Subsystem2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 35. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word2/Switch Case Action Subsystem3
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 36. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word2/Switch Case Action Subsystem4
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 37. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word2/Switch Case Action Subsystem5
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 38. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word2/Switch Case Action Subsystem6
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 39. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word2/Switch Case Action Subsystem7
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 40. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word2/Switch Case Action Subsystem8
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 41. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word2/Switch Case Action Subsystem9
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 42. SubSystem block "CDP_2D_Config_Word3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch
Child Systems: | Switch Case Action Subsystem, Switch Case Action Subsystem1, Switch Case Action Subsystem2, Switch Case Action Subsystem3, Switch Case Action Subsystem4, Switch Case Action Subsystem5, Switch Case Action Subsystem6, Switch Case Action Subsystem7, Switch Case Action Subsystem8, Switch Case Action Subsystem9
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 11
Decision | NA | 9% (1/11) decision outcomes
Execution | NA | 25% (3/12) objective outcomes

#### SwitchCase block "Switch Case"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word3
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 10
Decision | 9% (1/11) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
truncated input | 9%
= Enum_UDSCapSel_Default | 1001/1001
= Enum_UDSCapSel_CATL153Ah | 0/1001
= Enum_UDSCapSel_CATL180Ah | 0/1001
= Enum_UDSCapSel_CATL177Ah | 0/1001
= Enum_UDSCapSel_CATL203Ah | 0/1001
= Enum_UDSCapSel_CATL51Ah | 0/1001
= Enum_UDSCapSel_CATL132Ah | 0/1001
= Enum_UDSCapSel_XWD75Ah | 0/1001
= Enum_UDSCapSel_TFE177Ah | 0/1001
= Enum_UDSCapSel_CATLCTP248Ah | 0/1001
= implicit-default | 0/1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution

### 43. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word3
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Lookup_n-D block "1-D_Lookup_Table" | Execution

### 44. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word3
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word3/Switch Case Action Subsystem1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 45. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word3
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word3/Switch Case Action Subsystem2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 46. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word3
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word3/Switch Case Action Subsystem3
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 47. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word3
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word3/Switch Case Action Subsystem4
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 48. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word3
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word3/Switch Case Action Subsystem5
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 49. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word3
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word3/Switch Case Action Subsystem6
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 50. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word3
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word3/Switch Case Action Subsystem7
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 51. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word3
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word3/Switch Case Action Subsystem8
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 52. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word3
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word3/Switch Case Action Subsystem9
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 53. SubSystem block "CDP_2D_Config_Word4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch
Child Systems: | Switch Case Action Subsystem, Switch Case Action Subsystem1, Switch Case Action Subsystem2, Switch Case Action Subsystem3, Switch Case Action Subsystem4, Switch Case Action Subsystem5, Switch Case Action Subsystem6, Switch Case Action Subsystem7, Switch Case Action Subsystem8, Switch Case Action Subsystem9
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 11
Decision | NA | 9% (1/11) decision outcomes
Execution | NA | 25% (3/12) objective outcomes

#### SwitchCase block "Switch Case"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word4
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 10
Decision | 9% (1/11) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
truncated input | 9%
= Enum_UDSCapSel_Default | 1001/1001
= Enum_UDSCapSel_CATL153Ah | 0/1001
= Enum_UDSCapSel_CATL180Ah | 0/1001
= Enum_UDSCapSel_CATL177Ah | 0/1001
= Enum_UDSCapSel_CATL203Ah | 0/1001
= Enum_UDSCapSel_CATL51Ah | 0/1001
= Enum_UDSCapSel_CATL132Ah | 0/1001
= Enum_UDSCapSel_XWD75Ah | 0/1001
= Enum_UDSCapSel_TFE177Ah | 0/1001
= Enum_UDSCapSel_CATLCTP248Ah | 0/1001
= implicit-default | 0/1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution

### 54. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word4
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Lookup_n-D block "1-D_Lookup_Table" | Execution

### 55. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word4
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word4/Switch Case Action Subsystem1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 56. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word4
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word4/Switch Case Action Subsystem2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 57. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word4
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word4/Switch Case Action Subsystem3
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 58. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word4
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word4/Switch Case Action Subsystem4
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 59. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word4
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word4/Switch Case Action Subsystem5
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 60. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word4
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word4/Switch Case Action Subsystem6
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 61. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word4
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word4/Switch Case Action Subsystem7
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 62. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word4
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word4/Switch Case Action Subsystem8
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 63. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word4
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word4/Switch Case Action Subsystem9
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 64. SubSystem block "CDP_2D_Config_Word5"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch
Child Systems: | Switch Case Action Subsystem, Switch Case Action Subsystem1, Switch Case Action Subsystem2, Switch Case Action Subsystem3, Switch Case Action Subsystem4, Switch Case Action Subsystem5, Switch Case Action Subsystem6, Switch Case Action Subsystem7, Switch Case Action Subsystem8, Switch Case Action Subsystem9
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 11
Decision | NA | 9% (1/11) decision outcomes
Execution | NA | 25% (3/12) objective outcomes

#### SwitchCase block "Switch Case"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word5
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 10
Decision | 9% (1/11) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
truncated input | 9%
= Enum_UDSCapSel_Default | 1001/1001
= Enum_UDSCapSel_CATL153Ah | 0/1001
= Enum_UDSCapSel_CATL180Ah | 0/1001
= Enum_UDSCapSel_CATL177Ah | 0/1001
= Enum_UDSCapSel_CATL203Ah | 0/1001
= Enum_UDSCapSel_CATL51Ah | 0/1001
= Enum_UDSCapSel_CATL132Ah | 0/1001
= Enum_UDSCapSel_XWD75Ah | 0/1001
= Enum_UDSCapSel_TFE177Ah | 0/1001
= Enum_UDSCapSel_CATLCTP248Ah | 0/1001
= implicit-default | 0/1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution

### 65. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word5
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Lookup_n-D block "1-D_Lookup_Table" | Execution

### 66. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word5
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word5/Switch Case Action Subsystem1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 67. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word5
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word5/Switch Case Action Subsystem2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 68. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word5
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word5/Switch Case Action Subsystem3
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 69. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word5
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word5/Switch Case Action Subsystem4
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 70. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word5
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word5/Switch Case Action Subsystem5
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 71. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word5
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word5/Switch Case Action Subsystem6
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 72. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word5
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word5/Switch Case Action Subsystem7
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 73. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word5
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word5/Switch Case Action Subsystem8
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 74. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word5
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 0% (0/1) objective outcomes

#### Lookup_n-D block "1-D_Lookup_Table"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/CellFltLevel_Switch/CDP_2D_Config_Word5/Switch Case Action Subsystem9
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 75. SubSystem block "DiffCellVoltDet"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet
Child Systems: | DiffCellVolt_SateSwitch_Sys, DiffVoltCheck_Condition
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 7
Condition | NA | 50% (50/100) condition outcomes
Decision | NA | 50% (4/8) decision outcomes
MCDC | NA | 0% (0/22) conditions reversed the outcome
Execution | NA | 100% (79/79) objective outcomes

### 76. SubSystem block "DiffCellVolt_SateSwitch_Sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet
Child Systems: | CellVoltDiffFltLv1Det, CellVoltDiffFltLv2Det, CellVoltDiffFltLv3Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 50% (33/66) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
MCDC | NA | 0% (0/14) conditions reversed the outcome
Execution | NA | 100% (58/58) objective outcomes

#### Full Coverage

Model Object | Metric
Sum block "Add" | Execution

### 77. SubSystem block "CellVoltDiffFltLv1Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (12/24) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/5) conditions reversed the outcome
Execution | NA | 100% (21/21) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (3/6) condition outcomes
MCDC | 0% (0/5) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
input port 3 | 1001 | 0
MC/DC analysis (combinations in parentheses did not occur) Includes 3 blocks
Decision/Condition | True Out | False Out
((C1 && C2) && C3) && (C4 && C5) |
C1 (Logical Operator1 In1) | (TTTTT) | (FTTTT)
C2 (Logical Operator1 In2) | (TTTTT) | (TFTTT)
C3 (Logical Operator In2) | (TTTTT) | (TTFTT)
C4 (Logical Operator2 In1) | (TTTTT) | (TTTFT)
C5 (Logical Operator2 In2) | (TTTTT) | (TTTTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### Logic block "Logical Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 1001 | 0

#### RelationalOperator block "Comparison"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 > input2 | 1001 | 0

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### Full Coverage

Model Object | Metric
Sum block "Add" | Execution
Sum block "Add1" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution
Constant block "Constant5" | Execution
Constant block "Constant6" | Execution
Constant block "Constant7" | Execution
Constant block "Constant8" | Execution

### 78. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv1Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv1Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 79. SubSystem block "CellVoltDiffFltLv2Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (12/24) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/5) conditions reversed the outcome
Execution | NA | 100% (21/21) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (3/6) condition outcomes
MCDC | 0% (0/5) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
input port 3 | 1001 | 0
MC/DC analysis (combinations in parentheses did not occur) Includes 3 blocks
Decision/Condition | True Out | False Out
((C1 && C2) && C3) && (C4 && C5) |
C1 (Logical Operator1 In1) | (TTTTT) | (FTTTT)
C2 (Logical Operator1 In2) | (TTTTT) | (TFTTT)
C3 (Logical Operator In2) | (TTTTT) | (TTFTT)
C4 (Logical Operator2 In1) | (TTTTT) | (TTTFT)
C5 (Logical Operator2 In2) | (TTTTT) | (TTTTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### Logic block "Logical Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 1001 | 0

#### RelationalOperator block "Comparison"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 > input2 | 1001 | 0

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### Full Coverage

Model Object | Metric
Sum block "Add" | Execution
Sum block "Add1" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution
Constant block "Constant5" | Execution
Constant block "Constant6" | Execution
Constant block "Constant7" | Execution
Constant block "Constant8" | Execution

### 80. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv2Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv2Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 81. SubSystem block "CellVoltDiffFltLv3Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (9/18) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/4) conditions reversed the outcome
Execution | NA | 100% (15/15) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (3/6) condition outcomes
MCDC | 0% (0/4) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
input port 3 | 1001 | 0
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && (C3 && C4) |
C1 (Logical Operator In1) | (TTTT) | (FTTT)
C2 (Logical Operator In2) | (TTTT) | (TFTT)
C3 (Logical Operator1 In1) | (TTTT) | (TTFT)
C4 (Logical Operator1 In2) | (TTTT) | (TTTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 1001 | 0

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### Full Coverage

Model Object | Metric
Sum block "Add" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution
Constant block "Constant5" | Execution

### 82. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv3Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffCellVolt_SateSwitch_Sys/CellVoltDiffFltLv3Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 83. SubSystem block "DiffVoltCheck_Condition"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 1
Condition | NA | 50% (17/34) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/8) conditions reversed the outcome
Execution | NA | 100% (21/21) objective outcomes

#### Abs block "Abs"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
input < 0 | 50%
false | 1001/1001
true | 0/1001

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (8/16) condition outcomes
MCDC | 0% (0/8) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001
input port 3 | 1001 | 0
input port 4 | 1001 | 0
input port 5 | 1001 | 0
input port 6 | 1001 | 0
input port 7 | 0 | 1001
input port 8 | 1001 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TTTTTTTT) | (FTTTTTTT)
input port 2 | (TTTTTTTT) | (TFTTTTTT)
input port 3 | (TTTTTTTT) | (TTFTTTTT)
input port 4 | (TTTTTTTT) | (TTTFTTTT)
input port 5 | (TTTTTTTT) | (TTTTFTTT)
input port 6 | (TTTTTTTT) | (TTTTTFTT)
input port 7 | (TTTTTTTT) | (TTTTTTFT)
input port 8 | (TTTTTTTT) | (TTTTTTTF)

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 2 | 0

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 1001 | 0

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 1001 | 0

#### RelationalOperator block "Relational Operator4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 1001 | 0

#### RelationalOperator block "Relational Operator5"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator6"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator7"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 1001 | 0

#### RelationalOperator block "Relational Operator8"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/DiffCellVoltDet/DiffVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant10" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution
Constant block "Constant5" | Execution
Constant block "Constant6" | Execution
Constant block "Constant7" | Execution
Constant block "Constant8" | Execution

### 84. SubSystem block "MaxCellVoltDet"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet
Child Systems: | CellVoltHiFltDet, MaxVoltCheck_Condition
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 50% (28/56) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
MCDC | NA | 0% (0/12) conditions reversed the outcome
Execution | NA | 100% (52/52) objective outcomes

### 85. SubSystem block "CellVoltHiFltDet"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet
Child Systems: | CellVoltHiFltLv1Det, CellVoltHiFltLv2Det, CellVoltHiFltLv3Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 50% (21/42) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
MCDC | NA | 0% (0/9) conditions reversed the outcome
Execution | NA | 100% (41/41) objective outcomes

### 86. SubSystem block "CellVoltHiFltLv1Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (7/14) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (14/14) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Comparison"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 > input2 | 1001 | 0

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add1" | Execution
Sum block "Add3" | Execution
Constant block "Constant1" | Execution
Constant block "Constant13" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution

### 87. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv1Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv1Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 88. SubSystem block "CellVoltHiFltLv2Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (7/14) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (14/14) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Comparison"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 > input2 | 1001 | 0

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add1" | Execution
Sum block "Add3" | Execution
Constant block "Constant1" | Execution
Constant block "Constant13" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution

### 89. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv2Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv2Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 90. SubSystem block "CellVoltHiFltLv3Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (7/14) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (13/13) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Comparison"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 > input2 | 1001 | 0

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add3" | Execution
Constant block "Constant1" | Execution
Constant block "Constant13" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution

### 91. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv3Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/CellVoltHiFltDet/CellVoltHiFltLv3Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 92. SubSystem block "MaxVoltCheck_Condition"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Condition | NA | 50% (7/14) condition outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (11/11) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/MaxVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (3/6) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 1001 | 0
input port 3 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TTT) | (FTT)
input port 2 | (TTT) | (TFT)
input port 3 | (TTT) | TTF

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/MaxVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/MaxVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 2 | 0

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/MaxVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MaxCellVoltDet/MaxVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion1" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution

### 93. SubSystem block "MinCellVoltDet"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet
Child Systems: | CellVoltLowFltDet, MinVoltCheck_Condition
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 50% (28/56) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
MCDC | NA | 0% (0/12) conditions reversed the outcome
Execution | NA | 100% (48/48) objective outcomes

### 94. SubSystem block "CellVoltLowFltDet"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet
Child Systems: | CellVoltLowFltLv1Det, CellVoltLowFltLv2Det, CellVoltLowFltLv3Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 50% (21/42) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
MCDC | NA | 0% (0/9) conditions reversed the outcome
Execution | NA | 100% (37/37) objective outcomes

### 95. SubSystem block "CellVoltLowFltLv1Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (7/14) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (12/12) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | TTF

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 1001 | 0

#### RelationalOperator block "Comparison"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 > input2 | 0 | 1001

#### RelationalOperator block "Comparison1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 1001 | 0

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution

### 96. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv1Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv1Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 97. SubSystem block "CellVoltLowFltLv2Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (7/14) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (12/12) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | TTF

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 1001 | 0

#### RelationalOperator block "Comparison"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 > input2 | 0 | 1001

#### RelationalOperator block "Comparison1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 1001 | 0

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution

### 98. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv2Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv2Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 99. SubSystem block "CellVoltLowFltLv3Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (7/14) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (13/13) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | TTF

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 1001 | 0

#### RelationalOperator block "Comparison"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 > input2 | 0 | 1001

#### RelationalOperator block "Comparison1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 1001 | 0

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution

### 100. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv3Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/CellVoltLowFltDet/CellVoltLowFltLv3Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 101. SubSystem block "MinVoltCheck_Condition"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Condition | NA | 50% (7/14) condition outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (11/11) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/MinVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (3/6) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 1001 | 0
input port 3 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TTT) | (FTT)
input port 2 | (TTT) | (TFT)
input port 3 | (TTT) | TTF

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/MinVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/MinVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 2 | 0

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/MinVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/MinCellVoltDet/MinVoltCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion1" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution

### 102. SubSystem block "RngCellVoltDet"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet
Child Systems: | CellVoltRngHiCheck_Condition, CellVoltRngHiFltDet, CellVoltRngLowCheck_Condition, CellVoltRngLowFltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 4
Condition | NA | 50% (22/44) condition outcomes
Decision | NA | 50% (2/4) decision outcomes
MCDC | NA | 0% (0/10) conditions reversed the outcome
Execution | NA | 100% (38/38) objective outcomes

### 103. SubSystem block "CellVoltRngHiCheck_Condition"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Condition | NA | 50% (7/14) condition outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (11/11) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet/CellVoltRngHiCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (3/6) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 1001 | 0
input port 3 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TTT) | (FTT)
input port 2 | (TTT) | (TFT)
input port 3 | (TTT) | TTF

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet/CellVoltRngHiCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet/CellVoltRngHiCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 2 | 0

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet/CellVoltRngHiCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet/CellVoltRngHiCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion1" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution

### 104. SubSystem block "CellVoltRngHiFltDet"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (4/8) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 100% (8/8) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet/CellVoltRngHiFltDet
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TT) | (FT)
input port 2 | (TT) | (TF)

#### RelationalOperator block "Comparison1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet/CellVoltRngHiFltDet
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet/CellVoltRngHiFltDet
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Constant block "Constant2" | Execution
Constant block "Constant4" | Execution

### 105. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet/CellVoltRngHiFltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet/CellVoltRngHiFltDet/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 106. SubSystem block "CellVoltRngLowCheck_Condition"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Condition | NA | 50% (7/14) condition outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (11/11) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet/CellVoltRngLowCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (3/6) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 1001 | 0
input port 3 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TTT) | (FTT)
input port 2 | (TTT) | (TFT)
input port 3 | (TTT) | TTF

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet/CellVoltRngLowCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet/CellVoltRngLowCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 2 | 0

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet/CellVoltRngLowCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet/CellVoltRngLowCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion1" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution

### 107. SubSystem block "CellVoltRngLowFltDet"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (4/8) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 100% (8/8) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet/CellVoltRngLowFltDet
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TT) | (FT)
input port 2 | (TT) | TF

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet/CellVoltRngLowFltDet
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 1001 | 0

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet/CellVoltRngLowFltDet
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Constant block "Constant2" | Execution
Constant block "Constant4" | Execution

### 108. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet/CellVoltRngLowFltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/CellVoltFltDet/RngCellVoltDet/CellVoltRngLowFltDet/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 109. SubSystem block "ChrgWkUpDet"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Condition | NA | 50% (4/8) condition outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 100% (6/6) objective outcomes

#### Logic block "Logical1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/ChrgWkUpDet
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TF) | FF
input port 2 | (FT) | FF

#### RelationalOperator block "Comparison1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/ChrgWkUpDet
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Comparison2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/ChrgWkUpDet
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution

### 110. SubSystem block "TempDataPrc_20ms_sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys
Child Systems: | AFETempVld_Output, AFETemp_Flt, AFETemp_Output, BusbarTempVld_Output, BusbarTemp_Output, CDP_GaCDP_ModuleTempHighFlt_flg, CMUPCBTemp_Flt, CMUTempVld_Output, CMUTemp_Output, CellTemp_SelfCheck, MaxMin_AFETemp_Get, MaxMin_BusbarTemp_Get, MaxMin_CMUTemp_Get, MaxMin_CellTemp_Get, NTCTempVld_Output, NTCTemp_Output
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 440
Condition | NA | 40% (1344/3328) condition outcomes
Decision | NA | 41% (270/658) decision outcomes
MCDC | NA | 0% (0/1152) conditions reversed the outcome
Execution | NA | 73% (363/497) objective outcomes

### 111. SubSystem block "AFETempVld_Output"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys
Child Systems: | CDP_GaCDP_CMUPCBTempVld_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (18/36) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/16) conditions reversed the outcome
Execution | NA | 100% (10/10) objective outcomes

#### Logic block "Logical Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/AFETempVld_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (9/18) condition outcomes
MCDC | 0% (0/16) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 0 | 1001
input port1(2) | 0 | 1001
input port1(3) | 0 | 1001
input port1(4) | 0 | 1001
input port1(5) | 0 | 1001
input port1(6) | 0 | 1001
input port1(7) | 0 | 1001
input port1(8) | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output(1) |
input port1(1) | (TF) | FF
input port 2 | (FT) | FF
expression for output(2) |
input port1(2) | (TF) | FF
input port 2 | (FT) | FF
expression for output(3) |
input port1(3) | (TF) | FF
input port 2 | (FT) | FF
expression for output(4) |
input port1(4) | (TF) | FF
input port 2 | (FT) | FF
expression for output(5) |
input port1(5) | (TF) | FF
input port 2 | (FT) | FF
expression for output(6) |
input port1(6) | (TF) | FF
input port 2 | (FT) | FF
expression for output(7) |
input port1(7) | (TF) | FF
input port 2 | (FT) | FF
expression for output(8) |
input port1(8) | (TF) | FF
input port 2 | (FT) | FF

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/AFETempVld_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/AFETempVld_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (8/16) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2(1) | 0 | 1001
input1 == input2(2) | 0 | 1001
input1 == input2(3) | 0 | 1001
input1 == input2(4) | 0 | 1001
input1 == input2(5) | 0 | 1001
input1 == input2(6) | 0 | 1001
input1 == input2(7) | 0 | 1001
input1 == input2(8) | 0 | 1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution
S-Function block "Bitwise Logical Operator" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution

### 112. SubSystem block "CDP_GaCDP_CMUPCBTempVld_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/AFETempVld_Output
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/AFETempVld_Output/CDP_GaCDP_CMUPCBTempVld_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 113. SubSystem block "AFETemp_Flt"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys
Child Systems: | CDP_GbCDP_CMUTempHighFlt_flg, Hysteresis
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 5
Condition | NA | 50% (2/4) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
Execution | NA | 100% (13/13) objective outcomes

#### Full Coverage

Model Object | Metric
Sum block "Sum1" | Execution
Constant block "Constant1" | Execution
Constant block "Constant3" | Execution

### 114. SubSystem block "CDP_GbCDP_CMUTempHighFlt_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/AFETemp_Flt
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/AFETemp_Flt/CDP_GbCDP_CMUTempHighFlt_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 115. SubSystem block "Hysteresis"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/AFETemp_Flt
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 3
Condition | NA | 50% (2/4) condition outcomes
Decision | NA | 50% (2/4) decision outcomes
Execution | NA | 100% (7/7) objective outcomes

#### Switch block "Switch1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/AFETemp_Flt/Hysteresis
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Switch block "Switch2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/AFETemp_Flt/Hysteresis
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001

#### RelationalOperator block "Greater Than"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/AFETemp_Flt/Hysteresis
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 > input2 | 0 | 1001

#### RelationalOperator block "Greater Than1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/AFETemp_Flt/Hysteresis
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 < input2 | 1001 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant Value" | Execution
Constant block "Constant Value1" | Execution
UnitDelay block "Unit Delay" | Execution

### 116. SubSystem block "AFETemp_Output"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys
Child Systems: | CDP_GaCDP_CMUPCBTemp_C
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 10
Condition | NA | 50% (18/36) condition outcomes
Decision | NA | 50% (9/18) decision outcomes
MCDC | NA | 0% (0/16) conditions reversed the outcome
Execution | NA | 100% (13/13) objective outcomes

#### Logic block "Logical Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/AFETemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (9/18) condition outcomes
MCDC | 0% (0/16) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 1001 | 0
input port1(2) | 1001 | 0
input port1(3) | 1001 | 0
input port1(4) | 1001 | 0
input port1(5) | 1001 | 0
input port1(6) | 1001 | 0
input port1(7) | 1001 | 0
input port1(8) | 1001 | 0
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output(1) |
input port1(1) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(2) |
input port1(2) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(3) |
input port1(3) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(4) |
input port1(4) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(5) |
input port1(5) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(6) |
input port1(6) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(7) |
input port1(7) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(8) |
input port1(8) | TF | (FF)
input port 2 | (FT) | (FF)

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/AFETemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 8
Decision | 50% (8/16) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input(1) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(2) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(3) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(4) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(5) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(6) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(7) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(8) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/AFETemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/AFETemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (8/16) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) ~= input2 | 1001 | 0
input1(2) ~= input2 | 1001 | 0
input1(3) ~= input2 | 1001 | 0
input1(4) ~= input2 | 1001 | 0
input1(5) ~= input2 | 1001 | 0
input1(6) ~= input2 | 1001 | 0
input1(7) ~= input2 | 1001 | 0
input1(8) ~= input2 | 1001 | 0

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution
DataTypeConversion block "Data Type Conversion1" | Execution
S-Function block "Bitwise Logical Operator" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
UnitDelay block "Unit Delay" | Execution

### 117. SubSystem block "CDP_GaCDP_CMUPCBTemp_C"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/AFETemp_Output
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/AFETemp_Output/CDP_GaCDP_CMUPCBTemp_C
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 118. SubSystem block "BusbarTempVld_Output"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys
Child Systems: | OverWrite4
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (98/196) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/96) conditions reversed the outcome
Execution | NA | 100% (10/10) objective outcomes

#### Logic block "Logical Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTempVld_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (49/98) condition outcomes
MCDC | 0% (0/96) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 1001 | 0
input port1(2) | 1001 | 0
input port1(3) | 1001 | 0
input port1(4) | 1001 | 0
input port1(5) | 1001 | 0
input port1(6) | 1001 | 0
input port1(7) | 1001 | 0
input port1(8) | 1001 | 0
input port1(9) | 1001 | 0
input port1(10) | 1001 | 0
input port1(11) | 1001 | 0
input port1(12) | 1001 | 0
input port1(13) | 1001 | 0
input port1(14) | 1001 | 0
input port1(15) | 1001 | 0
input port1(16) | 1001 | 0
input port1(17) | 1001 | 0
input port1(18) | 1001 | 0
input port1(19) | 1001 | 0
input port1(20) | 1001 | 0
input port1(21) | 1001 | 0
input port1(22) | 1001 | 0
input port1(23) | 1001 | 0
input port1(24) | 1001 | 0
input port1(25) | 1001 | 0
input port1(26) | 1001 | 0
input port1(27) | 1001 | 0
input port1(28) | 1001 | 0
input port1(29) | 1001 | 0
input port1(30) | 1001 | 0
input port1(31) | 1001 | 0
input port1(32) | 1001 | 0
input port1(33) | 1001 | 0
input port1(34) | 1001 | 0
input port1(35) | 1001 | 0
input port1(36) | 1001 | 0
input port1(37) | 1001 | 0
input port1(38) | 1001 | 0
input port1(39) | 1001 | 0
input port1(40) | 1001 | 0
input port1(41) | 1001 | 0
input port1(42) | 1001 | 0
input port1(43) | 1001 | 0
input port1(44) | 1001 | 0
input port1(45) | 1001 | 0
input port1(46) | 1001 | 0
input port1(47) | 1001 | 0
input port1(48) | 1001 | 0
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output(1) |
input port1(1) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(2) |
input port1(2) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(3) |
input port1(3) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(4) |
input port1(4) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(5) |
input port1(5) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(6) |
input port1(6) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(7) |
input port1(7) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(8) |
input port1(8) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(9) |
input port1(9) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(10) |
input port1(10) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(11) |
input port1(11) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(12) |
input port1(12) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(13) |
input port1(13) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(14) |
input port1(14) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(15) |
input port1(15) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(16) |
input port1(16) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(17) |
input port1(17) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(18) |
input port1(18) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(19) |
input port1(19) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(20) |
input port1(20) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(21) |
input port1(21) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(22) |
input port1(22) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(23) |
input port1(23) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(24) |
input port1(24) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(25) |
input port1(25) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(26) |
input port1(26) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(27) |
input port1(27) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(28) |
input port1(28) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(29) |
input port1(29) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(30) |
input port1(30) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(31) |
input port1(31) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(32) |
input port1(32) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(33) |
input port1(33) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(34) |
input port1(34) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(35) |
input port1(35) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(36) |
input port1(36) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(37) |
input port1(37) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(38) |
input port1(38) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(39) |
input port1(39) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(40) |
input port1(40) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(41) |
input port1(41) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(42) |
input port1(42) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(43) |
input port1(43) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(44) |
input port1(44) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(45) |
input port1(45) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(46) |
input port1(46) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(47) |
input port1(47) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(48) |
input port1(48) | TF | (FF)
input port 2 | (FT) | (FF)

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTempVld_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTempVld_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (48/96) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) == input2 | 1001 | 0
input1(2) == input2 | 1001 | 0
input1(3) == input2 | 1001 | 0
input1(4) == input2 | 1001 | 0
input1(5) == input2 | 1001 | 0
input1(6) == input2 | 1001 | 0
input1(7) == input2 | 1001 | 0
input1(8) == input2 | 1001 | 0
input1(9) == input2 | 1001 | 0
input1(10) == input2 | 1001 | 0
input1(11) == input2 | 1001 | 0
input1(12) == input2 | 1001 | 0
input1(13) == input2 | 1001 | 0
input1(14) == input2 | 1001 | 0
input1(15) == input2 | 1001 | 0
input1(16) == input2 | 1001 | 0
input1(17) == input2 | 1001 | 0
input1(18) == input2 | 1001 | 0
input1(19) == input2 | 1001 | 0
input1(20) == input2 | 1001 | 0
input1(21) == input2 | 1001 | 0
input1(22) == input2 | 1001 | 0
input1(23) == input2 | 1001 | 0
input1(24) == input2 | 1001 | 0
input1(25) == input2 | 1001 | 0
input1(26) == input2 | 1001 | 0
input1(27) == input2 | 1001 | 0
input1(28) == input2 | 1001 | 0
input1(29) == input2 | 1001 | 0
input1(30) == input2 | 1001 | 0
input1(31) == input2 | 1001 | 0
input1(32) == input2 | 1001 | 0
input1(33) == input2 | 1001 | 0
input1(34) == input2 | 1001 | 0
input1(35) == input2 | 1001 | 0
input1(36) == input2 | 1001 | 0
input1(37) == input2 | 1001 | 0
input1(38) == input2 | 1001 | 0
input1(39) == input2 | 1001 | 0
input1(40) == input2 | 1001 | 0
input1(41) == input2 | 1001 | 0
input1(42) == input2 | 1001 | 0
input1(43) == input2 | 1001 | 0
input1(44) == input2 | 1001 | 0
input1(45) == input2 | 1001 | 0
input1(46) == input2 | 1001 | 0
input1(47) == input2 | 1001 | 0
input1(48) == input2 | 1001 | 0

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution
S-Function block "Bitwise Logical Operator" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution

### 119. SubSystem block "OverWrite4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTempVld_Output
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTempVld_Output/OverWrite4
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 120. SubSystem block "BusbarTemp_Output"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys
Child Systems: | BusbarTemp_SignalFilt, OverWrite2, ValidValueFilter_BusbarTemp
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 80
Condition | NA | 50% (338/676) condition outcomes
Decision | NA | 45% (64/141) decision outcomes
MCDC | NA | 0% (0/192) conditions reversed the outcome
Execution | NA | 100% (37/37) objective outcomes

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (96/192) condition outcomes
MCDC | 0% (0/96) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 0 | 1001
input port1(2) | 0 | 1001
input port1(3) | 0 | 1001
input port1(4) | 0 | 1001
input port1(5) | 0 | 1001
input port1(6) | 0 | 1001
input port1(7) | 0 | 1001
input port1(8) | 0 | 1001
input port1(9) | 0 | 1001
input port1(10) | 0 | 1001
input port1(11) | 0 | 1001
input port1(12) | 0 | 1001
input port1(13) | 0 | 1001
input port1(14) | 0 | 1001
input port1(15) | 0 | 1001
input port1(16) | 0 | 1001
input port1(17) | 0 | 1001
input port1(18) | 0 | 1001
input port1(19) | 0 | 1001
input port1(20) | 0 | 1001
input port1(21) | 0 | 1001
input port1(22) | 0 | 1001
input port1(23) | 0 | 1001
input port1(24) | 0 | 1001
input port1(25) | 0 | 1001
input port1(26) | 0 | 1001
input port1(27) | 0 | 1001
input port1(28) | 0 | 1001
input port1(29) | 0 | 1001
input port1(30) | 0 | 1001
input port1(31) | 0 | 1001
input port1(32) | 0 | 1001
input port1(33) | 0 | 1001
input port1(34) | 0 | 1001
input port1(35) | 0 | 1001
input port1(36) | 0 | 1001
input port1(37) | 0 | 1001
input port1(38) | 0 | 1001
input port1(39) | 0 | 1001
input port1(40) | 0 | 1001
input port1(41) | 0 | 1001
input port1(42) | 0 | 1001
input port1(43) | 0 | 1001
input port1(44) | 0 | 1001
input port1(45) | 0 | 1001
input port1(46) | 0 | 1001
input port1(47) | 0 | 1001
input port1(48) | 0 | 1001
input port2(1) | 0 | 1001
input port2(2) | 0 | 1001
input port2(3) | 0 | 1001
input port2(4) | 0 | 1001
input port2(5) | 0 | 1001
input port2(6) | 0 | 1001
input port2(7) | 0 | 1001
input port2(8) | 0 | 1001
input port2(9) | 0 | 1001
input port2(10) | 0 | 1001
input port2(11) | 0 | 1001
input port2(12) | 0 | 1001
input port2(13) | 0 | 1001
input port2(14) | 0 | 1001
input port2(15) | 0 | 1001
input port2(16) | 0 | 1001
input port2(17) | 0 | 1001
input port2(18) | 0 | 1001
input port2(19) | 0 | 1001
input port2(20) | 0 | 1001
input port2(21) | 0 | 1001
input port2(22) | 0 | 1001
input port2(23) | 0 | 1001
input port2(24) | 0 | 1001
input port2(25) | 0 | 1001
input port2(26) | 0 | 1001
input port2(27) | 0 | 1001
input port2(28) | 0 | 1001
input port2(29) | 0 | 1001
input port2(30) | 0 | 1001
input port2(31) | 0 | 1001
input port2(32) | 0 | 1001
input port2(33) | 0 | 1001
input port2(34) | 0 | 1001
input port2(35) | 0 | 1001
input port2(36) | 0 | 1001
input port2(37) | 0 | 1001
input port2(38) | 0 | 1001
input port2(39) | 0 | 1001
input port2(40) | 0 | 1001
input port2(41) | 0 | 1001
input port2(42) | 0 | 1001
input port2(43) | 0 | 1001
input port2(44) | 0 | 1001
input port2(45) | 0 | 1001
input port2(46) | 0 | 1001
input port2(47) | 0 | 1001
input port2(48) | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output(1) |
input port1(1) | (TF) | FF
input port2(1) | (FT) | FF
expression for output(2) |
input port1(2) | (TF) | FF
input port2(2) | (FT) | FF
expression for output(3) |
input port1(3) | (TF) | FF
input port2(3) | (FT) | FF
expression for output(4) |
input port1(4) | (TF) | FF
input port2(4) | (FT) | FF
expression for output(5) |
input port1(5) | (TF) | FF
input port2(5) | (FT) | FF
expression for output(6) |
input port1(6) | (TF) | FF
input port2(6) | (FT) | FF
expression for output(7) |
input port1(7) | (TF) | FF
input port2(7) | (FT) | FF
expression for output(8) |
input port1(8) | (TF) | FF
input port2(8) | (FT) | FF
expression for output(9) |
input port1(9) | (TF) | FF
input port2(9) | (FT) | FF
expression for output(10) |
input port1(10) | (TF) | FF
input port2(10) | (FT) | FF
expression for output(11) |
input port1(11) | (TF) | FF
input port2(11) | (FT) | FF
expression for output(12) |
input port1(12) | (TF) | FF
input port2(12) | (FT) | FF
expression for output(13) |
input port1(13) | (TF) | FF
input port2(13) | (FT) | FF
expression for output(14) |
input port1(14) | (TF) | FF
input port2(14) | (FT) | FF
expression for output(15) |
input port1(15) | (TF) | FF
input port2(15) | (FT) | FF
expression for output(16) |
input port1(16) | (TF) | FF
input port2(16) | (FT) | FF
expression for output(17) |
input port1(17) | (TF) | FF
input port2(17) | (FT) | FF
expression for output(18) |
input port1(18) | (TF) | FF
input port2(18) | (FT) | FF
expression for output(19) |
input port1(19) | (TF) | FF
input port2(19) | (FT) | FF
expression for output(20) |
input port1(20) | (TF) | FF
input port2(20) | (FT) | FF
expression for output(21) |
input port1(21) | (TF) | FF
input port2(21) | (FT) | FF
expression for output(22) |
input port1(22) | (TF) | FF
input port2(22) | (FT) | FF
expression for output(23) |
input port1(23) | (TF) | FF
input port2(23) | (FT) | FF
expression for output(24) |
input port1(24) | (TF) | FF
input port2(24) | (FT) | FF
expression for output(25) |
input port1(25) | (TF) | FF
input port2(25) | (FT) | FF
expression for output(26) |
input port1(26) | (TF) | FF
input port2(26) | (FT) | FF
expression for output(27) |
input port1(27) | (TF) | FF
input port2(27) | (FT) | FF
expression for output(28) |
input port1(28) | (TF) | FF
input port2(28) | (FT) | FF
expression for output(29) |
input port1(29) | (TF) | FF
input port2(29) | (FT) | FF
expression for output(30) |
input port1(30) | (TF) | FF
input port2(30) | (FT) | FF
expression for output(31) |
input port1(31) | (TF) | FF
input port2(31) | (FT) | FF
expression for output(32) |
input port1(32) | (TF) | FF
input port2(32) | (FT) | FF
expression for output(33) |
input port1(33) | (TF) | FF
input port2(33) | (FT) | FF
expression for output(34) |
input port1(34) | (TF) | FF
input port2(34) | (FT) | FF
expression for output(35) |
input port1(35) | (TF) | FF
input port2(35) | (FT) | FF
expression for output(36) |
input port1(36) | (TF) | FF
input port2(36) | (FT) | FF
expression for output(37) |
input port1(37) | (TF) | FF
input port2(37) | (FT) | FF
expression for output(38) |
input port1(38) | (TF) | FF
input port2(38) | (FT) | FF
expression for output(39) |
input port1(39) | (TF) | FF
input port2(39) | (FT) | FF
expression for output(40) |
input port1(40) | (TF) | FF
input port2(40) | (FT) | FF
expression for output(41) |
input port1(41) | (TF) | FF
input port2(41) | (FT) | FF
expression for output(42) |
input port1(42) | (TF) | FF
input port2(42) | (FT) | FF
expression for output(43) |
input port1(43) | (TF) | FF
input port2(43) | (FT) | FF
expression for output(44) |
input port1(44) | (TF) | FF
input port2(44) | (FT) | FF
expression for output(45) |
input port1(45) | (TF) | FF
input port2(45) | (FT) | FF
expression for output(46) |
input port1(46) | (TF) | FF
input port2(46) | (FT) | FF
expression for output(47) |
input port1(47) | (TF) | FF
input port2(47) | (FT) | FF
expression for output(48) |
input port1(48) | (TF) | FF
input port2(48) | (FT) | FF

#### Logic block "Logical Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (49/98) condition outcomes
MCDC | 0% (0/96) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 0 | 1001
input port1(2) | 0 | 1001
input port1(3) | 0 | 1001
input port1(4) | 0 | 1001
input port1(5) | 0 | 1001
input port1(6) | 0 | 1001
input port1(7) | 0 | 1001
input port1(8) | 0 | 1001
input port1(9) | 0 | 1001
input port1(10) | 0 | 1001
input port1(11) | 0 | 1001
input port1(12) | 0 | 1001
input port1(13) | 0 | 1001
input port1(14) | 0 | 1001
input port1(15) | 0 | 1001
input port1(16) | 0 | 1001
input port1(17) | 0 | 1001
input port1(18) | 0 | 1001
input port1(19) | 0 | 1001
input port1(20) | 0 | 1001
input port1(21) | 0 | 1001
input port1(22) | 0 | 1001
input port1(23) | 0 | 1001
input port1(24) | 0 | 1001
input port1(25) | 0 | 1001
input port1(26) | 0 | 1001
input port1(27) | 0 | 1001
input port1(28) | 0 | 1001
input port1(29) | 0 | 1001
input port1(30) | 0 | 1001
input port1(31) | 0 | 1001
input port1(32) | 0 | 1001
input port1(33) | 0 | 1001
input port1(34) | 0 | 1001
input port1(35) | 0 | 1001
input port1(36) | 0 | 1001
input port1(37) | 0 | 1001
input port1(38) | 0 | 1001
input port1(39) | 0 | 1001
input port1(40) | 0 | 1001
input port1(41) | 0 | 1001
input port1(42) | 0 | 1001
input port1(43) | 0 | 1001
input port1(44) | 0 | 1001
input port1(45) | 0 | 1001
input port1(46) | 0 | 1001
input port1(47) | 0 | 1001
input port1(48) | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output(1) |
input port1(1) | (TF) | FF
input port 2 | (FT) | FF
expression for output(2) |
input port1(2) | (TF) | FF
input port 2 | (FT) | FF
expression for output(3) |
input port1(3) | (TF) | FF
input port 2 | (FT) | FF
expression for output(4) |
input port1(4) | (TF) | FF
input port 2 | (FT) | FF
expression for output(5) |
input port1(5) | (TF) | FF
input port 2 | (FT) | FF
expression for output(6) |
input port1(6) | (TF) | FF
input port 2 | (FT) | FF
expression for output(7) |
input port1(7) | (TF) | FF
input port 2 | (FT) | FF
expression for output(8) |
input port1(8) | (TF) | FF
input port 2 | (FT) | FF
expression for output(9) |
input port1(9) | (TF) | FF
input port 2 | (FT) | FF
expression for output(10) |
input port1(10) | (TF) | FF
input port 2 | (FT) | FF
expression for output(11) |
input port1(11) | (TF) | FF
input port 2 | (FT) | FF
expression for output(12) |
input port1(12) | (TF) | FF
input port 2 | (FT) | FF
expression for output(13) |
input port1(13) | (TF) | FF
input port 2 | (FT) | FF
expression for output(14) |
input port1(14) | (TF) | FF
input port 2 | (FT) | FF
expression for output(15) |
input port1(15) | (TF) | FF
input port 2 | (FT) | FF
expression for output(16) |
input port1(16) | (TF) | FF
input port 2 | (FT) | FF
expression for output(17) |
input port1(17) | (TF) | FF
input port 2 | (FT) | FF
expression for output(18) |
input port1(18) | (TF) | FF
input port 2 | (FT) | FF
expression for output(19) |
input port1(19) | (TF) | FF
input port 2 | (FT) | FF
expression for output(20) |
input port1(20) | (TF) | FF
input port 2 | (FT) | FF
expression for output(21) |
input port1(21) | (TF) | FF
input port 2 | (FT) | FF
expression for output(22) |
input port1(22) | (TF) | FF
input port 2 | (FT) | FF
expression for output(23) |
input port1(23) | (TF) | FF
input port 2 | (FT) | FF
expression for output(24) |
input port1(24) | (TF) | FF
input port 2 | (FT) | FF
expression for output(25) |
input port1(25) | (TF) | FF
input port 2 | (FT) | FF
expression for output(26) |
input port1(26) | (TF) | FF
input port 2 | (FT) | FF
expression for output(27) |
input port1(27) | (TF) | FF
input port 2 | (FT) | FF
expression for output(28) |
input port1(28) | (TF) | FF
input port 2 | (FT) | FF
expression for output(29) |
input port1(29) | (TF) | FF
input port 2 | (FT) | FF
expression for output(30) |
input port1(30) | (TF) | FF
input port 2 | (FT) | FF
expression for output(31) |
input port1(31) | (TF) | FF
input port 2 | (FT) | FF
expression for output(32) |
input port1(32) | (TF) | FF
input port 2 | (FT) | FF
expression for output(33) |
input port1(33) | (TF) | FF
input port 2 | (FT) | FF
expression for output(34) |
input port1(34) | (TF) | FF
input port 2 | (FT) | FF
expression for output(35) |
input port1(35) | (TF) | FF
input port 2 | (FT) | FF
expression for output(36) |
input port1(36) | (TF) | FF
input port 2 | (FT) | FF
expression for output(37) |
input port1(37) | (TF) | FF
input port 2 | (FT) | FF
expression for output(38) |
input port1(38) | (TF) | FF
input port 2 | (FT) | FF
expression for output(39) |
input port1(39) | (TF) | FF
input port 2 | (FT) | FF
expression for output(40) |
input port1(40) | (TF) | FF
input port 2 | (FT) | FF
expression for output(41) |
input port1(41) | (TF) | FF
input port 2 | (FT) | FF
expression for output(42) |
input port1(42) | (TF) | FF
input port 2 | (FT) | FF
expression for output(43) |
input port1(43) | (TF) | FF
input port 2 | (FT) | FF
expression for output(44) |
input port1(44) | (TF) | FF
input port 2 | (FT) | FF
expression for output(45) |
input port1(45) | (TF) | FF
input port 2 | (FT) | FF
expression for output(46) |
input port1(46) | (TF) | FF
input port 2 | (FT) | FF
expression for output(47) |
input port1(47) | (TF) | FF
input port 2 | (FT) | FF
expression for output(48) |
input port1(48) | (TF) | FF
input port 2 | (FT) | FF

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 48
Decision | 50% (48/96) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input(1) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(2) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(3) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(4) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(5) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(6) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(7) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(8) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(9) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(10) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(11) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(12) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(13) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(14) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(15) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(16) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(17) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(18) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(19) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(20) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(21) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(22) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(23) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(24) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(25) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(26) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(27) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(28) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(29) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(30) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(31) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(32) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(33) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(34) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(35) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(36) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(37) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(38) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(39) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(40) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(41) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(42) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(43) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(44) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(45) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(46) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(47) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(48) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Switch block "Switch1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### RelationalOperator block "Comparison1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (48/96) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) == input2 | 0 | 1001
input1(2) == input2 | 0 | 1001
input1(3) == input2 | 0 | 1001
input1(4) == input2 | 0 | 1001
input1(5) == input2 | 0 | 1001
input1(6) == input2 | 0 | 1001
input1(7) == input2 | 0 | 1001
input1(8) == input2 | 0 | 1001
input1(9) == input2 | 0 | 1001
input1(10) == input2 | 0 | 1001
input1(11) == input2 | 0 | 1001
input1(12) == input2 | 0 | 1001
input1(13) == input2 | 0 | 1001
input1(14) == input2 | 0 | 1001
input1(15) == input2 | 0 | 1001
input1(16) == input2 | 0 | 1001
input1(17) == input2 | 0 | 1001
input1(18) == input2 | 0 | 1001
input1(19) == input2 | 0 | 1001
input1(20) == input2 | 0 | 1001
input1(21) == input2 | 0 | 1001
input1(22) == input2 | 0 | 1001
input1(23) == input2 | 0 | 1001
input1(24) == input2 | 0 | 1001
input1(25) == input2 | 0 | 1001
input1(26) == input2 | 0 | 1001
input1(27) == input2 | 0 | 1001
input1(28) == input2 | 0 | 1001
input1(29) == input2 | 0 | 1001
input1(30) == input2 | 0 | 1001
input1(31) == input2 | 0 | 1001
input1(32) == input2 | 0 | 1001
input1(33) == input2 | 0 | 1001
input1(34) == input2 | 0 | 1001
input1(35) == input2 | 0 | 1001
input1(36) == input2 | 0 | 1001
input1(37) == input2 | 0 | 1001
input1(38) == input2 | 0 | 1001
input1(39) == input2 | 0 | 1001
input1(40) == input2 | 0 | 1001
input1(41) == input2 | 0 | 1001
input1(42) == input2 | 0 | 1001
input1(43) == input2 | 0 | 1001
input1(44) == input2 | 0 | 1001
input1(45) == input2 | 0 | 1001
input1(46) == input2 | 0 | 1001
input1(47) == input2 | 0 | 1001
input1(48) == input2 | 0 | 1001

#### RelationalOperator block "Comparison4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (48/96) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) == input2 | 1001 | 0
input1(2) == input2 | 1001 | 0
input1(3) == input2 | 1001 | 0
input1(4) == input2 | 1001 | 0
input1(5) == input2 | 1001 | 0
input1(6) == input2 | 1001 | 0
input1(7) == input2 | 1001 | 0
input1(8) == input2 | 1001 | 0
input1(9) == input2 | 1001 | 0
input1(10) == input2 | 1001 | 0
input1(11) == input2 | 1001 | 0
input1(12) == input2 | 1001 | 0
input1(13) == input2 | 1001 | 0
input1(14) == input2 | 1001 | 0
input1(15) == input2 | 1001 | 0
input1(16) == input2 | 1001 | 0
input1(17) == input2 | 1001 | 0
input1(18) == input2 | 1001 | 0
input1(19) == input2 | 1001 | 0
input1(20) == input2 | 1001 | 0
input1(21) == input2 | 1001 | 0
input1(22) == input2 | 1001 | 0
input1(23) == input2 | 1001 | 0
input1(24) == input2 | 1001 | 0
input1(25) == input2 | 1001 | 0
input1(26) == input2 | 1001 | 0
input1(27) == input2 | 1001 | 0
input1(28) == input2 | 1001 | 0
input1(29) == input2 | 1001 | 0
input1(30) == input2 | 1001 | 0
input1(31) == input2 | 1001 | 0
input1(32) == input2 | 1001 | 0
input1(33) == input2 | 1001 | 0
input1(34) == input2 | 1001 | 0
input1(35) == input2 | 1001 | 0
input1(36) == input2 | 1001 | 0
input1(37) == input2 | 1001 | 0
input1(38) == input2 | 1001 | 0
input1(39) == input2 | 1001 | 0
input1(40) == input2 | 1001 | 0
input1(41) == input2 | 1001 | 0
input1(42) == input2 | 1001 | 0
input1(43) == input2 | 1001 | 0
input1(44) == input2 | 1001 | 0
input1(45) == input2 | 1001 | 0
input1(46) == input2 | 1001 | 0
input1(47) == input2 | 1001 | 0
input1(48) == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (48/96) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) ~= input2 | 0 | 1001
input1(2) ~= input2 | 0 | 1001
input1(3) ~= input2 | 0 | 1001
input1(4) ~= input2 | 0 | 1001
input1(5) ~= input2 | 0 | 1001
input1(6) ~= input2 | 0 | 1001
input1(7) ~= input2 | 0 | 1001
input1(8) ~= input2 | 0 | 1001
input1(9) ~= input2 | 0 | 1001
input1(10) ~= input2 | 0 | 1001
input1(11) ~= input2 | 0 | 1001
input1(12) ~= input2 | 0 | 1001
input1(13) ~= input2 | 0 | 1001
input1(14) ~= input2 | 0 | 1001
input1(15) ~= input2 | 0 | 1001
input1(16) ~= input2 | 0 | 1001
input1(17) ~= input2 | 0 | 1001
input1(18) ~= input2 | 0 | 1001
input1(19) ~= input2 | 0 | 1001
input1(20) ~= input2 | 0 | 1001
input1(21) ~= input2 | 0 | 1001
input1(22) ~= input2 | 0 | 1001
input1(23) ~= input2 | 0 | 1001
input1(24) ~= input2 | 0 | 1001
input1(25) ~= input2 | 0 | 1001
input1(26) ~= input2 | 0 | 1001
input1(27) ~= input2 | 0 | 1001
input1(28) ~= input2 | 0 | 1001
input1(29) ~= input2 | 0 | 1001
input1(30) ~= input2 | 0 | 1001
input1(31) ~= input2 | 0 | 1001
input1(32) ~= input2 | 0 | 1001
input1(33) ~= input2 | 0 | 1001
input1(34) ~= input2 | 0 | 1001
input1(35) ~= input2 | 0 | 1001
input1(36) ~= input2 | 0 | 1001
input1(37) ~= input2 | 0 | 1001
input1(38) ~= input2 | 0 | 1001
input1(39) ~= input2 | 0 | 1001
input1(40) ~= input2 | 0 | 1001
input1(41) ~= input2 | 0 | 1001
input1(42) ~= input2 | 0 | 1001
input1(43) ~= input2 | 0 | 1001
input1(44) ~= input2 | 0 | 1001
input1(45) ~= input2 | 0 | 1001
input1(46) ~= input2 | 0 | 1001
input1(47) ~= input2 | 0 | 1001
input1(48) ~= input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Lookup_n-D block "1-D Lookup Table" | Execution
DataTypeConversion block "Data Type Conversion" | Execution
DataTypeConversion block "Data Type Conversion1" | Execution
S-Function block "Bitwise Logical Operator" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution
Constant block "Constant6" | Execution
Constant block "Constant7" | Execution
UnitDelay block "Unit Delay" | Execution

### 121. SubSystem block "BusbarTemp_SignalFilt"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output
Child Systems: | 1D_Config_Word, InputValueCalc, MaxValue_sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 26
Condition | NA | 50% (48/96) condition outcomes
Decision | NA | 30% (11/37) decision outcomes
Execution | NA | 100% (15/15) objective outcomes

#### RelationalOperator block "Comparison1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (48/96) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) == input2 | 1001 | 0
input1(2) == input2 | 1001 | 0
input1(3) == input2 | 1001 | 0
input1(4) == input2 | 1001 | 0
input1(5) == input2 | 1001 | 0
input1(6) == input2 | 1001 | 0
input1(7) == input2 | 1001 | 0
input1(8) == input2 | 1001 | 0
input1(9) == input2 | 1001 | 0
input1(10) == input2 | 1001 | 0
input1(11) == input2 | 1001 | 0
input1(12) == input2 | 1001 | 0
input1(13) == input2 | 1001 | 0
input1(14) == input2 | 1001 | 0
input1(15) == input2 | 1001 | 0
input1(16) == input2 | 1001 | 0
input1(17) == input2 | 1001 | 0
input1(18) == input2 | 1001 | 0
input1(19) == input2 | 1001 | 0
input1(20) == input2 | 1001 | 0
input1(21) == input2 | 1001 | 0
input1(22) == input2 | 1001 | 0
input1(23) == input2 | 1001 | 0
input1(24) == input2 | 1001 | 0
input1(25) == input2 | 1001 | 0
input1(26) == input2 | 1001 | 0
input1(27) == input2 | 1001 | 0
input1(28) == input2 | 1001 | 0
input1(29) == input2 | 1001 | 0
input1(30) == input2 | 1001 | 0
input1(31) == input2 | 1001 | 0
input1(32) == input2 | 1001 | 0
input1(33) == input2 | 1001 | 0
input1(34) == input2 | 1001 | 0
input1(35) == input2 | 1001 | 0
input1(36) == input2 | 1001 | 0
input1(37) == input2 | 1001 | 0
input1(38) == input2 | 1001 | 0
input1(39) == input2 | 1001 | 0
input1(40) == input2 | 1001 | 0
input1(41) == input2 | 1001 | 0
input1(42) == input2 | 1001 | 0
input1(43) == input2 | 1001 | 0
input1(44) == input2 | 1001 | 0
input1(45) == input2 | 1001 | 0
input1(46) == input2 | 1001 | 0
input1(47) == input2 | 1001 | 0
input1(48) == input2 | 1001 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant6" | Execution
UnitDelay block "Unit Delay21" | Execution

### 122. SubSystem block "1D_Config_Word"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt
Child Systems: | Switch Case Action Subsystem, Switch Case Action Subsystem1, Switch Case Action Subsystem2, Switch Case Action Subsystem3, Switch Case Action Subsystem4, Switch Case Action Subsystem5, Switch Case Action Subsystem6, Switch Case Action Subsystem7, Switch Case Action Subsystem8, Switch Case Action Subsystem9
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 11
Decision | NA | 9% (1/11) decision outcomes
Execution | NA | 100% (12/12) objective outcomes

#### SwitchCase block "Switch Case"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/1D_Config_Word
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 10
Decision | 9% (1/11) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
truncated input | 9%
= Enum_UDSCapSel_Default | 1001/1001
= Enum_UDSCapSel_CATL153Ah | 0/1001
= Enum_UDSCapSel_CATL180Ah | 0/1001
= Enum_UDSCapSel_CATL177Ah | 0/1001
= Enum_UDSCapSel_CATL203Ah | 0/1001
= Enum_UDSCapSel_CATL51Ah | 0/1001
= Enum_UDSCapSel_CATL132Ah | 0/1001
= Enum_UDSCapSel_XWD75Ah | 0/1001
= Enum_UDSCapSel_TFE177Ah | 0/1001
= Enum_UDSCapSel_CATLCTP248Ah | 0/1001
= implicit-default | 0/1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution

### 123. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 124. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 125. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 126. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 127. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 128. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 129. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 130. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 131. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 132. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 133. SubSystem block "InputValueCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt
Child Systems: | CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/InputValueCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 6
Decision | NA | 50% (5/10) decision outcomes

### 134. Chart "CellDataPrc_20ms_sys/TempDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/InputValueCalc
Child Systems: | Default, Update
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 5
Decision | 100% (2/2) decision outcomes | 50% (5/10) decision outcomes
Decisions analyzed
Substate executed | 100%
State "Default" | 1/1000
State "Update" | 999/1000

#### Transition "[i >Input_num-1]" from "Default" to "Update"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/InputValueCalc
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 0/1
true | 1/1

### 135. State "Default"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/InputValueCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 1
Decision | NA | 50% (1/2) decision outcomes

#### Transition "[i <Input_num]" from Junction #8 to Junction #9

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/InputValueCalc.Default
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1/1
true | 0/1

### 136. State "Update"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/InputValueCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Decision | NA | 25% (1/4) decision outcomes

#### Transition "[i < Input_num]" from Junction #1 to Junction #2

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/InputValueCalc.Update
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1000/1000
true | 0/1000

#### Transition "[Update[i]]" from Junction #2 to Junction #3

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/InputValueCalc.Update
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
Transition trigger expression | 0%
false | --
true | --

### 137. SubSystem block "MaxValue_sort"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt
Child Systems: | CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/MaxValue_sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 9
Decision | NA | 31% (5/16) decision outcomes

### 138. Chart "CellDataPrc_20ms_sys/TempDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/MaxValue_sort
Child Systems: | sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 8
Decision | NA | 31% (5/16) decision outcomes

### 139. State "sort"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/MaxValue_sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 8
Decision | NA | 31% (5/16) decision outcomes

#### Transition "[m >= 1]" from Junction #11 to Junction #3

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
Transition trigger expression | 0%
false | --
true | --

#### Transition "[j < Input_num]" from Junction #5 to Junction #9

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1001/1001
true | 0/1001

#### Transition "[k<Input_num]" from Junction #4 to Junction #12

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
Transition trigger expression | 0%
false | --
true | --

#### Transition "[Output_Value[n][k] > Output_Value[m][k]..." from Junction #17 to Junction #14

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
Transition trigger expression | 0%
false | --
true | --

#### Transition "[n>=0]" from Junction #7 to Junction #17

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
Transition trigger expression | 0%
false | --
true | --

#### Transition "[k<Input_num]" from Junction #19 to Junction #20

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1001/1001
true | 0/1001

#### Transition "[Input_dim == 1]" from Junction #24 to Junction #23

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/BusbarTemp_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 0/1001
true | 1001/1001

#### Full Coverage

Model Object | Metric
Transition "[i < Input_dim]" from Junction #8 to Junction #5 | Decision

### 140. SubSystem block "OverWrite2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/OverWrite2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 141. SubSystem block "ValidValueFilter_BusbarTemp"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output
Child Systems: | CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/ValidValueFilter_BusbarTemp
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 3
Decision | NA | 75% (3/4) decision outcomes

### 142. Chart "CellDataPrc_20ms_sys/TempDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/ValidValueFilter_BusbarTemp
Child Systems: | VldValueFilter
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Decision | NA | 75% (3/4) decision outcomes

### 143. State "VldValueFilter"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/ValidValueFilter_BusbarTemp
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Decision | NA | 75% (3/4) decision outcomes

#### Transition "[i < NumbConfig]" from Junction #2 to Junction #3

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/BusbarTemp_Output/ValidValueFilter_BusbarTemp.VldValueFilter
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 48048/48048
true | 0/48048

#### Full Coverage

Model Object | Metric
Transition "[i < InputNumb]" from Junction #1 to Junction #2 | Decision

### 144. SubSystem block "CDP_GaCDP_ModuleTempHighFlt_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CDP_GaCDP_ModuleTempHighFlt_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 2/2
true (output is from 1st input port) | 0/2

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 145. SubSystem block "CMUPCBTemp_Flt"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys
Child Systems: | CDP_GbCDP_CMUTempHighFlt_flg, Hysteresis
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 5
Condition | NA | 50% (2/4) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
Execution | NA | 100% (13/13) objective outcomes

#### Full Coverage

Model Object | Metric
Sum block "Sum1" | Execution
Constant block "Constant1" | Execution
Constant block "Constant3" | Execution

### 146. SubSystem block "CDP_GbCDP_CMUTempHighFlt_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CMUPCBTemp_Flt
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CMUPCBTemp_Flt/CDP_GbCDP_CMUTempHighFlt_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 147. SubSystem block "Hysteresis"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CMUPCBTemp_Flt
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 3
Condition | NA | 50% (2/4) condition outcomes
Decision | NA | 50% (2/4) decision outcomes
Execution | NA | 100% (7/7) objective outcomes

#### Switch block "Switch1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CMUPCBTemp_Flt/Hysteresis
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Switch block "Switch2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CMUPCBTemp_Flt/Hysteresis
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001

#### RelationalOperator block "Greater Than"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CMUPCBTemp_Flt/Hysteresis
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 > input2 | 0 | 1001

#### RelationalOperator block "Greater Than1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CMUPCBTemp_Flt/Hysteresis
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 < input2 | 1001 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant Value" | Execution
Constant block "Constant Value1" | Execution
UnitDelay block "Unit Delay" | Execution

### 148. SubSystem block "CMUTempVld_Output"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys
Child Systems: | CDP_GaCDP_CMUPCBTempVld_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (66/132) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/64) conditions reversed the outcome
Execution | NA | 100% (9/9) objective outcomes

#### Logic block "Logical Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CMUTempVld_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (33/66) condition outcomes
MCDC | 0% (0/64) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 0 | 1001
input port1(2) | 0 | 1001
input port1(3) | 0 | 1001
input port1(4) | 0 | 1001
input port1(5) | 0 | 1001
input port1(6) | 0 | 1001
input port1(7) | 0 | 1001
input port1(8) | 0 | 1001
input port1(9) | 0 | 1001
input port1(10) | 0 | 1001
input port1(11) | 0 | 1001
input port1(12) | 0 | 1001
input port1(13) | 0 | 1001
input port1(14) | 0 | 1001
input port1(15) | 0 | 1001
input port1(16) | 0 | 1001
input port1(17) | 0 | 1001
input port1(18) | 0 | 1001
input port1(19) | 0 | 1001
input port1(20) | 0 | 1001
input port1(21) | 0 | 1001
input port1(22) | 0 | 1001
input port1(23) | 0 | 1001
input port1(24) | 0 | 1001
input port1(25) | 0 | 1001
input port1(26) | 0 | 1001
input port1(27) | 0 | 1001
input port1(28) | 0 | 1001
input port1(29) | 0 | 1001
input port1(30) | 0 | 1001
input port1(31) | 0 | 1001
input port1(32) | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output(1) |
input port1(1) | (TF) | FF
input port 2 | (FT) | FF
expression for output(2) |
input port1(2) | (TF) | FF
input port 2 | (FT) | FF
expression for output(3) |
input port1(3) | (TF) | FF
input port 2 | (FT) | FF
expression for output(4) |
input port1(4) | (TF) | FF
input port 2 | (FT) | FF
expression for output(5) |
input port1(5) | (TF) | FF
input port 2 | (FT) | FF
expression for output(6) |
input port1(6) | (TF) | FF
input port 2 | (FT) | FF
expression for output(7) |
input port1(7) | (TF) | FF
input port 2 | (FT) | FF
expression for output(8) |
input port1(8) | (TF) | FF
input port 2 | (FT) | FF
expression for output(9) |
input port1(9) | (TF) | FF
input port 2 | (FT) | FF
expression for output(10) |
input port1(10) | (TF) | FF
input port 2 | (FT) | FF
expression for output(11) |
input port1(11) | (TF) | FF
input port 2 | (FT) | FF
expression for output(12) |
input port1(12) | (TF) | FF
input port 2 | (FT) | FF
expression for output(13) |
input port1(13) | (TF) | FF
input port 2 | (FT) | FF
expression for output(14) |
input port1(14) | (TF) | FF
input port 2 | (FT) | FF
expression for output(15) |
input port1(15) | (TF) | FF
input port 2 | (FT) | FF
expression for output(16) |
input port1(16) | (TF) | FF
input port 2 | (FT) | FF
expression for output(17) |
input port1(17) | (TF) | FF
input port 2 | (FT) | FF
expression for output(18) |
input port1(18) | (TF) | FF
input port 2 | (FT) | FF
expression for output(19) |
input port1(19) | (TF) | FF
input port 2 | (FT) | FF
expression for output(20) |
input port1(20) | (TF) | FF
input port 2 | (FT) | FF
expression for output(21) |
input port1(21) | (TF) | FF
input port 2 | (FT) | FF
expression for output(22) |
input port1(22) | (TF) | FF
input port 2 | (FT) | FF
expression for output(23) |
input port1(23) | (TF) | FF
input port 2 | (FT) | FF
expression for output(24) |
input port1(24) | (TF) | FF
input port 2 | (FT) | FF
expression for output(25) |
input port1(25) | (TF) | FF
input port 2 | (FT) | FF
expression for output(26) |
input port1(26) | (TF) | FF
input port 2 | (FT) | FF
expression for output(27) |
input port1(27) | (TF) | FF
input port 2 | (FT) | FF
expression for output(28) |
input port1(28) | (TF) | FF
input port 2 | (FT) | FF
expression for output(29) |
input port1(29) | (TF) | FF
input port 2 | (FT) | FF
expression for output(30) |
input port1(30) | (TF) | FF
input port 2 | (FT) | FF
expression for output(31) |
input port1(31) | (TF) | FF
input port 2 | (FT) | FF
expression for output(32) |
input port1(32) | (TF) | FF
input port 2 | (FT) | FF

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CMUTempVld_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CMUTempVld_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (32/64) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2(1) | 0 | 1001
input1 == input2(2) | 0 | 1001
input1 == input2(3) | 0 | 1001
input1 == input2(4) | 0 | 1001
input1 == input2(5) | 0 | 1001
input1 == input2(6) | 0 | 1001
input1 == input2(7) | 0 | 1001
input1 == input2(8) | 0 | 1001
input1 == input2(9) | 0 | 1001
input1 == input2(10) | 0 | 1001
input1 == input2(11) | 0 | 1001
input1 == input2(12) | 0 | 1001
input1 == input2(13) | 0 | 1001
input1 == input2(14) | 0 | 1001
input1 == input2(15) | 0 | 1001
input1 == input2(16) | 0 | 1001
input1 == input2(17) | 0 | 1001
input1 == input2(18) | 0 | 1001
input1 == input2(19) | 0 | 1001
input1 == input2(20) | 0 | 1001
input1 == input2(21) | 0 | 1001
input1 == input2(22) | 0 | 1001
input1 == input2(23) | 0 | 1001
input1 == input2(24) | 0 | 1001
input1 == input2(25) | 0 | 1001
input1 == input2(26) | 0 | 1001
input1 == input2(27) | 0 | 1001
input1 == input2(28) | 0 | 1001
input1 == input2(29) | 0 | 1001
input1 == input2(30) | 0 | 1001
input1 == input2(31) | 0 | 1001
input1 == input2(32) | 0 | 1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution

### 149. SubSystem block "CDP_GaCDP_CMUPCBTempVld_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CMUTempVld_Output
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CMUTempVld_Output/CDP_GaCDP_CMUPCBTempVld_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 150. SubSystem block "CMUTemp_Output"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys
Child Systems: | CDP_GaCDP_CMUPCBTemp_C
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 34
Condition | NA | 50% (66/132) condition outcomes
Decision | NA | 50% (33/66) decision outcomes
MCDC | NA | 0% (0/64) conditions reversed the outcome
Execution | NA | 100% (13/13) objective outcomes

#### Logic block "Logical Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CMUTemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (33/66) condition outcomes
MCDC | 0% (0/64) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 1001 | 0
input port1(2) | 1001 | 0
input port1(3) | 1001 | 0
input port1(4) | 1001 | 0
input port1(5) | 1001 | 0
input port1(6) | 1001 | 0
input port1(7) | 1001 | 0
input port1(8) | 1001 | 0
input port1(9) | 1001 | 0
input port1(10) | 1001 | 0
input port1(11) | 1001 | 0
input port1(12) | 1001 | 0
input port1(13) | 1001 | 0
input port1(14) | 1001 | 0
input port1(15) | 1001 | 0
input port1(16) | 1001 | 0
input port1(17) | 1001 | 0
input port1(18) | 1001 | 0
input port1(19) | 1001 | 0
input port1(20) | 1001 | 0
input port1(21) | 1001 | 0
input port1(22) | 1001 | 0
input port1(23) | 1001 | 0
input port1(24) | 1001 | 0
input port1(25) | 1001 | 0
input port1(26) | 1001 | 0
input port1(27) | 1001 | 0
input port1(28) | 1001 | 0
input port1(29) | 1001 | 0
input port1(30) | 1001 | 0
input port1(31) | 1001 | 0
input port1(32) | 1001 | 0
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output(1) |
input port1(1) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(2) |
input port1(2) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(3) |
input port1(3) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(4) |
input port1(4) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(5) |
input port1(5) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(6) |
input port1(6) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(7) |
input port1(7) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(8) |
input port1(8) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(9) |
input port1(9) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(10) |
input port1(10) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(11) |
input port1(11) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(12) |
input port1(12) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(13) |
input port1(13) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(14) |
input port1(14) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(15) |
input port1(15) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(16) |
input port1(16) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(17) |
input port1(17) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(18) |
input port1(18) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(19) |
input port1(19) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(20) |
input port1(20) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(21) |
input port1(21) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(22) |
input port1(22) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(23) |
input port1(23) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(24) |
input port1(24) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(25) |
input port1(25) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(26) |
input port1(26) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(27) |
input port1(27) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(28) |
input port1(28) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(29) |
input port1(29) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(30) |
input port1(30) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(31) |
input port1(31) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(32) |
input port1(32) | TF | (FF)
input port 2 | (FT) | (FF)

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CMUTemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 32
Decision | 50% (32/64) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input(1) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(2) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(3) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(4) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(5) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(6) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(7) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(8) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(9) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(10) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(11) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(12) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(13) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(14) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(15) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(16) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(17) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(18) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(19) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(20) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(21) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(22) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(23) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(24) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(25) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(26) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(27) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(28) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(29) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(30) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(31) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(32) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CMUTemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CMUTemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (32/64) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) ~= input2 | 1001 | 0
input1(2) ~= input2 | 1001 | 0
input1(3) ~= input2 | 1001 | 0
input1(4) ~= input2 | 1001 | 0
input1(5) ~= input2 | 1001 | 0
input1(6) ~= input2 | 1001 | 0
input1(7) ~= input2 | 1001 | 0
input1(8) ~= input2 | 1001 | 0
input1(9) ~= input2 | 1001 | 0
input1(10) ~= input2 | 1001 | 0
input1(11) ~= input2 | 1001 | 0
input1(12) ~= input2 | 1001 | 0
input1(13) ~= input2 | 1001 | 0
input1(14) ~= input2 | 1001 | 0
input1(15) ~= input2 | 1001 | 0
input1(16) ~= input2 | 1001 | 0
input1(17) ~= input2 | 1001 | 0
input1(18) ~= input2 | 1001 | 0
input1(19) ~= input2 | 1001 | 0
input1(20) ~= input2 | 1001 | 0
input1(21) ~= input2 | 1001 | 0
input1(22) ~= input2 | 1001 | 0
input1(23) ~= input2 | 1001 | 0
input1(24) ~= input2 | 1001 | 0
input1(25) ~= input2 | 1001 | 0
input1(26) ~= input2 | 1001 | 0
input1(27) ~= input2 | 1001 | 0
input1(28) ~= input2 | 1001 | 0
input1(29) ~= input2 | 1001 | 0
input1(30) ~= input2 | 1001 | 0
input1(31) ~= input2 | 1001 | 0
input1(32) ~= input2 | 1001 | 0

#### Full Coverage

Model Object | Metric
Lookup_n-D block "1-D Lookup Table" | Execution
DataTypeConversion block "Data Type Conversion" | Execution
DataTypeConversion block "Data Type Conversion1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
UnitDelay block "Unit Delay" | Execution

### 151. SubSystem block "CDP_GaCDP_CMUPCBTemp_C"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CMUTemp_Output
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CMUTemp_Output/CDP_GaCDP_CMUPCBTemp_C
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 152. SubSystem block "CellTemp_SelfCheck"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys
Child Systems: | OverWrite
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (8/16) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/4) conditions reversed the outcome
Execution | NA | 100% (13/13) objective outcomes

#### Logic block "Logical Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CellTemp_SelfCheck
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (4/8) condition outcomes
MCDC | 0% (0/4) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
input port 3 | 1001 | 0
input port 4 | 1001 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TTTT) | (FTTT)
input port 2 | (TTTT) | (TFTT)
input port 3 | (TTTT) | (TTFT)
input port 4 | (TTTT) | (TTTF)

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CellTemp_SelfCheck
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CellTemp_SelfCheck
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 1001 | 0

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CellTemp_SelfCheck
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 1001 | 0

#### RelationalOperator block "Relational Operator4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CellTemp_SelfCheck
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion1" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution

### 153. SubSystem block "OverWrite"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CellTemp_SelfCheck
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/CellTemp_SelfCheck/OverWrite
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 154. SubSystem block "MaxMin_AFETemp_Get"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys
Child Systems: | AllAFETemp_FaultCheck, MaxMin_AFETemp_Get_Sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 24
Condition | NA | 13% (2/16) condition outcomes
Decision | NA | 10% (3/30) decision outcomes
MCDC | NA | 0% (0/6) conditions reversed the outcome
Execution | NA | 34% (15/44) objective outcomes

### 155. SubSystem block "AllAFETemp_FaultCheck"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get
Child Systems: | AFETempVld
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 1
Condition | NA | 50% (2/4) condition outcomes
Decision | NA | 100% (2/2) decision outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 100% (4/4) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant4" | Execution

### 156. SubSystem block "AFETempVld"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/AllAFETemp_FaultCheck
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 1
Condition | NA | 50% (2/4) condition outcomes
Decision | NA | 100% (2/2) decision outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 100% (3/3) objective outcomes

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/AllAFETemp_FaultCheck/AFETempVld
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 8008
input port 2 | 0 | 8008
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TF) | FF
input port 2 | (FT) | FF

#### Full Coverage

Model Object | Metric
ForIterator block "AFETemp" | Decision
Selector block "Selector" | Execution
UnitDelay block "Unit Delay1" | Execution

### 157. SubSystem block "MaxMin_AFETemp_Get_Sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get
Child Systems: | CDP_GcCDP_MaxCMUPCBTempNumb_numb, CDP_GcCDP_MaxCMUPCBTemp_C, CDP_GcCDP_MinCMUPCBTempNumb_numb, CDP_GcCDP_MinCMUPCBTemp_C, MinAFETemp_ForIterator
Uncovered Links: |
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 2 | 23
Condition | NA | 0% (0/12) condition outcomes
Decision | 50% (1/2) decision outcomes | 4% (1/28) decision outcomes
MCDC | NA | 0% (0/4) conditions reversed the outcome
Execution | NA | 28% (11/40) objective outcomes
Decisions analyzed
enable logical value | 50%
false | 1001/1001
true | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant3" | Execution

### 158. SubSystem block "CDP_GcCDP_MaxCMUPCBTempNumb_numb"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 67% (2/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/CDP_GcCDP_MaxCMUPCBTempNumb_numb
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 159. SubSystem block "CDP_GcCDP_MaxCMUPCBTemp_C"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 67% (2/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/CDP_GcCDP_MaxCMUPCBTemp_C
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 160. SubSystem block "CDP_GcCDP_MinCMUPCBTempNumb_numb"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 67% (2/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/CDP_GcCDP_MinCMUPCBTempNumb_numb
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 161. SubSystem block "CDP_GcCDP_MinCMUPCBTemp_C"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 67% (2/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/CDP_GcCDP_MinCMUPCBTemp_C
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 162. SubSystem block "MinAFETemp_ForIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys
Child Systems: | MaxAFETemp_ForIterator, MinAFETemp_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 13
Condition | NA | 0% (0/12) condition outcomes
Decision | NA | 0% (0/18) decision outcomes
MCDC | NA | 0% (0/4) conditions reversed the outcome
Execution | NA | 7% (2/27) objective outcomes

#### ForIterator block "MinAFETempNumbIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
loop condition | 0%
false | --
true | --

#### DataTypeConversion block "Data Type Conversion"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### Selector block "Selector1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### Selector block "Selector2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 163. SubSystem block "MaxAFETemp_ForIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator
Child Systems: | Unit Delay External IC, Unit Delay External IC2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 0% (0/6) condition outcomes
Decision | NA | 0% (0/8) decision outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 8% (1/12) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MaxAFETemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 0
input port 2 | 0 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TT) | (FT)
input port 2 | (TT) | (TF)

#### Switch block "Switch2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MaxAFETemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### Switch block "Switch3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MaxAFETemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MaxAFETemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/2) condition outcomes
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 0 | 0

#### UnitDelay block "Unit Delay3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MaxAFETemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant3" | Execution

### 164. SubSystem block "Unit Delay External IC"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MaxAFETemp_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 0% (0/3) objective outcomes

#### Switch block "Init"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MaxAFETemp_ForIterator/Unit Delay External IC
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### UnitDelay block "Unit Delay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MaxAFETemp_ForIterator/Unit Delay External IC
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MaxAFETemp_ForIterator/Unit Delay External IC
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 165. SubSystem block "Unit Delay External IC2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MaxAFETemp_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 0% (0/3) objective outcomes

#### Switch block "Init"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MaxAFETemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### UnitDelay block "Unit Delay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MaxAFETemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MaxAFETemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 166. SubSystem block "MinAFETemp_ForIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator
Child Systems: | Unit Delay External IC1, Unit Delay External IC2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 0% (0/6) condition outcomes
Decision | NA | 0% (0/8) decision outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 8% (1/12) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MinAFETemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 0
input port 2 | 0 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TT) | (FT)
input port 2 | (TT) | (TF)

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MinAFETemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### Switch block "Switch1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MinAFETemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MinAFETemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/2) condition outcomes
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 0

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MinAFETemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant3" | Execution

### 167. SubSystem block "Unit Delay External IC1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MinAFETemp_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 0% (0/3) objective outcomes

#### Switch block "Init"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MinAFETemp_ForIterator/Unit Delay External IC1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### UnitDelay block "Unit Delay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MinAFETemp_ForIterator/Unit Delay External IC1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MinAFETemp_ForIterator/Unit Delay External IC1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 168. SubSystem block "Unit Delay External IC2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MinAFETemp_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 0% (0/3) objective outcomes

#### Switch block "Init"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MinAFETemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### UnitDelay block "Unit Delay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MinAFETemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_AFETemp_Get/MaxMin_AFETemp_Get_Sys/MinAFETemp_ForIterator/MinAFETemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 169. SubSystem block "MaxMin_BusbarTemp_Get"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys
Child Systems: | AllBusbarTemp_FaultCheck, BusbarTempMax_SignalFilt, BusbarTempMin_SignalFilt, MaxMin_BusbarAvgTemp_Get_Sys, MaxMin_BusbarTemp_Get_Sys, OverWrite, OverWrite1, OverWrite2, OverWrite3
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 83
Condition | NA | 24% (144/596) condition outcomes
Decision | NA | 39% (41/104) decision outcomes
MCDC | NA | 0% (0/200) conditions reversed the outcome
Execution | NA | 67% (76/114) objective outcomes

### 170. SubSystem block "AllBusbarTemp_FaultCheck"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get
Child Systems: | BusbarTempVld, OverWrite
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 4
Condition | NA | 49% (144/296) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
MCDC | NA | 0% (0/100) conditions reversed the outcome
Execution | NA | 62% (8/13) objective outcomes

#### Logic block "Logical"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/AllBusbarTemp_FaultCheck
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (96/192) condition outcomes
MCDC | 0% (0/96) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 1001 | 0
input port1(2) | 1001 | 0
input port1(3) | 1001 | 0
input port1(4) | 1001 | 0
input port1(5) | 1001 | 0
input port1(6) | 1001 | 0
input port1(7) | 1001 | 0
input port1(8) | 1001 | 0
input port1(9) | 1001 | 0
input port1(10) | 1001 | 0
input port1(11) | 1001 | 0
input port1(12) | 1001 | 0
input port1(13) | 1001 | 0
input port1(14) | 1001 | 0
input port1(15) | 1001 | 0
input port1(16) | 1001 | 0
input port1(17) | 1001 | 0
input port1(18) | 1001 | 0
input port1(19) | 1001 | 0
input port1(20) | 1001 | 0
input port1(21) | 1001 | 0
input port1(22) | 1001 | 0
input port1(23) | 1001 | 0
input port1(24) | 1001 | 0
input port1(25) | 1001 | 0
input port1(26) | 1001 | 0
input port1(27) | 1001 | 0
input port1(28) | 1001 | 0
input port1(29) | 1001 | 0
input port1(30) | 1001 | 0
input port1(31) | 1001 | 0
input port1(32) | 1001 | 0
input port1(33) | 1001 | 0
input port1(34) | 1001 | 0
input port1(35) | 1001 | 0
input port1(36) | 1001 | 0
input port1(37) | 1001 | 0
input port1(38) | 1001 | 0
input port1(39) | 1001 | 0
input port1(40) | 1001 | 0
input port1(41) | 1001 | 0
input port1(42) | 1001 | 0
input port1(43) | 1001 | 0
input port1(44) | 1001 | 0
input port1(45) | 1001 | 0
input port1(46) | 1001 | 0
input port1(47) | 1001 | 0
input port1(48) | 1001 | 0
input port2(1) | 1001 | 0
input port2(2) | 1001 | 0
input port2(3) | 1001 | 0
input port2(4) | 1001 | 0
input port2(5) | 1001 | 0
input port2(6) | 1001 | 0
input port2(7) | 1001 | 0
input port2(8) | 1001 | 0
input port2(9) | 1001 | 0
input port2(10) | 1001 | 0
input port2(11) | 1001 | 0
input port2(12) | 1001 | 0
input port2(13) | 1001 | 0
input port2(14) | 1001 | 0
input port2(15) | 1001 | 0
input port2(16) | 1001 | 0
input port2(17) | 1001 | 0
input port2(18) | 1001 | 0
input port2(19) | 1001 | 0
input port2(20) | 1001 | 0
input port2(21) | 1001 | 0
input port2(22) | 1001 | 0
input port2(23) | 1001 | 0
input port2(24) | 1001 | 0
input port2(25) | 1001 | 0
input port2(26) | 1001 | 0
input port2(27) | 1001 | 0
input port2(28) | 1001 | 0
input port2(29) | 1001 | 0
input port2(30) | 1001 | 0
input port2(31) | 1001 | 0
input port2(32) | 1001 | 0
input port2(33) | 1001 | 0
input port2(34) | 1001 | 0
input port2(35) | 1001 | 0
input port2(36) | 1001 | 0
input port2(37) | 1001 | 0
input port2(38) | 1001 | 0
input port2(39) | 1001 | 0
input port2(40) | 1001 | 0
input port2(41) | 1001 | 0
input port2(42) | 1001 | 0
input port2(43) | 1001 | 0
input port2(44) | 1001 | 0
input port2(45) | 1001 | 0
input port2(46) | 1001 | 0
input port2(47) | 1001 | 0
input port2(48) | 1001 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output(1) |
input port1(1) | TT | (FT)
input port2(1) | TT | (TF)
expression for output(2) |
input port1(2) | TT | (FT)
input port2(2) | TT | (TF)
expression for output(3) |
input port1(3) | TT | (FT)
input port2(3) | TT | (TF)
expression for output(4) |
input port1(4) | TT | (FT)
input port2(4) | TT | (TF)
expression for output(5) |
input port1(5) | TT | (FT)
input port2(5) | TT | (TF)
expression for output(6) |
input port1(6) | TT | (FT)
input port2(6) | TT | (TF)
expression for output(7) |
input port1(7) | TT | (FT)
input port2(7) | TT | (TF)
expression for output(8) |
input port1(8) | TT | (FT)
input port2(8) | TT | (TF)
expression for output(9) |
input port1(9) | TT | (FT)
input port2(9) | TT | (TF)
expression for output(10) |
input port1(10) | TT | (FT)
input port2(10) | TT | (TF)
expression for output(11) |
input port1(11) | TT | (FT)
input port2(11) | TT | (TF)
expression for output(12) |
input port1(12) | TT | (FT)
input port2(12) | TT | (TF)
expression for output(13) |
input port1(13) | TT | (FT)
input port2(13) | TT | (TF)
expression for output(14) |
input port1(14) | TT | (FT)
input port2(14) | TT | (TF)
expression for output(15) |
input port1(15) | TT | (FT)
input port2(15) | TT | (TF)
expression for output(16) |
input port1(16) | TT | (FT)
input port2(16) | TT | (TF)
expression for output(17) |
input port1(17) | TT | (FT)
input port2(17) | TT | (TF)
expression for output(18) |
input port1(18) | TT | (FT)
input port2(18) | TT | (TF)
expression for output(19) |
input port1(19) | TT | (FT)
input port2(19) | TT | (TF)
expression for output(20) |
input port1(20) | TT | (FT)
input port2(20) | TT | (TF)
expression for output(21) |
input port1(21) | TT | (FT)
input port2(21) | TT | (TF)
expression for output(22) |
input port1(22) | TT | (FT)
input port2(22) | TT | (TF)
expression for output(23) |
input port1(23) | TT | (FT)
input port2(23) | TT | (TF)
expression for output(24) |
input port1(24) | TT | (FT)
input port2(24) | TT | (TF)
expression for output(25) |
input port1(25) | TT | (FT)
input port2(25) | TT | (TF)
expression for output(26) |
input port1(26) | TT | (FT)
input port2(26) | TT | (TF)
expression for output(27) |
input port1(27) | TT | (FT)
input port2(27) | TT | (TF)
expression for output(28) |
input port1(28) | TT | (FT)
input port2(28) | TT | (TF)
expression for output(29) |
input port1(29) | TT | (FT)
input port2(29) | TT | (TF)
expression for output(30) |
input port1(30) | TT | (FT)
input port2(30) | TT | (TF)
expression for output(31) |
input port1(31) | TT | (FT)
input port2(31) | TT | (TF)
expression for output(32) |
input port1(32) | TT | (FT)
input port2(32) | TT | (TF)
expression for output(33) |
input port1(33) | TT | (FT)
input port2(33) | TT | (TF)
expression for output(34) |
input port1(34) | TT | (FT)
input port2(34) | TT | (TF)
expression for output(35) |
input port1(35) | TT | (FT)
input port2(35) | TT | (TF)
expression for output(36) |
input port1(36) | TT | (FT)
input port2(36) | TT | (TF)
expression for output(37) |
input port1(37) | TT | (FT)
input port2(37) | TT | (TF)
expression for output(38) |
input port1(38) | TT | (FT)
input port2(38) | TT | (TF)
expression for output(39) |
input port1(39) | TT | (FT)
input port2(39) | TT | (TF)
expression for output(40) |
input port1(40) | TT | (FT)
input port2(40) | TT | (TF)
expression for output(41) |
input port1(41) | TT | (FT)
input port2(41) | TT | (TF)
expression for output(42) |
input port1(42) | TT | (FT)
input port2(42) | TT | (TF)
expression for output(43) |
input port1(43) | TT | (FT)
input port2(43) | TT | (TF)
expression for output(44) |
input port1(44) | TT | (FT)
input port2(44) | TT | (TF)
expression for output(45) |
input port1(45) | TT | (FT)
input port2(45) | TT | (TF)
expression for output(46) |
input port1(46) | TT | (FT)
input port2(46) | TT | (TF)
expression for output(47) |
input port1(47) | TT | (FT)
input port2(47) | TT | (TF)
expression for output(48) |
input port1(48) | TT | (FT)
input port2(48) | TT | (TF)

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/AllBusbarTemp_FaultCheck
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### RelationalOperator block "Comparison4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/AllBusbarTemp_FaultCheck
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (48/96) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) == input2 | 1001 | 0
input1(2) == input2 | 1001 | 0
input1(3) == input2 | 1001 | 0
input1(4) == input2 | 1001 | 0
input1(5) == input2 | 1001 | 0
input1(6) == input2 | 1001 | 0
input1(7) == input2 | 1001 | 0
input1(8) == input2 | 1001 | 0
input1(9) == input2 | 1001 | 0
input1(10) == input2 | 1001 | 0
input1(11) == input2 | 1001 | 0
input1(12) == input2 | 1001 | 0
input1(13) == input2 | 1001 | 0
input1(14) == input2 | 1001 | 0
input1(15) == input2 | 1001 | 0
input1(16) == input2 | 1001 | 0
input1(17) == input2 | 1001 | 0
input1(18) == input2 | 1001 | 0
input1(19) == input2 | 1001 | 0
input1(20) == input2 | 1001 | 0
input1(21) == input2 | 1001 | 0
input1(22) == input2 | 1001 | 0
input1(23) == input2 | 1001 | 0
input1(24) == input2 | 1001 | 0
input1(25) == input2 | 1001 | 0
input1(26) == input2 | 1001 | 0
input1(27) == input2 | 1001 | 0
input1(28) == input2 | 1001 | 0
input1(29) == input2 | 1001 | 0
input1(30) == input2 | 1001 | 0
input1(31) == input2 | 1001 | 0
input1(32) == input2 | 1001 | 0
input1(33) == input2 | 1001 | 0
input1(34) == input2 | 1001 | 0
input1(35) == input2 | 1001 | 0
input1(36) == input2 | 1001 | 0
input1(37) == input2 | 1001 | 0
input1(38) == input2 | 1001 | 0
input1(39) == input2 | 1001 | 0
input1(40) == input2 | 1001 | 0
input1(41) == input2 | 1001 | 0
input1(42) == input2 | 1001 | 0
input1(43) == input2 | 1001 | 0
input1(44) == input2 | 1001 | 0
input1(45) == input2 | 1001 | 0
input1(46) == input2 | 1001 | 0
input1(47) == input2 | 1001 | 0
input1(48) == input2 | 1001 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution

### 171. SubSystem block "BusbarTempVld"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/AllBusbarTemp_FaultCheck
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 1
Condition | NA | 0% (0/8) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/4) conditions reversed the outcome
Execution | NA | 0% (0/5) objective outcomes

#### ForIterator block "BusbarTemp"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/AllBusbarTemp_FaultCheck/BusbarTempVld
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
loop condition | 50%
false | 1001/1001
true | 0/1001

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/AllBusbarTemp_FaultCheck/BusbarTempVld
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 0
input port 2 | 0 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TT) | (FT)
input port 2 | (TT) | (TF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/AllBusbarTemp_FaultCheck/BusbarTempVld
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 0
input port 2 | 0 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TF) | (FF)
input port 2 | (FT) | (FF)

#### Selector block "Selector"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/AllBusbarTemp_FaultCheck/BusbarTempVld
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/AllBusbarTemp_FaultCheck/BusbarTempVld
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/AllBusbarTemp_FaultCheck/BusbarTempVld
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 172. SubSystem block "OverWrite"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/AllBusbarTemp_FaultCheck
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/AllBusbarTemp_FaultCheck/OverWrite
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 173. SubSystem block "BusbarTempMax_SignalFilt"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get
Child Systems: | 1D_Config_Word, InputValueCalc, MaxValue_sort, ValueCalc, ValueIndexCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 25
Decision | NA | 52% (16/31) decision outcomes
Execution | NA | 100% (25/25) objective outcomes

#### Full Coverage

Model Object | Metric
UnitDelay block "Unit Delay21" | Execution

### 174. SubSystem block "1D_Config_Word"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt
Child Systems: | Switch Case Action Subsystem, Switch Case Action Subsystem1, Switch Case Action Subsystem2, Switch Case Action Subsystem3, Switch Case Action Subsystem4, Switch Case Action Subsystem5, Switch Case Action Subsystem6, Switch Case Action Subsystem7, Switch Case Action Subsystem8, Switch Case Action Subsystem9
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 11
Decision | NA | 9% (1/11) decision outcomes
Execution | NA | 100% (12/12) objective outcomes

#### SwitchCase block "Switch Case"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/1D_Config_Word
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 10
Decision | 9% (1/11) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
truncated input | 9%
= Enum_UDSCapSel_Default | 1001/1001
= Enum_UDSCapSel_CATL153Ah | 0/1001
= Enum_UDSCapSel_CATL180Ah | 0/1001
= Enum_UDSCapSel_CATL177Ah | 0/1001
= Enum_UDSCapSel_CATL203Ah | 0/1001
= Enum_UDSCapSel_CATL51Ah | 0/1001
= Enum_UDSCapSel_CATL132Ah | 0/1001
= Enum_UDSCapSel_XWD75Ah | 0/1001
= Enum_UDSCapSel_TFE177Ah | 0/1001
= Enum_UDSCapSel_CATLCTP248Ah | 0/1001
= implicit-default | 0/1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution

### 175. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 176. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 177. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 178. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 179. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 180. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 181. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 182. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 183. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 184. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 185. SubSystem block "InputValueCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt
Child Systems: | CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/InputValueCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 4
Decision | NA | 60% (3/5) decision outcomes

### 186. Chart "CellDataPrc_20ms_sys/TempDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/InputValueCalc
Child Systems: | VldValueFilter
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 3
Decision | NA | 60% (3/5) decision outcomes

### 187. State "VldValueFilter"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/InputValueCalc
Uncovered Links: |
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 2 | 3
Decision | 67% (2/3) decision outcomes | 60% (3/5) decision outcomes
Decisions analyzed
Substate exited when parent exits | 67%
State "Default" | 1/1000
State "NotUpdate" | 999/1000
State "Update" | 0/1000

#### Transition "[Rige]" from Junction #0 to Junction #1

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/InputValueCalc.VldValueFilter
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1000/1000
true | 0/1000

### 188. SubSystem block "MaxValue_sort"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt
Child Systems: | CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/MaxValue_sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 6
Decision | NA | 90% (9/10) decision outcomes

### 189. Chart "CellDataPrc_20ms_sys/TempDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/MaxValue_sort
Child Systems: | sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 5
Decision | NA | 90% (9/10) decision outcomes

### 190. State "sort"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/MaxValue_sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 5
Decision | NA | 90% (9/10) decision outcomes

#### Transition "[Output_Value[j] > temp]" from Junction #6 to Junction #5

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1001/1001
true | 0/1001

#### Full Coverage

Model Object | Metric
Transition "[j < Input_dim]" from Junction #13 to Junction #6 | Decision
Transition "[i < Input_dim]" from Junction #10 to Junction #9 | Decision
Transition "[i < Input_dim]" from Junction #15 to Junction #11 | Decision
Transition "[i < Input_dim]" from Junction #4 to Junction #7 | Decision

### 191. SubSystem block "ValueCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (10/10) objective outcomes

#### Full Coverage

Model Object | Metric
Product block "Product1" | Execution
Product block "Product2" | Execution
Sum block "Sum" | Execution
Sum block "Sum1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant4" | Execution
Constant block "Constant6" | Execution
Constant block "Constant7" | Execution
Selector block "Selector" | Execution
Selector block "Selector1" | Execution

### 192. SubSystem block "ValueIndexCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt
Child Systems: | InputValueCalc1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 4
Decision | NA | 60% (3/5) decision outcomes
Execution | NA | 100% (2/2) objective outcomes

#### Full Coverage

Model Object | Metric
Selector block "Selector2" | Execution
UnitDelay block "Unit Delay1" | Execution

### 193. SubSystem block "InputValueCalc1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/ValueIndexCalc
Child Systems: | CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/ValueIndexCalc/InputValueCalc1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 4
Decision | NA | 60% (3/5) decision outcomes

### 194. Chart "CellDataPrc_20ms_sys/TempDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/ValueIndexCalc/InputValueCalc1
Child Systems: | VldValueFilter
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 3
Decision | NA | 60% (3/5) decision outcomes

### 195. State "VldValueFilter"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/ValueIndexCalc/InputValueCalc1
Uncovered Links: |
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 2 | 3
Decision | 67% (2/3) decision outcomes | 60% (3/5) decision outcomes
Decisions analyzed
Substate exited when parent exits | 67%
State "Default" | 1/1000
State "NotUpdate" | 999/1000
State "Update" | 0/1000

#### Transition "[Rige]" from Junction #0 to Junction #1

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMax_SignalFilt/ValueIndexCalc/InputValueCalc1.VldValueFilter
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1000/1000
true | 0/1000

### 196. SubSystem block "BusbarTempMin_SignalFilt"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get
Child Systems: | 1D_Config_Word, InputValueCalc, MaxValue_sort, ValueCalc, ValueIndexCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 25
Decision | NA | 52% (16/31) decision outcomes
Execution | NA | 100% (25/25) objective outcomes

#### Full Coverage

Model Object | Metric
UnitDelay block "Unit Delay21" | Execution

### 197. SubSystem block "1D_Config_Word"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt
Child Systems: | Switch Case Action Subsystem, Switch Case Action Subsystem1, Switch Case Action Subsystem2, Switch Case Action Subsystem3, Switch Case Action Subsystem4, Switch Case Action Subsystem5, Switch Case Action Subsystem6, Switch Case Action Subsystem7, Switch Case Action Subsystem8, Switch Case Action Subsystem9
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 11
Decision | NA | 9% (1/11) decision outcomes
Execution | NA | 100% (12/12) objective outcomes

#### SwitchCase block "Switch Case"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/1D_Config_Word
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 10
Decision | 9% (1/11) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
truncated input | 9%
= Enum_UDSCapSel_Default | 1001/1001
= Enum_UDSCapSel_CATL153Ah | 0/1001
= Enum_UDSCapSel_CATL180Ah | 0/1001
= Enum_UDSCapSel_CATL177Ah | 0/1001
= Enum_UDSCapSel_CATL203Ah | 0/1001
= Enum_UDSCapSel_CATL51Ah | 0/1001
= Enum_UDSCapSel_CATL132Ah | 0/1001
= Enum_UDSCapSel_XWD75Ah | 0/1001
= Enum_UDSCapSel_TFE177Ah | 0/1001
= Enum_UDSCapSel_CATLCTP248Ah | 0/1001
= implicit-default | 0/1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution

### 198. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 199. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 200. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 201. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 202. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 203. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 204. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 205. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 206. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 207. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 208. SubSystem block "InputValueCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt
Child Systems: | CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/InputValueCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 4
Decision | NA | 60% (3/5) decision outcomes

### 209. Chart "CellDataPrc_20ms_sys/TempDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/InputValueCalc
Child Systems: | VldValueFilter
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 3
Decision | NA | 60% (3/5) decision outcomes

### 210. State "VldValueFilter"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/InputValueCalc
Uncovered Links: |
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 2 | 3
Decision | 67% (2/3) decision outcomes | 60% (3/5) decision outcomes
Decisions analyzed
Substate exited when parent exits | 67%
State "Default" | 1/1000
State "NotUpdate" | 999/1000
State "Update" | 0/1000

#### Transition "[Rige]" from Junction #0 to Junction #1

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/InputValueCalc.VldValueFilter
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1000/1000
true | 0/1000

### 211. SubSystem block "MaxValue_sort"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt
Child Systems: | CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/MaxValue_sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 6
Decision | NA | 90% (9/10) decision outcomes

### 212. Chart "CellDataPrc_20ms_sys/TempDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/MaxValue_sort
Child Systems: | sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 5
Decision | NA | 90% (9/10) decision outcomes

### 213. State "sort"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/MaxValue_sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 5
Decision | NA | 90% (9/10) decision outcomes

#### Transition "[Output_Value[j] > temp]" from Junction #6 to Junction #5

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1001/1001
true | 0/1001

#### Full Coverage

Model Object | Metric
Transition "[j < Input_dim]" from Junction #13 to Junction #6 | Decision
Transition "[i < Input_dim]" from Junction #10 to Junction #9 | Decision
Transition "[i < Input_dim]" from Junction #15 to Junction #11 | Decision
Transition "[i < Input_dim]" from Junction #4 to Junction #7 | Decision

### 214. SubSystem block "ValueCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (10/10) objective outcomes

#### Full Coverage

Model Object | Metric
Product block "Product1" | Execution
Product block "Product2" | Execution
Sum block "Sum" | Execution
Sum block "Sum1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant4" | Execution
Constant block "Constant6" | Execution
Constant block "Constant7" | Execution
Selector block "Selector" | Execution
Selector block "Selector1" | Execution

### 215. SubSystem block "ValueIndexCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt
Child Systems: | InputValueCalc1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 4
Decision | NA | 60% (3/5) decision outcomes
Execution | NA | 100% (2/2) objective outcomes

#### Full Coverage

Model Object | Metric
Selector block "Selector2" | Execution
UnitDelay block "Unit Delay1" | Execution

### 216. SubSystem block "InputValueCalc1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/ValueIndexCalc
Child Systems: | CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/ValueIndexCalc/InputValueCalc1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 4
Decision | NA | 60% (3/5) decision outcomes

### 217. Chart "CellDataPrc_20ms_sys/TempDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/ValueIndexCalc/InputValueCalc1
Child Systems: | VldValueFilter
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 3
Decision | NA | 60% (3/5) decision outcomes

### 218. State "VldValueFilter"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/ValueIndexCalc/InputValueCalc1
Uncovered Links: |
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 2 | 3
Decision | 67% (2/3) decision outcomes | 60% (3/5) decision outcomes
Decisions analyzed
Substate exited when parent exits | 67%
State "Default" | 1/1000
State "NotUpdate" | 999/1000
State "Update" | 0/1000

#### Transition "[Rige]" from Junction #0 to Junction #1

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/BusbarTempMin_SignalFilt/ValueIndexCalc/InputValueCalc1.VldValueFilter
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1000/1000
true | 0/1000

### 219. SubSystem block "MaxMin_BusbarAvgTemp_Get_Sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get
Child Systems: | MinBusbarTemp_ForIterator, OverWrite1
Uncovered Links: |
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 2 | 5
Decision | 50% (1/2) decision outcomes | 17% (1/6) decision outcomes
Execution | NA | 29% (2/7) objective outcomes
Decisions analyzed
enable logical value | 50%
false | 1001/1001
true | 0/1001

#### Product block "Divide1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarAvgTemp_Get_Sys
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 220. SubSystem block "MinBusbarTemp_ForIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarAvgTemp_Get_Sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 1
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 0% (0/3) objective outcomes

#### ForIterator block "MinBusbarTempNumbIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarAvgTemp_Get_Sys/MinBusbarTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
loop condition | 0%
false | --
true | --

#### Sum block "Add"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarAvgTemp_Get_Sys/MinBusbarTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### Selector block "Selector1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarAvgTemp_Get_Sys/MinBusbarTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarAvgTemp_Get_Sys/MinBusbarTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 221. SubSystem block "OverWrite1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarAvgTemp_Get_Sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 67% (2/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarAvgTemp_Get_Sys/OverWrite1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 222. SubSystem block "MaxMin_BusbarTemp_Get_Sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get
Child Systems: | MinBusbarTemp_ForIterator
Uncovered Links: |
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 2 | 16
Condition | NA | 0% (0/300) condition outcomes
Decision | 50% (1/2) decision outcomes | 5% (1/22) decision outcomes
MCDC | NA | 0% (0/100) conditions reversed the outcome
Execution | NA | 13% (4/32) objective outcomes
Decisions analyzed
enable logical value | 50%
false | 1001/1001
true | 0/1001

#### Logic block "Logical"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/192) condition outcomes
MCDC | 0% (0/96) conditions reversed the outcome
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 0 | 0
input port1(2) | 0 | 0
input port1(3) | 0 | 0
input port1(4) | 0 | 0
input port1(5) | 0 | 0
input port1(6) | 0 | 0
input port1(7) | 0 | 0
input port1(8) | 0 | 0
input port1(9) | 0 | 0
input port1(10) | 0 | 0
input port1(11) | 0 | 0
input port1(12) | 0 | 0
input port1(13) | 0 | 0
input port1(14) | 0 | 0
input port1(15) | 0 | 0
input port1(16) | 0 | 0
input port1(17) | 0 | 0
input port1(18) | 0 | 0
input port1(19) | 0 | 0
input port1(20) | 0 | 0
input port1(21) | 0 | 0
input port1(22) | 0 | 0
input port1(23) | 0 | 0
input port1(24) | 0 | 0
input port1(25) | 0 | 0
input port1(26) | 0 | 0
input port1(27) | 0 | 0
input port1(28) | 0 | 0
input port1(29) | 0 | 0
input port1(30) | 0 | 0
input port1(31) | 0 | 0
input port1(32) | 0 | 0
input port1(33) | 0 | 0
input port1(34) | 0 | 0
input port1(35) | 0 | 0
input port1(36) | 0 | 0
input port1(37) | 0 | 0
input port1(38) | 0 | 0
input port1(39) | 0 | 0
input port1(40) | 0 | 0
input port1(41) | 0 | 0
input port1(42) | 0 | 0
input port1(43) | 0 | 0
input port1(44) | 0 | 0
input port1(45) | 0 | 0
input port1(46) | 0 | 0
input port1(47) | 0 | 0
input port1(48) | 0 | 0
input port2(1) | 0 | 0
input port2(2) | 0 | 0
input port2(3) | 0 | 0
input port2(4) | 0 | 0
input port2(5) | 0 | 0
input port2(6) | 0 | 0
input port2(7) | 0 | 0
input port2(8) | 0 | 0
input port2(9) | 0 | 0
input port2(10) | 0 | 0
input port2(11) | 0 | 0
input port2(12) | 0 | 0
input port2(13) | 0 | 0
input port2(14) | 0 | 0
input port2(15) | 0 | 0
input port2(16) | 0 | 0
input port2(17) | 0 | 0
input port2(18) | 0 | 0
input port2(19) | 0 | 0
input port2(20) | 0 | 0
input port2(21) | 0 | 0
input port2(22) | 0 | 0
input port2(23) | 0 | 0
input port2(24) | 0 | 0
input port2(25) | 0 | 0
input port2(26) | 0 | 0
input port2(27) | 0 | 0
input port2(28) | 0 | 0
input port2(29) | 0 | 0
input port2(30) | 0 | 0
input port2(31) | 0 | 0
input port2(32) | 0 | 0
input port2(33) | 0 | 0
input port2(34) | 0 | 0
input port2(35) | 0 | 0
input port2(36) | 0 | 0
input port2(37) | 0 | 0
input port2(38) | 0 | 0
input port2(39) | 0 | 0
input port2(40) | 0 | 0
input port2(41) | 0 | 0
input port2(42) | 0 | 0
input port2(43) | 0 | 0
input port2(44) | 0 | 0
input port2(45) | 0 | 0
input port2(46) | 0 | 0
input port2(47) | 0 | 0
input port2(48) | 0 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output(1) |
input port1(1) | (TT) | (FT)
input port2(1) | (TT) | (TF)
expression for output(2) |
input port1(2) | (TT) | (FT)
input port2(2) | (TT) | (TF)
expression for output(3) |
input port1(3) | (TT) | (FT)
input port2(3) | (TT) | (TF)
expression for output(4) |
input port1(4) | (TT) | (FT)
input port2(4) | (TT) | (TF)
expression for output(5) |
input port1(5) | (TT) | (FT)
input port2(5) | (TT) | (TF)
expression for output(6) |
input port1(6) | (TT) | (FT)
input port2(6) | (TT) | (TF)
expression for output(7) |
input port1(7) | (TT) | (FT)
input port2(7) | (TT) | (TF)
expression for output(8) |
input port1(8) | (TT) | (FT)
input port2(8) | (TT) | (TF)
expression for output(9) |
input port1(9) | (TT) | (FT)
input port2(9) | (TT) | (TF)
expression for output(10) |
input port1(10) | (TT) | (FT)
input port2(10) | (TT) | (TF)
expression for output(11) |
input port1(11) | (TT) | (FT)
input port2(11) | (TT) | (TF)
expression for output(12) |
input port1(12) | (TT) | (FT)
input port2(12) | (TT) | (TF)
expression for output(13) |
input port1(13) | (TT) | (FT)
input port2(13) | (TT) | (TF)
expression for output(14) |
input port1(14) | (TT) | (FT)
input port2(14) | (TT) | (TF)
expression for output(15) |
input port1(15) | (TT) | (FT)
input port2(15) | (TT) | (TF)
expression for output(16) |
input port1(16) | (TT) | (FT)
input port2(16) | (TT) | (TF)
expression for output(17) |
input port1(17) | (TT) | (FT)
input port2(17) | (TT) | (TF)
expression for output(18) |
input port1(18) | (TT) | (FT)
input port2(18) | (TT) | (TF)
expression for output(19) |
input port1(19) | (TT) | (FT)
input port2(19) | (TT) | (TF)
expression for output(20) |
input port1(20) | (TT) | (FT)
input port2(20) | (TT) | (TF)
expression for output(21) |
input port1(21) | (TT) | (FT)
input port2(21) | (TT) | (TF)
expression for output(22) |
input port1(22) | (TT) | (FT)
input port2(22) | (TT) | (TF)
expression for output(23) |
input port1(23) | (TT) | (FT)
input port2(23) | (TT) | (TF)
expression for output(24) |
input port1(24) | (TT) | (FT)
input port2(24) | (TT) | (TF)
expression for output(25) |
input port1(25) | (TT) | (FT)
input port2(25) | (TT) | (TF)
expression for output(26) |
input port1(26) | (TT) | (FT)
input port2(26) | (TT) | (TF)
expression for output(27) |
input port1(27) | (TT) | (FT)
input port2(27) | (TT) | (TF)
expression for output(28) |
input port1(28) | (TT) | (FT)
input port2(28) | (TT) | (TF)
expression for output(29) |
input port1(29) | (TT) | (FT)
input port2(29) | (TT) | (TF)
expression for output(30) |
input port1(30) | (TT) | (FT)
input port2(30) | (TT) | (TF)
expression for output(31) |
input port1(31) | (TT) | (FT)
input port2(31) | (TT) | (TF)
expression for output(32) |
input port1(32) | (TT) | (FT)
input port2(32) | (TT) | (TF)
expression for output(33) |
input port1(33) | (TT) | (FT)
input port2(33) | (TT) | (TF)
expression for output(34) |
input port1(34) | (TT) | (FT)
input port2(34) | (TT) | (TF)
expression for output(35) |
input port1(35) | (TT) | (FT)
input port2(35) | (TT) | (TF)
expression for output(36) |
input port1(36) | (TT) | (FT)
input port2(36) | (TT) | (TF)
expression for output(37) |
input port1(37) | (TT) | (FT)
input port2(37) | (TT) | (TF)
expression for output(38) |
input port1(38) | (TT) | (FT)
input port2(38) | (TT) | (TF)
expression for output(39) |
input port1(39) | (TT) | (FT)
input port2(39) | (TT) | (TF)
expression for output(40) |
input port1(40) | (TT) | (FT)
input port2(40) | (TT) | (TF)
expression for output(41) |
input port1(41) | (TT) | (FT)
input port2(41) | (TT) | (TF)
expression for output(42) |
input port1(42) | (TT) | (FT)
input port2(42) | (TT) | (TF)
expression for output(43) |
input port1(43) | (TT) | (FT)
input port2(43) | (TT) | (TF)
expression for output(44) |
input port1(44) | (TT) | (FT)
input port2(44) | (TT) | (TF)
expression for output(45) |
input port1(45) | (TT) | (FT)
input port2(45) | (TT) | (TF)
expression for output(46) |
input port1(46) | (TT) | (FT)
input port2(46) | (TT) | (TF)
expression for output(47) |
input port1(47) | (TT) | (FT)
input port2(47) | (TT) | (TF)
expression for output(48) |
input port1(48) | (TT) | (FT)
input port2(48) | (TT) | (TF)

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### RelationalOperator block "Comparison4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/96) condition outcomes
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) == input2 | 0 | 0
input1(2) == input2 | 0 | 0
input1(3) == input2 | 0 | 0
input1(4) == input2 | 0 | 0
input1(5) == input2 | 0 | 0
input1(6) == input2 | 0 | 0
input1(7) == input2 | 0 | 0
input1(8) == input2 | 0 | 0
input1(9) == input2 | 0 | 0
input1(10) == input2 | 0 | 0
input1(11) == input2 | 0 | 0
input1(12) == input2 | 0 | 0
input1(13) == input2 | 0 | 0
input1(14) == input2 | 0 | 0
input1(15) == input2 | 0 | 0
input1(16) == input2 | 0 | 0
input1(17) == input2 | 0 | 0
input1(18) == input2 | 0 | 0
input1(19) == input2 | 0 | 0
input1(20) == input2 | 0 | 0
input1(21) == input2 | 0 | 0
input1(22) == input2 | 0 | 0
input1(23) == input2 | 0 | 0
input1(24) == input2 | 0 | 0
input1(25) == input2 | 0 | 0
input1(26) == input2 | 0 | 0
input1(27) == input2 | 0 | 0
input1(28) == input2 | 0 | 0
input1(29) == input2 | 0 | 0
input1(30) == input2 | 0 | 0
input1(31) == input2 | 0 | 0
input1(32) == input2 | 0 | 0
input1(33) == input2 | 0 | 0
input1(34) == input2 | 0 | 0
input1(35) == input2 | 0 | 0
input1(36) == input2 | 0 | 0
input1(37) == input2 | 0 | 0
input1(38) == input2 | 0 | 0
input1(39) == input2 | 0 | 0
input1(40) == input2 | 0 | 0
input1(41) == input2 | 0 | 0
input1(42) == input2 | 0 | 0
input1(43) == input2 | 0 | 0
input1(44) == input2 | 0 | 0
input1(45) == input2 | 0 | 0
input1(46) == input2 | 0 | 0
input1(47) == input2 | 0 | 0
input1(48) == input2 | 0 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution

### 223. SubSystem block "MinBusbarTemp_ForIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys
Child Systems: | MaxBusbarTemp_ForIterator, MinBusbarTemp_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 13
Condition | NA | 0% (0/12) condition outcomes
Decision | NA | 0% (0/18) decision outcomes
MCDC | NA | 0% (0/4) conditions reversed the outcome
Execution | NA | 7% (2/27) objective outcomes

#### ForIterator block "MinBusbarTempNumbIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
loop condition | 0%
false | --
true | --

#### DataTypeConversion block "Data Type Conversion"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### Selector block "Selector1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### Selector block "Selector2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 224. SubSystem block "MaxBusbarTemp_ForIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator
Child Systems: | Unit Delay External IC, Unit Delay External IC2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 0% (0/6) condition outcomes
Decision | NA | 0% (0/8) decision outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 8% (1/12) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MaxBusbarTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 0
input port 2 | 0 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TT) | (FT)
input port 2 | (TT) | (TF)

#### Switch block "Switch2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MaxBusbarTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### Switch block "Switch3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MaxBusbarTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MaxBusbarTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/2) condition outcomes
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 0 | 0

#### UnitDelay block "Unit Delay3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MaxBusbarTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant3" | Execution

### 225. SubSystem block "Unit Delay External IC"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MaxBusbarTemp_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 0% (0/3) objective outcomes

#### Switch block "Init"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MaxBusbarTemp_ForIterator/Unit Delay External IC
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### UnitDelay block "Unit Delay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MaxBusbarTemp_ForIterator/Unit Delay External IC
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MaxBusbarTemp_ForIterator/Unit Delay External IC
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 226. SubSystem block "Unit Delay External IC2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MaxBusbarTemp_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 0% (0/3) objective outcomes

#### Switch block "Init"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MaxBusbarTemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### UnitDelay block "Unit Delay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MaxBusbarTemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MaxBusbarTemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 227. SubSystem block "MinBusbarTemp_ForIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator
Child Systems: | Unit Delay External IC1, Unit Delay External IC2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 0% (0/6) condition outcomes
Decision | NA | 0% (0/8) decision outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 8% (1/12) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MinBusbarTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 0
input port 2 | 0 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TT) | (FT)
input port 2 | (TT) | (TF)

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MinBusbarTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### Switch block "Switch1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MinBusbarTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MinBusbarTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/2) condition outcomes
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 0

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MinBusbarTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant3" | Execution

### 228. SubSystem block "Unit Delay External IC1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MinBusbarTemp_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 0% (0/3) objective outcomes

#### Switch block "Init"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MinBusbarTemp_ForIterator/Unit Delay External IC1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### UnitDelay block "Unit Delay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MinBusbarTemp_ForIterator/Unit Delay External IC1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MinBusbarTemp_ForIterator/Unit Delay External IC1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 229. SubSystem block "Unit Delay External IC2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MinBusbarTemp_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 0% (0/3) objective outcomes

#### Switch block "Init"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MinBusbarTemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### UnitDelay block "Unit Delay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MinBusbarTemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/MaxMin_BusbarTemp_Get_Sys/MinBusbarTemp_ForIterator/MinBusbarTemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 230. SubSystem block "OverWrite"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/OverWrite
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 231. SubSystem block "OverWrite1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/OverWrite1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 232. SubSystem block "OverWrite2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/OverWrite2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 233. SubSystem block "OverWrite3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_BusbarTemp_Get/OverWrite3
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 234. SubSystem block "MaxMin_CMUTemp_Get"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys
Child Systems: | AllCMUPCBTemp_FaultCheck, MaxMin_CMUPCBTemp_Get_Sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 24
Condition | NA | 13% (2/16) condition outcomes
Decision | NA | 10% (3/30) decision outcomes
MCDC | NA | 0% (0/6) conditions reversed the outcome
Execution | NA | 34% (15/44) objective outcomes

### 235. SubSystem block "AllCMUPCBTemp_FaultCheck"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get
Child Systems: | CMUTempVld
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 1
Condition | NA | 50% (2/4) condition outcomes
Decision | NA | 100% (2/2) decision outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 100% (4/4) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant4" | Execution

### 236. SubSystem block "CMUTempVld"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/AllCMUPCBTemp_FaultCheck
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 1
Condition | NA | 50% (2/4) condition outcomes
Decision | NA | 100% (2/2) decision outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 100% (3/3) objective outcomes

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/AllCMUPCBTemp_FaultCheck/CMUTempVld
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 16016
input port 2 | 0 | 16016
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TF) | FF
input port 2 | (FT) | FF

#### Full Coverage

Model Object | Metric
ForIterator block "CMUTemp" | Decision
Selector block "Selector" | Execution
UnitDelay block "Unit Delay1" | Execution

### 237. SubSystem block "MaxMin_CMUPCBTemp_Get_Sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get
Child Systems: | CDP_GcCDP_MaxCMUPCBTempNumb_numb, CDP_GcCDP_MaxCMUPCBTemp_C, CDP_GcCDP_MinCMUPCBTempNumb_numb, CDP_GcCDP_MinCMUPCBTemp_C, MinCMUTemp_ForIterator
Uncovered Links: |
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 2 | 23
Condition | NA | 0% (0/12) condition outcomes
Decision | 50% (1/2) decision outcomes | 4% (1/28) decision outcomes
MCDC | NA | 0% (0/4) conditions reversed the outcome
Execution | NA | 28% (11/40) objective outcomes
Decisions analyzed
enable logical value | 50%
false | 1001/1001
true | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant3" | Execution

### 238. SubSystem block "CDP_GcCDP_MaxCMUPCBTempNumb_numb"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 67% (2/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/CDP_GcCDP_MaxCMUPCBTempNumb_numb
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 239. SubSystem block "CDP_GcCDP_MaxCMUPCBTemp_C"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 67% (2/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/CDP_GcCDP_MaxCMUPCBTemp_C
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 240. SubSystem block "CDP_GcCDP_MinCMUPCBTempNumb_numb"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 67% (2/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/CDP_GcCDP_MinCMUPCBTempNumb_numb
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 241. SubSystem block "CDP_GcCDP_MinCMUPCBTemp_C"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 67% (2/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/CDP_GcCDP_MinCMUPCBTemp_C
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 242. SubSystem block "MinCMUTemp_ForIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys
Child Systems: | MaxCMUTemp_ForIterator, MinCMUTemp_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 13
Condition | NA | 0% (0/12) condition outcomes
Decision | NA | 0% (0/18) decision outcomes
MCDC | NA | 0% (0/4) conditions reversed the outcome
Execution | NA | 7% (2/27) objective outcomes

#### ForIterator block "MinCMUTempNumbIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
loop condition | 0%
false | --
true | --

#### DataTypeConversion block "Data Type Conversion"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### Selector block "Selector1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### Selector block "Selector2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 243. SubSystem block "MaxCMUTemp_ForIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator
Child Systems: | Unit Delay External IC, Unit Delay External IC2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 0% (0/6) condition outcomes
Decision | NA | 0% (0/8) decision outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 8% (1/12) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MaxCMUTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 0
input port 2 | 0 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TT) | (FT)
input port 2 | (TT) | (TF)

#### Switch block "Switch2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MaxCMUTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### Switch block "Switch3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MaxCMUTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MaxCMUTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/2) condition outcomes
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 0 | 0

#### UnitDelay block "Unit Delay3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MaxCMUTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant3" | Execution

### 244. SubSystem block "Unit Delay External IC"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MaxCMUTemp_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 0% (0/3) objective outcomes

#### Switch block "Init"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MaxCMUTemp_ForIterator/Unit Delay External IC
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### UnitDelay block "Unit Delay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MaxCMUTemp_ForIterator/Unit Delay External IC
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MaxCMUTemp_ForIterator/Unit Delay External IC
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 245. SubSystem block "Unit Delay External IC2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MaxCMUTemp_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 0% (0/3) objective outcomes

#### Switch block "Init"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MaxCMUTemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### UnitDelay block "Unit Delay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MaxCMUTemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MaxCMUTemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 246. SubSystem block "MinCMUTemp_ForIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator
Child Systems: | Unit Delay External IC1, Unit Delay External IC2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 0% (0/6) condition outcomes
Decision | NA | 0% (0/8) decision outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 8% (1/12) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MinCMUTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 0
input port 2 | 0 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TT) | (FT)
input port 2 | (TT) | (TF)

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MinCMUTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### Switch block "Switch1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MinCMUTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MinCMUTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/2) condition outcomes
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 0

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MinCMUTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant3" | Execution

### 247. SubSystem block "Unit Delay External IC1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MinCMUTemp_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 0% (0/3) objective outcomes

#### Switch block "Init"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MinCMUTemp_ForIterator/Unit Delay External IC1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### UnitDelay block "Unit Delay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MinCMUTemp_ForIterator/Unit Delay External IC1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MinCMUTemp_ForIterator/Unit Delay External IC1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 248. SubSystem block "Unit Delay External IC2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MinCMUTemp_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 0% (0/3) objective outcomes

#### Switch block "Init"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MinCMUTemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### UnitDelay block "Unit Delay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MinCMUTemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CMUTemp_Get/MaxMin_CMUPCBTemp_Get_Sys/MinCMUTemp_ForIterator/MinCMUTemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 249. SubSystem block "MaxMin_CellTemp_Get"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys
Child Systems: | AllCellTemp_FaultCheck, CellTempMax_SignalFilt, CellTempMin_SignalFilt, MaxMin_CellAvgTemp_Get_Sys, MaxMin_CellTemp_Get_Sys, OverWrite, OverWrite1, OverWrite2, OverWrite3
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 83
Condition | NA | 24% (144/596) condition outcomes
Decision | NA | 39% (41/104) decision outcomes
MCDC | NA | 0% (0/200) conditions reversed the outcome
Execution | NA | 67% (76/114) objective outcomes

### 250. SubSystem block "AllCellTemp_FaultCheck"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get
Child Systems: | CellTempVld, OverWrite
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 4
Condition | NA | 49% (144/296) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
MCDC | NA | 0% (0/100) conditions reversed the outcome
Execution | NA | 62% (8/13) objective outcomes

#### Logic block "Logical"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/AllCellTemp_FaultCheck
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (96/192) condition outcomes
MCDC | 0% (0/96) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 1001 | 0
input port1(2) | 1001 | 0
input port1(3) | 1001 | 0
input port1(4) | 1001 | 0
input port1(5) | 1001 | 0
input port1(6) | 1001 | 0
input port1(7) | 1001 | 0
input port1(8) | 1001 | 0
input port1(9) | 1001 | 0
input port1(10) | 1001 | 0
input port1(11) | 1001 | 0
input port1(12) | 1001 | 0
input port1(13) | 1001 | 0
input port1(14) | 1001 | 0
input port1(15) | 1001 | 0
input port1(16) | 1001 | 0
input port1(17) | 1001 | 0
input port1(18) | 1001 | 0
input port1(19) | 1001 | 0
input port1(20) | 1001 | 0
input port1(21) | 1001 | 0
input port1(22) | 1001 | 0
input port1(23) | 1001 | 0
input port1(24) | 1001 | 0
input port1(25) | 1001 | 0
input port1(26) | 1001 | 0
input port1(27) | 1001 | 0
input port1(28) | 1001 | 0
input port1(29) | 1001 | 0
input port1(30) | 1001 | 0
input port1(31) | 1001 | 0
input port1(32) | 1001 | 0
input port1(33) | 1001 | 0
input port1(34) | 1001 | 0
input port1(35) | 1001 | 0
input port1(36) | 1001 | 0
input port1(37) | 1001 | 0
input port1(38) | 1001 | 0
input port1(39) | 1001 | 0
input port1(40) | 1001 | 0
input port1(41) | 1001 | 0
input port1(42) | 1001 | 0
input port1(43) | 1001 | 0
input port1(44) | 1001 | 0
input port1(45) | 1001 | 0
input port1(46) | 1001 | 0
input port1(47) | 1001 | 0
input port1(48) | 1001 | 0
input port2(1) | 1001 | 0
input port2(2) | 1001 | 0
input port2(3) | 1001 | 0
input port2(4) | 1001 | 0
input port2(5) | 1001 | 0
input port2(6) | 1001 | 0
input port2(7) | 1001 | 0
input port2(8) | 1001 | 0
input port2(9) | 1001 | 0
input port2(10) | 1001 | 0
input port2(11) | 1001 | 0
input port2(12) | 1001 | 0
input port2(13) | 1001 | 0
input port2(14) | 1001 | 0
input port2(15) | 1001 | 0
input port2(16) | 1001 | 0
input port2(17) | 1001 | 0
input port2(18) | 1001 | 0
input port2(19) | 1001 | 0
input port2(20) | 1001 | 0
input port2(21) | 1001 | 0
input port2(22) | 1001 | 0
input port2(23) | 1001 | 0
input port2(24) | 1001 | 0
input port2(25) | 1001 | 0
input port2(26) | 1001 | 0
input port2(27) | 1001 | 0
input port2(28) | 1001 | 0
input port2(29) | 1001 | 0
input port2(30) | 1001 | 0
input port2(31) | 1001 | 0
input port2(32) | 1001 | 0
input port2(33) | 1001 | 0
input port2(34) | 1001 | 0
input port2(35) | 1001 | 0
input port2(36) | 1001 | 0
input port2(37) | 1001 | 0
input port2(38) | 1001 | 0
input port2(39) | 1001 | 0
input port2(40) | 1001 | 0
input port2(41) | 1001 | 0
input port2(42) | 1001 | 0
input port2(43) | 1001 | 0
input port2(44) | 1001 | 0
input port2(45) | 1001 | 0
input port2(46) | 1001 | 0
input port2(47) | 1001 | 0
input port2(48) | 1001 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output(1) |
input port1(1) | TT | (FT)
input port2(1) | TT | (TF)
expression for output(2) |
input port1(2) | TT | (FT)
input port2(2) | TT | (TF)
expression for output(3) |
input port1(3) | TT | (FT)
input port2(3) | TT | (TF)
expression for output(4) |
input port1(4) | TT | (FT)
input port2(4) | TT | (TF)
expression for output(5) |
input port1(5) | TT | (FT)
input port2(5) | TT | (TF)
expression for output(6) |
input port1(6) | TT | (FT)
input port2(6) | TT | (TF)
expression for output(7) |
input port1(7) | TT | (FT)
input port2(7) | TT | (TF)
expression for output(8) |
input port1(8) | TT | (FT)
input port2(8) | TT | (TF)
expression for output(9) |
input port1(9) | TT | (FT)
input port2(9) | TT | (TF)
expression for output(10) |
input port1(10) | TT | (FT)
input port2(10) | TT | (TF)
expression for output(11) |
input port1(11) | TT | (FT)
input port2(11) | TT | (TF)
expression for output(12) |
input port1(12) | TT | (FT)
input port2(12) | TT | (TF)
expression for output(13) |
input port1(13) | TT | (FT)
input port2(13) | TT | (TF)
expression for output(14) |
input port1(14) | TT | (FT)
input port2(14) | TT | (TF)
expression for output(15) |
input port1(15) | TT | (FT)
input port2(15) | TT | (TF)
expression for output(16) |
input port1(16) | TT | (FT)
input port2(16) | TT | (TF)
expression for output(17) |
input port1(17) | TT | (FT)
input port2(17) | TT | (TF)
expression for output(18) |
input port1(18) | TT | (FT)
input port2(18) | TT | (TF)
expression for output(19) |
input port1(19) | TT | (FT)
input port2(19) | TT | (TF)
expression for output(20) |
input port1(20) | TT | (FT)
input port2(20) | TT | (TF)
expression for output(21) |
input port1(21) | TT | (FT)
input port2(21) | TT | (TF)
expression for output(22) |
input port1(22) | TT | (FT)
input port2(22) | TT | (TF)
expression for output(23) |
input port1(23) | TT | (FT)
input port2(23) | TT | (TF)
expression for output(24) |
input port1(24) | TT | (FT)
input port2(24) | TT | (TF)
expression for output(25) |
input port1(25) | TT | (FT)
input port2(25) | TT | (TF)
expression for output(26) |
input port1(26) | TT | (FT)
input port2(26) | TT | (TF)
expression for output(27) |
input port1(27) | TT | (FT)
input port2(27) | TT | (TF)
expression for output(28) |
input port1(28) | TT | (FT)
input port2(28) | TT | (TF)
expression for output(29) |
input port1(29) | TT | (FT)
input port2(29) | TT | (TF)
expression for output(30) |
input port1(30) | TT | (FT)
input port2(30) | TT | (TF)
expression for output(31) |
input port1(31) | TT | (FT)
input port2(31) | TT | (TF)
expression for output(32) |
input port1(32) | TT | (FT)
input port2(32) | TT | (TF)
expression for output(33) |
input port1(33) | TT | (FT)
input port2(33) | TT | (TF)
expression for output(34) |
input port1(34) | TT | (FT)
input port2(34) | TT | (TF)
expression for output(35) |
input port1(35) | TT | (FT)
input port2(35) | TT | (TF)
expression for output(36) |
input port1(36) | TT | (FT)
input port2(36) | TT | (TF)
expression for output(37) |
input port1(37) | TT | (FT)
input port2(37) | TT | (TF)
expression for output(38) |
input port1(38) | TT | (FT)
input port2(38) | TT | (TF)
expression for output(39) |
input port1(39) | TT | (FT)
input port2(39) | TT | (TF)
expression for output(40) |
input port1(40) | TT | (FT)
input port2(40) | TT | (TF)
expression for output(41) |
input port1(41) | TT | (FT)
input port2(41) | TT | (TF)
expression for output(42) |
input port1(42) | TT | (FT)
input port2(42) | TT | (TF)
expression for output(43) |
input port1(43) | TT | (FT)
input port2(43) | TT | (TF)
expression for output(44) |
input port1(44) | TT | (FT)
input port2(44) | TT | (TF)
expression for output(45) |
input port1(45) | TT | (FT)
input port2(45) | TT | (TF)
expression for output(46) |
input port1(46) | TT | (FT)
input port2(46) | TT | (TF)
expression for output(47) |
input port1(47) | TT | (FT)
input port2(47) | TT | (TF)
expression for output(48) |
input port1(48) | TT | (FT)
input port2(48) | TT | (TF)

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/AllCellTemp_FaultCheck
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### RelationalOperator block "Comparison4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/AllCellTemp_FaultCheck
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (48/96) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) == input2 | 1001 | 0
input1(2) == input2 | 1001 | 0
input1(3) == input2 | 1001 | 0
input1(4) == input2 | 1001 | 0
input1(5) == input2 | 1001 | 0
input1(6) == input2 | 1001 | 0
input1(7) == input2 | 1001 | 0
input1(8) == input2 | 1001 | 0
input1(9) == input2 | 1001 | 0
input1(10) == input2 | 1001 | 0
input1(11) == input2 | 1001 | 0
input1(12) == input2 | 1001 | 0
input1(13) == input2 | 1001 | 0
input1(14) == input2 | 1001 | 0
input1(15) == input2 | 1001 | 0
input1(16) == input2 | 1001 | 0
input1(17) == input2 | 1001 | 0
input1(18) == input2 | 1001 | 0
input1(19) == input2 | 1001 | 0
input1(20) == input2 | 1001 | 0
input1(21) == input2 | 1001 | 0
input1(22) == input2 | 1001 | 0
input1(23) == input2 | 1001 | 0
input1(24) == input2 | 1001 | 0
input1(25) == input2 | 1001 | 0
input1(26) == input2 | 1001 | 0
input1(27) == input2 | 1001 | 0
input1(28) == input2 | 1001 | 0
input1(29) == input2 | 1001 | 0
input1(30) == input2 | 1001 | 0
input1(31) == input2 | 1001 | 0
input1(32) == input2 | 1001 | 0
input1(33) == input2 | 1001 | 0
input1(34) == input2 | 1001 | 0
input1(35) == input2 | 1001 | 0
input1(36) == input2 | 1001 | 0
input1(37) == input2 | 1001 | 0
input1(38) == input2 | 1001 | 0
input1(39) == input2 | 1001 | 0
input1(40) == input2 | 1001 | 0
input1(41) == input2 | 1001 | 0
input1(42) == input2 | 1001 | 0
input1(43) == input2 | 1001 | 0
input1(44) == input2 | 1001 | 0
input1(45) == input2 | 1001 | 0
input1(46) == input2 | 1001 | 0
input1(47) == input2 | 1001 | 0
input1(48) == input2 | 1001 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution

### 251. SubSystem block "CellTempVld"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/AllCellTemp_FaultCheck
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 1
Condition | NA | 0% (0/8) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/4) conditions reversed the outcome
Execution | NA | 0% (0/5) objective outcomes

#### ForIterator block "CellTemp"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/AllCellTemp_FaultCheck/CellTempVld
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
loop condition | 50%
false | 1001/1001
true | 0/1001

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/AllCellTemp_FaultCheck/CellTempVld
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 0
input port 2 | 0 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TT) | (FT)
input port 2 | (TT) | (TF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/AllCellTemp_FaultCheck/CellTempVld
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 0
input port 2 | 0 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TF) | (FF)
input port 2 | (FT) | (FF)

#### Selector block "Selector"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/AllCellTemp_FaultCheck/CellTempVld
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/AllCellTemp_FaultCheck/CellTempVld
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/AllCellTemp_FaultCheck/CellTempVld
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 252. SubSystem block "OverWrite"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/AllCellTemp_FaultCheck
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/AllCellTemp_FaultCheck/OverWrite
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 253. SubSystem block "CellTempMax_SignalFilt"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get
Child Systems: | 1D_Config_Word, InputValueCalc, MaxValue_sort, ValueCalc, ValueIndexCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 25
Decision | NA | 52% (16/31) decision outcomes
Execution | NA | 100% (25/25) objective outcomes

#### Full Coverage

Model Object | Metric
UnitDelay block "Unit Delay21" | Execution

### 254. SubSystem block "1D_Config_Word"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt
Child Systems: | Switch Case Action Subsystem, Switch Case Action Subsystem1, Switch Case Action Subsystem2, Switch Case Action Subsystem3, Switch Case Action Subsystem4, Switch Case Action Subsystem5, Switch Case Action Subsystem6, Switch Case Action Subsystem7, Switch Case Action Subsystem8, Switch Case Action Subsystem9
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 11
Decision | NA | 9% (1/11) decision outcomes
Execution | NA | 100% (12/12) objective outcomes

#### SwitchCase block "Switch Case"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/1D_Config_Word
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 10
Decision | 9% (1/11) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
truncated input | 9%
= Enum_UDSCapSel_Default | 1001/1001
= Enum_UDSCapSel_CATL153Ah | 0/1001
= Enum_UDSCapSel_CATL180Ah | 0/1001
= Enum_UDSCapSel_CATL177Ah | 0/1001
= Enum_UDSCapSel_CATL203Ah | 0/1001
= Enum_UDSCapSel_CATL51Ah | 0/1001
= Enum_UDSCapSel_CATL132Ah | 0/1001
= Enum_UDSCapSel_XWD75Ah | 0/1001
= Enum_UDSCapSel_TFE177Ah | 0/1001
= Enum_UDSCapSel_CATLCTP248Ah | 0/1001
= implicit-default | 0/1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution

### 255. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 256. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 257. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 258. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 259. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 260. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 261. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 262. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 263. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 264. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 265. SubSystem block "InputValueCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt
Child Systems: | CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/InputValueCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 4
Decision | NA | 60% (3/5) decision outcomes

### 266. Chart "CellDataPrc_20ms_sys/TempDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/InputValueCalc
Child Systems: | VldValueFilter
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 3
Decision | NA | 60% (3/5) decision outcomes

### 267. State "VldValueFilter"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/InputValueCalc
Uncovered Links: |
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 2 | 3
Decision | 67% (2/3) decision outcomes | 60% (3/5) decision outcomes
Decisions analyzed
Substate exited when parent exits | 67%
State "Default" | 1/1000
State "NotUpdate" | 999/1000
State "Update" | 0/1000

#### Transition "[Rige]" from Junction #0 to Junction #1

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/InputValueCalc.VldValueFilter
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1000/1000
true | 0/1000

### 268. SubSystem block "MaxValue_sort"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt
Child Systems: | CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/MaxValue_sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 6
Decision | NA | 90% (9/10) decision outcomes

### 269. Chart "CellDataPrc_20ms_sys/TempDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/MaxValue_sort
Child Systems: | sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 5
Decision | NA | 90% (9/10) decision outcomes

### 270. State "sort"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/MaxValue_sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 5
Decision | NA | 90% (9/10) decision outcomes

#### Transition "[Output_Value[j] > temp]" from Junction #6 to Junction #5

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1001/1001
true | 0/1001

#### Full Coverage

Model Object | Metric
Transition "[j < Input_dim]" from Junction #13 to Junction #6 | Decision
Transition "[i < Input_dim]" from Junction #10 to Junction #9 | Decision
Transition "[i < Input_dim]" from Junction #15 to Junction #11 | Decision
Transition "[i < Input_dim]" from Junction #4 to Junction #7 | Decision

### 271. SubSystem block "ValueCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (10/10) objective outcomes

#### Full Coverage

Model Object | Metric
Product block "Product1" | Execution
Product block "Product2" | Execution
Sum block "Sum" | Execution
Sum block "Sum1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant4" | Execution
Constant block "Constant6" | Execution
Constant block "Constant7" | Execution
Selector block "Selector" | Execution
Selector block "Selector1" | Execution

### 272. SubSystem block "ValueIndexCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt
Child Systems: | InputValueCalc1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 4
Decision | NA | 60% (3/5) decision outcomes
Execution | NA | 100% (2/2) objective outcomes

#### Full Coverage

Model Object | Metric
Selector block "Selector2" | Execution
UnitDelay block "Unit Delay1" | Execution

### 273. SubSystem block "InputValueCalc1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/ValueIndexCalc
Child Systems: | CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/ValueIndexCalc/InputValueCalc1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 4
Decision | NA | 60% (3/5) decision outcomes

### 274. Chart "CellDataPrc_20ms_sys/TempDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/ValueIndexCalc/InputValueCalc1
Child Systems: | VldValueFilter
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 3
Decision | NA | 60% (3/5) decision outcomes

### 275. State "VldValueFilter"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/ValueIndexCalc/InputValueCalc1
Uncovered Links: |
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 2 | 3
Decision | 67% (2/3) decision outcomes | 60% (3/5) decision outcomes
Decisions analyzed
Substate exited when parent exits | 67%
State "Default" | 1/1000
State "NotUpdate" | 999/1000
State "Update" | 0/1000

#### Transition "[Rige]" from Junction #0 to Junction #1

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMax_SignalFilt/ValueIndexCalc/InputValueCalc1.VldValueFilter
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1000/1000
true | 0/1000

### 276. SubSystem block "CellTempMin_SignalFilt"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get
Child Systems: | 1D_Config_Word, InputValueCalc, MaxValue_sort, ValueCalc, ValueIndexCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 25
Decision | NA | 52% (16/31) decision outcomes
Execution | NA | 100% (25/25) objective outcomes

#### Full Coverage

Model Object | Metric
UnitDelay block "Unit Delay21" | Execution

### 277. SubSystem block "1D_Config_Word"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt
Child Systems: | Switch Case Action Subsystem, Switch Case Action Subsystem1, Switch Case Action Subsystem2, Switch Case Action Subsystem3, Switch Case Action Subsystem4, Switch Case Action Subsystem5, Switch Case Action Subsystem6, Switch Case Action Subsystem7, Switch Case Action Subsystem8, Switch Case Action Subsystem9
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 11
Decision | NA | 9% (1/11) decision outcomes
Execution | NA | 100% (12/12) objective outcomes

#### SwitchCase block "Switch Case"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/1D_Config_Word
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 10
Decision | 9% (1/11) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
truncated input | 9%
= Enum_UDSCapSel_Default | 1001/1001
= Enum_UDSCapSel_CATL153Ah | 0/1001
= Enum_UDSCapSel_CATL180Ah | 0/1001
= Enum_UDSCapSel_CATL177Ah | 0/1001
= Enum_UDSCapSel_CATL203Ah | 0/1001
= Enum_UDSCapSel_CATL51Ah | 0/1001
= Enum_UDSCapSel_CATL132Ah | 0/1001
= Enum_UDSCapSel_XWD75Ah | 0/1001
= Enum_UDSCapSel_TFE177Ah | 0/1001
= Enum_UDSCapSel_CATLCTP248Ah | 0/1001
= implicit-default | 0/1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution

### 278. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 279. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 280. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 281. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 282. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 283. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 284. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 285. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 286. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 287. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 288. SubSystem block "InputValueCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt
Child Systems: | CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/InputValueCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 4
Decision | NA | 60% (3/5) decision outcomes

### 289. Chart "CellDataPrc_20ms_sys/TempDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/InputValueCalc
Child Systems: | VldValueFilter
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 3
Decision | NA | 60% (3/5) decision outcomes

### 290. State "VldValueFilter"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/InputValueCalc
Uncovered Links: |
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 2 | 3
Decision | 67% (2/3) decision outcomes | 60% (3/5) decision outcomes
Decisions analyzed
Substate exited when parent exits | 67%
State "Default" | 1/1000
State "NotUpdate" | 999/1000
State "Update" | 0/1000

#### Transition "[Rige]" from Junction #0 to Junction #1

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/InputValueCalc.VldValueFilter
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1000/1000
true | 0/1000

### 291. SubSystem block "MaxValue_sort"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt
Child Systems: | CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/MaxValue_sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 6
Decision | NA | 90% (9/10) decision outcomes

### 292. Chart "CellDataPrc_20ms_sys/TempDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/MaxValue_sort
Child Systems: | sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 5
Decision | NA | 90% (9/10) decision outcomes

### 293. State "sort"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/MaxValue_sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 5
Decision | NA | 90% (9/10) decision outcomes

#### Transition "[Output_Value[j] > temp]" from Junction #6 to Junction #5

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1001/1001
true | 0/1001

#### Full Coverage

Model Object | Metric
Transition "[j < Input_dim]" from Junction #13 to Junction #6 | Decision
Transition "[i < Input_dim]" from Junction #10 to Junction #9 | Decision
Transition "[i < Input_dim]" from Junction #15 to Junction #11 | Decision
Transition "[i < Input_dim]" from Junction #4 to Junction #7 | Decision

### 294. SubSystem block "ValueCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (10/10) objective outcomes

#### Full Coverage

Model Object | Metric
Product block "Product1" | Execution
Product block "Product2" | Execution
Sum block "Sum" | Execution
Sum block "Sum1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant4" | Execution
Constant block "Constant6" | Execution
Constant block "Constant7" | Execution
Selector block "Selector" | Execution
Selector block "Selector1" | Execution

### 295. SubSystem block "ValueIndexCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt
Child Systems: | InputValueCalc1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 4
Decision | NA | 60% (3/5) decision outcomes
Execution | NA | 100% (2/2) objective outcomes

#### Full Coverage

Model Object | Metric
Selector block "Selector2" | Execution
UnitDelay block "Unit Delay1" | Execution

### 296. SubSystem block "InputValueCalc1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/ValueIndexCalc
Child Systems: | CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/ValueIndexCalc/InputValueCalc1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 4
Decision | NA | 60% (3/5) decision outcomes

### 297. Chart "CellDataPrc_20ms_sys/TempDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/ValueIndexCalc/InputValueCalc1
Child Systems: | VldValueFilter
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 3
Decision | NA | 60% (3/5) decision outcomes

### 298. State "VldValueFilter"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/ValueIndexCalc/InputValueCalc1
Uncovered Links: |
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 2 | 3
Decision | 67% (2/3) decision outcomes | 60% (3/5) decision outcomes
Decisions analyzed
Substate exited when parent exits | 67%
State "Default" | 1/1000
State "NotUpdate" | 999/1000
State "Update" | 0/1000

#### Transition "[Rige]" from Junction #0 to Junction #1

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/CellTempMin_SignalFilt/ValueIndexCalc/InputValueCalc1.VldValueFilter
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1000/1000
true | 0/1000

### 299. SubSystem block "MaxMin_CellAvgTemp_Get_Sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get
Child Systems: | MinCellTemp_ForIterator, OverWrite1
Uncovered Links: |
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 2 | 5
Decision | 50% (1/2) decision outcomes | 17% (1/6) decision outcomes
Execution | NA | 29% (2/7) objective outcomes
Decisions analyzed
enable logical value | 50%
false | 1001/1001
true | 0/1001

#### Product block "Divide1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellAvgTemp_Get_Sys
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 300. SubSystem block "MinCellTemp_ForIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellAvgTemp_Get_Sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 1
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 0% (0/3) objective outcomes

#### ForIterator block "MinCellTempNumbIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellAvgTemp_Get_Sys/MinCellTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
loop condition | 0%
false | --
true | --

#### Sum block "Add"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellAvgTemp_Get_Sys/MinCellTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### Selector block "Selector1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellAvgTemp_Get_Sys/MinCellTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellAvgTemp_Get_Sys/MinCellTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 301. SubSystem block "OverWrite1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellAvgTemp_Get_Sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 67% (2/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellAvgTemp_Get_Sys/OverWrite1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 302. SubSystem block "MaxMin_CellTemp_Get_Sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get
Child Systems: | MinCellTemp_ForIterator
Uncovered Links: |
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 2 | 16
Condition | NA | 0% (0/300) condition outcomes
Decision | 50% (1/2) decision outcomes | 5% (1/22) decision outcomes
MCDC | NA | 0% (0/100) conditions reversed the outcome
Execution | NA | 13% (4/32) objective outcomes
Decisions analyzed
enable logical value | 50%
false | 1001/1001
true | 0/1001

#### Logic block "Logical"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/192) condition outcomes
MCDC | 0% (0/96) conditions reversed the outcome
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 0 | 0
input port1(2) | 0 | 0
input port1(3) | 0 | 0
input port1(4) | 0 | 0
input port1(5) | 0 | 0
input port1(6) | 0 | 0
input port1(7) | 0 | 0
input port1(8) | 0 | 0
input port1(9) | 0 | 0
input port1(10) | 0 | 0
input port1(11) | 0 | 0
input port1(12) | 0 | 0
input port1(13) | 0 | 0
input port1(14) | 0 | 0
input port1(15) | 0 | 0
input port1(16) | 0 | 0
input port1(17) | 0 | 0
input port1(18) | 0 | 0
input port1(19) | 0 | 0
input port1(20) | 0 | 0
input port1(21) | 0 | 0
input port1(22) | 0 | 0
input port1(23) | 0 | 0
input port1(24) | 0 | 0
input port1(25) | 0 | 0
input port1(26) | 0 | 0
input port1(27) | 0 | 0
input port1(28) | 0 | 0
input port1(29) | 0 | 0
input port1(30) | 0 | 0
input port1(31) | 0 | 0
input port1(32) | 0 | 0
input port1(33) | 0 | 0
input port1(34) | 0 | 0
input port1(35) | 0 | 0
input port1(36) | 0 | 0
input port1(37) | 0 | 0
input port1(38) | 0 | 0
input port1(39) | 0 | 0
input port1(40) | 0 | 0
input port1(41) | 0 | 0
input port1(42) | 0 | 0
input port1(43) | 0 | 0
input port1(44) | 0 | 0
input port1(45) | 0 | 0
input port1(46) | 0 | 0
input port1(47) | 0 | 0
input port1(48) | 0 | 0
input port2(1) | 0 | 0
input port2(2) | 0 | 0
input port2(3) | 0 | 0
input port2(4) | 0 | 0
input port2(5) | 0 | 0
input port2(6) | 0 | 0
input port2(7) | 0 | 0
input port2(8) | 0 | 0
input port2(9) | 0 | 0
input port2(10) | 0 | 0
input port2(11) | 0 | 0
input port2(12) | 0 | 0
input port2(13) | 0 | 0
input port2(14) | 0 | 0
input port2(15) | 0 | 0
input port2(16) | 0 | 0
input port2(17) | 0 | 0
input port2(18) | 0 | 0
input port2(19) | 0 | 0
input port2(20) | 0 | 0
input port2(21) | 0 | 0
input port2(22) | 0 | 0
input port2(23) | 0 | 0
input port2(24) | 0 | 0
input port2(25) | 0 | 0
input port2(26) | 0 | 0
input port2(27) | 0 | 0
input port2(28) | 0 | 0
input port2(29) | 0 | 0
input port2(30) | 0 | 0
input port2(31) | 0 | 0
input port2(32) | 0 | 0
input port2(33) | 0 | 0
input port2(34) | 0 | 0
input port2(35) | 0 | 0
input port2(36) | 0 | 0
input port2(37) | 0 | 0
input port2(38) | 0 | 0
input port2(39) | 0 | 0
input port2(40) | 0 | 0
input port2(41) | 0 | 0
input port2(42) | 0 | 0
input port2(43) | 0 | 0
input port2(44) | 0 | 0
input port2(45) | 0 | 0
input port2(46) | 0 | 0
input port2(47) | 0 | 0
input port2(48) | 0 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output(1) |
input port1(1) | (TT) | (FT)
input port2(1) | (TT) | (TF)
expression for output(2) |
input port1(2) | (TT) | (FT)
input port2(2) | (TT) | (TF)
expression for output(3) |
input port1(3) | (TT) | (FT)
input port2(3) | (TT) | (TF)
expression for output(4) |
input port1(4) | (TT) | (FT)
input port2(4) | (TT) | (TF)
expression for output(5) |
input port1(5) | (TT) | (FT)
input port2(5) | (TT) | (TF)
expression for output(6) |
input port1(6) | (TT) | (FT)
input port2(6) | (TT) | (TF)
expression for output(7) |
input port1(7) | (TT) | (FT)
input port2(7) | (TT) | (TF)
expression for output(8) |
input port1(8) | (TT) | (FT)
input port2(8) | (TT) | (TF)
expression for output(9) |
input port1(9) | (TT) | (FT)
input port2(9) | (TT) | (TF)
expression for output(10) |
input port1(10) | (TT) | (FT)
input port2(10) | (TT) | (TF)
expression for output(11) |
input port1(11) | (TT) | (FT)
input port2(11) | (TT) | (TF)
expression for output(12) |
input port1(12) | (TT) | (FT)
input port2(12) | (TT) | (TF)
expression for output(13) |
input port1(13) | (TT) | (FT)
input port2(13) | (TT) | (TF)
expression for output(14) |
input port1(14) | (TT) | (FT)
input port2(14) | (TT) | (TF)
expression for output(15) |
input port1(15) | (TT) | (FT)
input port2(15) | (TT) | (TF)
expression for output(16) |
input port1(16) | (TT) | (FT)
input port2(16) | (TT) | (TF)
expression for output(17) |
input port1(17) | (TT) | (FT)
input port2(17) | (TT) | (TF)
expression for output(18) |
input port1(18) | (TT) | (FT)
input port2(18) | (TT) | (TF)
expression for output(19) |
input port1(19) | (TT) | (FT)
input port2(19) | (TT) | (TF)
expression for output(20) |
input port1(20) | (TT) | (FT)
input port2(20) | (TT) | (TF)
expression for output(21) |
input port1(21) | (TT) | (FT)
input port2(21) | (TT) | (TF)
expression for output(22) |
input port1(22) | (TT) | (FT)
input port2(22) | (TT) | (TF)
expression for output(23) |
input port1(23) | (TT) | (FT)
input port2(23) | (TT) | (TF)
expression for output(24) |
input port1(24) | (TT) | (FT)
input port2(24) | (TT) | (TF)
expression for output(25) |
input port1(25) | (TT) | (FT)
input port2(25) | (TT) | (TF)
expression for output(26) |
input port1(26) | (TT) | (FT)
input port2(26) | (TT) | (TF)
expression for output(27) |
input port1(27) | (TT) | (FT)
input port2(27) | (TT) | (TF)
expression for output(28) |
input port1(28) | (TT) | (FT)
input port2(28) | (TT) | (TF)
expression for output(29) |
input port1(29) | (TT) | (FT)
input port2(29) | (TT) | (TF)
expression for output(30) |
input port1(30) | (TT) | (FT)
input port2(30) | (TT) | (TF)
expression for output(31) |
input port1(31) | (TT) | (FT)
input port2(31) | (TT) | (TF)
expression for output(32) |
input port1(32) | (TT) | (FT)
input port2(32) | (TT) | (TF)
expression for output(33) |
input port1(33) | (TT) | (FT)
input port2(33) | (TT) | (TF)
expression for output(34) |
input port1(34) | (TT) | (FT)
input port2(34) | (TT) | (TF)
expression for output(35) |
input port1(35) | (TT) | (FT)
input port2(35) | (TT) | (TF)
expression for output(36) |
input port1(36) | (TT) | (FT)
input port2(36) | (TT) | (TF)
expression for output(37) |
input port1(37) | (TT) | (FT)
input port2(37) | (TT) | (TF)
expression for output(38) |
input port1(38) | (TT) | (FT)
input port2(38) | (TT) | (TF)
expression for output(39) |
input port1(39) | (TT) | (FT)
input port2(39) | (TT) | (TF)
expression for output(40) |
input port1(40) | (TT) | (FT)
input port2(40) | (TT) | (TF)
expression for output(41) |
input port1(41) | (TT) | (FT)
input port2(41) | (TT) | (TF)
expression for output(42) |
input port1(42) | (TT) | (FT)
input port2(42) | (TT) | (TF)
expression for output(43) |
input port1(43) | (TT) | (FT)
input port2(43) | (TT) | (TF)
expression for output(44) |
input port1(44) | (TT) | (FT)
input port2(44) | (TT) | (TF)
expression for output(45) |
input port1(45) | (TT) | (FT)
input port2(45) | (TT) | (TF)
expression for output(46) |
input port1(46) | (TT) | (FT)
input port2(46) | (TT) | (TF)
expression for output(47) |
input port1(47) | (TT) | (FT)
input port2(47) | (TT) | (TF)
expression for output(48) |
input port1(48) | (TT) | (FT)
input port2(48) | (TT) | (TF)

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### RelationalOperator block "Comparison4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/96) condition outcomes
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) == input2 | 0 | 0
input1(2) == input2 | 0 | 0
input1(3) == input2 | 0 | 0
input1(4) == input2 | 0 | 0
input1(5) == input2 | 0 | 0
input1(6) == input2 | 0 | 0
input1(7) == input2 | 0 | 0
input1(8) == input2 | 0 | 0
input1(9) == input2 | 0 | 0
input1(10) == input2 | 0 | 0
input1(11) == input2 | 0 | 0
input1(12) == input2 | 0 | 0
input1(13) == input2 | 0 | 0
input1(14) == input2 | 0 | 0
input1(15) == input2 | 0 | 0
input1(16) == input2 | 0 | 0
input1(17) == input2 | 0 | 0
input1(18) == input2 | 0 | 0
input1(19) == input2 | 0 | 0
input1(20) == input2 | 0 | 0
input1(21) == input2 | 0 | 0
input1(22) == input2 | 0 | 0
input1(23) == input2 | 0 | 0
input1(24) == input2 | 0 | 0
input1(25) == input2 | 0 | 0
input1(26) == input2 | 0 | 0
input1(27) == input2 | 0 | 0
input1(28) == input2 | 0 | 0
input1(29) == input2 | 0 | 0
input1(30) == input2 | 0 | 0
input1(31) == input2 | 0 | 0
input1(32) == input2 | 0 | 0
input1(33) == input2 | 0 | 0
input1(34) == input2 | 0 | 0
input1(35) == input2 | 0 | 0
input1(36) == input2 | 0 | 0
input1(37) == input2 | 0 | 0
input1(38) == input2 | 0 | 0
input1(39) == input2 | 0 | 0
input1(40) == input2 | 0 | 0
input1(41) == input2 | 0 | 0
input1(42) == input2 | 0 | 0
input1(43) == input2 | 0 | 0
input1(44) == input2 | 0 | 0
input1(45) == input2 | 0 | 0
input1(46) == input2 | 0 | 0
input1(47) == input2 | 0 | 0
input1(48) == input2 | 0 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution

### 303. SubSystem block "MinCellTemp_ForIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys
Child Systems: | MaxCellTemp_ForIterator, MinCellTemp_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 13
Condition | NA | 0% (0/12) condition outcomes
Decision | NA | 0% (0/18) decision outcomes
MCDC | NA | 0% (0/4) conditions reversed the outcome
Execution | NA | 7% (2/27) objective outcomes

#### ForIterator block "MinCellTempNumbIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
loop condition | 0%
false | --
true | --

#### DataTypeConversion block "Data Type Conversion"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### Selector block "Selector1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### Selector block "Selector2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 304. SubSystem block "MaxCellTemp_ForIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator
Child Systems: | Unit Delay External IC, Unit Delay External IC2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 0% (0/6) condition outcomes
Decision | NA | 0% (0/8) decision outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 8% (1/12) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MaxCellTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 0
input port 2 | 0 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TT) | (FT)
input port 2 | (TT) | (TF)

#### Switch block "Switch2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MaxCellTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### Switch block "Switch3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MaxCellTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MaxCellTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/2) condition outcomes
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 0 | 0

#### UnitDelay block "Unit Delay3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MaxCellTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant3" | Execution

### 305. SubSystem block "Unit Delay External IC"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MaxCellTemp_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 0% (0/3) objective outcomes

#### Switch block "Init"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MaxCellTemp_ForIterator/Unit Delay External IC
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### UnitDelay block "Unit Delay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MaxCellTemp_ForIterator/Unit Delay External IC
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MaxCellTemp_ForIterator/Unit Delay External IC
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 306. SubSystem block "Unit Delay External IC2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MaxCellTemp_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 0% (0/3) objective outcomes

#### Switch block "Init"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MaxCellTemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### UnitDelay block "Unit Delay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MaxCellTemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MaxCellTemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 307. SubSystem block "MinCellTemp_ForIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator
Child Systems: | Unit Delay External IC1, Unit Delay External IC2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 0% (0/6) condition outcomes
Decision | NA | 0% (0/8) decision outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 8% (1/12) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MinCellTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 0
input port 2 | 0 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TT) | (FT)
input port 2 | (TT) | (TF)

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MinCellTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### Switch block "Switch1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MinCellTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MinCellTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 0% (0/2) condition outcomes
Execution | 0% (0/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 0

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MinCellTemp_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant3" | Execution

### 308. SubSystem block "Unit Delay External IC1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MinCellTemp_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 0% (0/3) objective outcomes

#### Switch block "Init"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MinCellTemp_ForIterator/Unit Delay External IC1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### UnitDelay block "Unit Delay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MinCellTemp_ForIterator/Unit Delay External IC1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MinCellTemp_ForIterator/Unit Delay External IC1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 309. SubSystem block "Unit Delay External IC2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MinCellTemp_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 0% (0/2) decision outcomes
Execution | NA | 0% (0/3) objective outcomes

#### Switch block "Init"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MinCellTemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Execution | 0% (0/1) objective outcomes
Decisions analyzed
logical trigger input | 0%
false (output is from 3rd input port) | --
true (output is from 1st input port) | --

#### UnitDelay block "Unit Delay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MinCellTemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

#### UnitDelay block "Unit Delay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/MaxMin_CellTemp_Get_Sys/MinCellTemp_ForIterator/MinCellTemp_ForIterator/Unit Delay External IC2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Execution | 0% (0/1) objective outcomes

### 310. SubSystem block "OverWrite"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/OverWrite
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 311. SubSystem block "OverWrite1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/OverWrite1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 312. SubSystem block "OverWrite2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/OverWrite2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 313. SubSystem block "OverWrite3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/MaxMin_CellTemp_Get/OverWrite3
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 314. SubSystem block "NTCTempVld_Output"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys
Child Systems: | OverWrite4
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (98/196) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/96) conditions reversed the outcome
Execution | NA | 100% (10/10) objective outcomes

#### Logic block "Logical Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTempVld_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (49/98) condition outcomes
MCDC | 0% (0/96) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 1001 | 0
input port1(2) | 1001 | 0
input port1(3) | 1001 | 0
input port1(4) | 1001 | 0
input port1(5) | 1001 | 0
input port1(6) | 1001 | 0
input port1(7) | 1001 | 0
input port1(8) | 1001 | 0
input port1(9) | 1001 | 0
input port1(10) | 1001 | 0
input port1(11) | 1001 | 0
input port1(12) | 1001 | 0
input port1(13) | 1001 | 0
input port1(14) | 1001 | 0
input port1(15) | 1001 | 0
input port1(16) | 1001 | 0
input port1(17) | 1001 | 0
input port1(18) | 1001 | 0
input port1(19) | 1001 | 0
input port1(20) | 1001 | 0
input port1(21) | 1001 | 0
input port1(22) | 1001 | 0
input port1(23) | 1001 | 0
input port1(24) | 1001 | 0
input port1(25) | 1001 | 0
input port1(26) | 1001 | 0
input port1(27) | 1001 | 0
input port1(28) | 1001 | 0
input port1(29) | 1001 | 0
input port1(30) | 1001 | 0
input port1(31) | 1001 | 0
input port1(32) | 1001 | 0
input port1(33) | 1001 | 0
input port1(34) | 1001 | 0
input port1(35) | 1001 | 0
input port1(36) | 1001 | 0
input port1(37) | 1001 | 0
input port1(38) | 1001 | 0
input port1(39) | 1001 | 0
input port1(40) | 1001 | 0
input port1(41) | 1001 | 0
input port1(42) | 1001 | 0
input port1(43) | 1001 | 0
input port1(44) | 1001 | 0
input port1(45) | 1001 | 0
input port1(46) | 1001 | 0
input port1(47) | 1001 | 0
input port1(48) | 1001 | 0
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output(1) |
input port1(1) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(2) |
input port1(2) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(3) |
input port1(3) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(4) |
input port1(4) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(5) |
input port1(5) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(6) |
input port1(6) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(7) |
input port1(7) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(8) |
input port1(8) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(9) |
input port1(9) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(10) |
input port1(10) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(11) |
input port1(11) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(12) |
input port1(12) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(13) |
input port1(13) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(14) |
input port1(14) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(15) |
input port1(15) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(16) |
input port1(16) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(17) |
input port1(17) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(18) |
input port1(18) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(19) |
input port1(19) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(20) |
input port1(20) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(21) |
input port1(21) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(22) |
input port1(22) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(23) |
input port1(23) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(24) |
input port1(24) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(25) |
input port1(25) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(26) |
input port1(26) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(27) |
input port1(27) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(28) |
input port1(28) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(29) |
input port1(29) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(30) |
input port1(30) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(31) |
input port1(31) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(32) |
input port1(32) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(33) |
input port1(33) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(34) |
input port1(34) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(35) |
input port1(35) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(36) |
input port1(36) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(37) |
input port1(37) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(38) |
input port1(38) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(39) |
input port1(39) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(40) |
input port1(40) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(41) |
input port1(41) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(42) |
input port1(42) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(43) |
input port1(43) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(44) |
input port1(44) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(45) |
input port1(45) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(46) |
input port1(46) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(47) |
input port1(47) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(48) |
input port1(48) | TF | (FF)
input port 2 | (FT) | (FF)

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTempVld_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTempVld_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (48/96) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) == input2 | 1001 | 0
input1(2) == input2 | 1001 | 0
input1(3) == input2 | 1001 | 0
input1(4) == input2 | 1001 | 0
input1(5) == input2 | 1001 | 0
input1(6) == input2 | 1001 | 0
input1(7) == input2 | 1001 | 0
input1(8) == input2 | 1001 | 0
input1(9) == input2 | 1001 | 0
input1(10) == input2 | 1001 | 0
input1(11) == input2 | 1001 | 0
input1(12) == input2 | 1001 | 0
input1(13) == input2 | 1001 | 0
input1(14) == input2 | 1001 | 0
input1(15) == input2 | 1001 | 0
input1(16) == input2 | 1001 | 0
input1(17) == input2 | 1001 | 0
input1(18) == input2 | 1001 | 0
input1(19) == input2 | 1001 | 0
input1(20) == input2 | 1001 | 0
input1(21) == input2 | 1001 | 0
input1(22) == input2 | 1001 | 0
input1(23) == input2 | 1001 | 0
input1(24) == input2 | 1001 | 0
input1(25) == input2 | 1001 | 0
input1(26) == input2 | 1001 | 0
input1(27) == input2 | 1001 | 0
input1(28) == input2 | 1001 | 0
input1(29) == input2 | 1001 | 0
input1(30) == input2 | 1001 | 0
input1(31) == input2 | 1001 | 0
input1(32) == input2 | 1001 | 0
input1(33) == input2 | 1001 | 0
input1(34) == input2 | 1001 | 0
input1(35) == input2 | 1001 | 0
input1(36) == input2 | 1001 | 0
input1(37) == input2 | 1001 | 0
input1(38) == input2 | 1001 | 0
input1(39) == input2 | 1001 | 0
input1(40) == input2 | 1001 | 0
input1(41) == input2 | 1001 | 0
input1(42) == input2 | 1001 | 0
input1(43) == input2 | 1001 | 0
input1(44) == input2 | 1001 | 0
input1(45) == input2 | 1001 | 0
input1(46) == input2 | 1001 | 0
input1(47) == input2 | 1001 | 0
input1(48) == input2 | 1001 | 0

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution
S-Function block "Bitwise Logical Operator" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution

### 315. SubSystem block "OverWrite4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTempVld_Output
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTempVld_Output/OverWrite4
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 316. SubSystem block "NTCTemp_Output"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys
Child Systems: | CellTemp_SignalFilt, OverWrite2, ValidValueFilter_CellTemp
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 80
Condition | NA | 50% (338/676) condition outcomes
Decision | NA | 45% (64/141) decision outcomes
MCDC | NA | 0% (0/192) conditions reversed the outcome
Execution | NA | 100% (37/37) objective outcomes

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (96/192) condition outcomes
MCDC | 0% (0/96) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 0 | 1001
input port1(2) | 0 | 1001
input port1(3) | 0 | 1001
input port1(4) | 0 | 1001
input port1(5) | 0 | 1001
input port1(6) | 0 | 1001
input port1(7) | 0 | 1001
input port1(8) | 0 | 1001
input port1(9) | 0 | 1001
input port1(10) | 0 | 1001
input port1(11) | 0 | 1001
input port1(12) | 0 | 1001
input port1(13) | 0 | 1001
input port1(14) | 0 | 1001
input port1(15) | 0 | 1001
input port1(16) | 0 | 1001
input port1(17) | 0 | 1001
input port1(18) | 0 | 1001
input port1(19) | 0 | 1001
input port1(20) | 0 | 1001
input port1(21) | 0 | 1001
input port1(22) | 0 | 1001
input port1(23) | 0 | 1001
input port1(24) | 0 | 1001
input port1(25) | 0 | 1001
input port1(26) | 0 | 1001
input port1(27) | 0 | 1001
input port1(28) | 0 | 1001
input port1(29) | 0 | 1001
input port1(30) | 0 | 1001
input port1(31) | 0 | 1001
input port1(32) | 0 | 1001
input port1(33) | 0 | 1001
input port1(34) | 0 | 1001
input port1(35) | 0 | 1001
input port1(36) | 0 | 1001
input port1(37) | 0 | 1001
input port1(38) | 0 | 1001
input port1(39) | 0 | 1001
input port1(40) | 0 | 1001
input port1(41) | 0 | 1001
input port1(42) | 0 | 1001
input port1(43) | 0 | 1001
input port1(44) | 0 | 1001
input port1(45) | 0 | 1001
input port1(46) | 0 | 1001
input port1(47) | 0 | 1001
input port1(48) | 0 | 1001
input port2(1) | 0 | 1001
input port2(2) | 0 | 1001
input port2(3) | 0 | 1001
input port2(4) | 0 | 1001
input port2(5) | 0 | 1001
input port2(6) | 0 | 1001
input port2(7) | 0 | 1001
input port2(8) | 0 | 1001
input port2(9) | 0 | 1001
input port2(10) | 0 | 1001
input port2(11) | 0 | 1001
input port2(12) | 0 | 1001
input port2(13) | 0 | 1001
input port2(14) | 0 | 1001
input port2(15) | 0 | 1001
input port2(16) | 0 | 1001
input port2(17) | 0 | 1001
input port2(18) | 0 | 1001
input port2(19) | 0 | 1001
input port2(20) | 0 | 1001
input port2(21) | 0 | 1001
input port2(22) | 0 | 1001
input port2(23) | 0 | 1001
input port2(24) | 0 | 1001
input port2(25) | 0 | 1001
input port2(26) | 0 | 1001
input port2(27) | 0 | 1001
input port2(28) | 0 | 1001
input port2(29) | 0 | 1001
input port2(30) | 0 | 1001
input port2(31) | 0 | 1001
input port2(32) | 0 | 1001
input port2(33) | 0 | 1001
input port2(34) | 0 | 1001
input port2(35) | 0 | 1001
input port2(36) | 0 | 1001
input port2(37) | 0 | 1001
input port2(38) | 0 | 1001
input port2(39) | 0 | 1001
input port2(40) | 0 | 1001
input port2(41) | 0 | 1001
input port2(42) | 0 | 1001
input port2(43) | 0 | 1001
input port2(44) | 0 | 1001
input port2(45) | 0 | 1001
input port2(46) | 0 | 1001
input port2(47) | 0 | 1001
input port2(48) | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output(1) |
input port1(1) | (TF) | FF
input port2(1) | (FT) | FF
expression for output(2) |
input port1(2) | (TF) | FF
input port2(2) | (FT) | FF
expression for output(3) |
input port1(3) | (TF) | FF
input port2(3) | (FT) | FF
expression for output(4) |
input port1(4) | (TF) | FF
input port2(4) | (FT) | FF
expression for output(5) |
input port1(5) | (TF) | FF
input port2(5) | (FT) | FF
expression for output(6) |
input port1(6) | (TF) | FF
input port2(6) | (FT) | FF
expression for output(7) |
input port1(7) | (TF) | FF
input port2(7) | (FT) | FF
expression for output(8) |
input port1(8) | (TF) | FF
input port2(8) | (FT) | FF
expression for output(9) |
input port1(9) | (TF) | FF
input port2(9) | (FT) | FF
expression for output(10) |
input port1(10) | (TF) | FF
input port2(10) | (FT) | FF
expression for output(11) |
input port1(11) | (TF) | FF
input port2(11) | (FT) | FF
expression for output(12) |
input port1(12) | (TF) | FF
input port2(12) | (FT) | FF
expression for output(13) |
input port1(13) | (TF) | FF
input port2(13) | (FT) | FF
expression for output(14) |
input port1(14) | (TF) | FF
input port2(14) | (FT) | FF
expression for output(15) |
input port1(15) | (TF) | FF
input port2(15) | (FT) | FF
expression for output(16) |
input port1(16) | (TF) | FF
input port2(16) | (FT) | FF
expression for output(17) |
input port1(17) | (TF) | FF
input port2(17) | (FT) | FF
expression for output(18) |
input port1(18) | (TF) | FF
input port2(18) | (FT) | FF
expression for output(19) |
input port1(19) | (TF) | FF
input port2(19) | (FT) | FF
expression for output(20) |
input port1(20) | (TF) | FF
input port2(20) | (FT) | FF
expression for output(21) |
input port1(21) | (TF) | FF
input port2(21) | (FT) | FF
expression for output(22) |
input port1(22) | (TF) | FF
input port2(22) | (FT) | FF
expression for output(23) |
input port1(23) | (TF) | FF
input port2(23) | (FT) | FF
expression for output(24) |
input port1(24) | (TF) | FF
input port2(24) | (FT) | FF
expression for output(25) |
input port1(25) | (TF) | FF
input port2(25) | (FT) | FF
expression for output(26) |
input port1(26) | (TF) | FF
input port2(26) | (FT) | FF
expression for output(27) |
input port1(27) | (TF) | FF
input port2(27) | (FT) | FF
expression for output(28) |
input port1(28) | (TF) | FF
input port2(28) | (FT) | FF
expression for output(29) |
input port1(29) | (TF) | FF
input port2(29) | (FT) | FF
expression for output(30) |
input port1(30) | (TF) | FF
input port2(30) | (FT) | FF
expression for output(31) |
input port1(31) | (TF) | FF
input port2(31) | (FT) | FF
expression for output(32) |
input port1(32) | (TF) | FF
input port2(32) | (FT) | FF
expression for output(33) |
input port1(33) | (TF) | FF
input port2(33) | (FT) | FF
expression for output(34) |
input port1(34) | (TF) | FF
input port2(34) | (FT) | FF
expression for output(35) |
input port1(35) | (TF) | FF
input port2(35) | (FT) | FF
expression for output(36) |
input port1(36) | (TF) | FF
input port2(36) | (FT) | FF
expression for output(37) |
input port1(37) | (TF) | FF
input port2(37) | (FT) | FF
expression for output(38) |
input port1(38) | (TF) | FF
input port2(38) | (FT) | FF
expression for output(39) |
input port1(39) | (TF) | FF
input port2(39) | (FT) | FF
expression for output(40) |
input port1(40) | (TF) | FF
input port2(40) | (FT) | FF
expression for output(41) |
input port1(41) | (TF) | FF
input port2(41) | (FT) | FF
expression for output(42) |
input port1(42) | (TF) | FF
input port2(42) | (FT) | FF
expression for output(43) |
input port1(43) | (TF) | FF
input port2(43) | (FT) | FF
expression for output(44) |
input port1(44) | (TF) | FF
input port2(44) | (FT) | FF
expression for output(45) |
input port1(45) | (TF) | FF
input port2(45) | (FT) | FF
expression for output(46) |
input port1(46) | (TF) | FF
input port2(46) | (FT) | FF
expression for output(47) |
input port1(47) | (TF) | FF
input port2(47) | (FT) | FF
expression for output(48) |
input port1(48) | (TF) | FF
input port2(48) | (FT) | FF

#### Logic block "Logical Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (49/98) condition outcomes
MCDC | 0% (0/96) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 0 | 1001
input port1(2) | 0 | 1001
input port1(3) | 0 | 1001
input port1(4) | 0 | 1001
input port1(5) | 0 | 1001
input port1(6) | 0 | 1001
input port1(7) | 0 | 1001
input port1(8) | 0 | 1001
input port1(9) | 0 | 1001
input port1(10) | 0 | 1001
input port1(11) | 0 | 1001
input port1(12) | 0 | 1001
input port1(13) | 0 | 1001
input port1(14) | 0 | 1001
input port1(15) | 0 | 1001
input port1(16) | 0 | 1001
input port1(17) | 0 | 1001
input port1(18) | 0 | 1001
input port1(19) | 0 | 1001
input port1(20) | 0 | 1001
input port1(21) | 0 | 1001
input port1(22) | 0 | 1001
input port1(23) | 0 | 1001
input port1(24) | 0 | 1001
input port1(25) | 0 | 1001
input port1(26) | 0 | 1001
input port1(27) | 0 | 1001
input port1(28) | 0 | 1001
input port1(29) | 0 | 1001
input port1(30) | 0 | 1001
input port1(31) | 0 | 1001
input port1(32) | 0 | 1001
input port1(33) | 0 | 1001
input port1(34) | 0 | 1001
input port1(35) | 0 | 1001
input port1(36) | 0 | 1001
input port1(37) | 0 | 1001
input port1(38) | 0 | 1001
input port1(39) | 0 | 1001
input port1(40) | 0 | 1001
input port1(41) | 0 | 1001
input port1(42) | 0 | 1001
input port1(43) | 0 | 1001
input port1(44) | 0 | 1001
input port1(45) | 0 | 1001
input port1(46) | 0 | 1001
input port1(47) | 0 | 1001
input port1(48) | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output(1) |
input port1(1) | (TF) | FF
input port 2 | (FT) | FF
expression for output(2) |
input port1(2) | (TF) | FF
input port 2 | (FT) | FF
expression for output(3) |
input port1(3) | (TF) | FF
input port 2 | (FT) | FF
expression for output(4) |
input port1(4) | (TF) | FF
input port 2 | (FT) | FF
expression for output(5) |
input port1(5) | (TF) | FF
input port 2 | (FT) | FF
expression for output(6) |
input port1(6) | (TF) | FF
input port 2 | (FT) | FF
expression for output(7) |
input port1(7) | (TF) | FF
input port 2 | (FT) | FF
expression for output(8) |
input port1(8) | (TF) | FF
input port 2 | (FT) | FF
expression for output(9) |
input port1(9) | (TF) | FF
input port 2 | (FT) | FF
expression for output(10) |
input port1(10) | (TF) | FF
input port 2 | (FT) | FF
expression for output(11) |
input port1(11) | (TF) | FF
input port 2 | (FT) | FF
expression for output(12) |
input port1(12) | (TF) | FF
input port 2 | (FT) | FF
expression for output(13) |
input port1(13) | (TF) | FF
input port 2 | (FT) | FF
expression for output(14) |
input port1(14) | (TF) | FF
input port 2 | (FT) | FF
expression for output(15) |
input port1(15) | (TF) | FF
input port 2 | (FT) | FF
expression for output(16) |
input port1(16) | (TF) | FF
input port 2 | (FT) | FF
expression for output(17) |
input port1(17) | (TF) | FF
input port 2 | (FT) | FF
expression for output(18) |
input port1(18) | (TF) | FF
input port 2 | (FT) | FF
expression for output(19) |
input port1(19) | (TF) | FF
input port 2 | (FT) | FF
expression for output(20) |
input port1(20) | (TF) | FF
input port 2 | (FT) | FF
expression for output(21) |
input port1(21) | (TF) | FF
input port 2 | (FT) | FF
expression for output(22) |
input port1(22) | (TF) | FF
input port 2 | (FT) | FF
expression for output(23) |
input port1(23) | (TF) | FF
input port 2 | (FT) | FF
expression for output(24) |
input port1(24) | (TF) | FF
input port 2 | (FT) | FF
expression for output(25) |
input port1(25) | (TF) | FF
input port 2 | (FT) | FF
expression for output(26) |
input port1(26) | (TF) | FF
input port 2 | (FT) | FF
expression for output(27) |
input port1(27) | (TF) | FF
input port 2 | (FT) | FF
expression for output(28) |
input port1(28) | (TF) | FF
input port 2 | (FT) | FF
expression for output(29) |
input port1(29) | (TF) | FF
input port 2 | (FT) | FF
expression for output(30) |
input port1(30) | (TF) | FF
input port 2 | (FT) | FF
expression for output(31) |
input port1(31) | (TF) | FF
input port 2 | (FT) | FF
expression for output(32) |
input port1(32) | (TF) | FF
input port 2 | (FT) | FF
expression for output(33) |
input port1(33) | (TF) | FF
input port 2 | (FT) | FF
expression for output(34) |
input port1(34) | (TF) | FF
input port 2 | (FT) | FF
expression for output(35) |
input port1(35) | (TF) | FF
input port 2 | (FT) | FF
expression for output(36) |
input port1(36) | (TF) | FF
input port 2 | (FT) | FF
expression for output(37) |
input port1(37) | (TF) | FF
input port 2 | (FT) | FF
expression for output(38) |
input port1(38) | (TF) | FF
input port 2 | (FT) | FF
expression for output(39) |
input port1(39) | (TF) | FF
input port 2 | (FT) | FF
expression for output(40) |
input port1(40) | (TF) | FF
input port 2 | (FT) | FF
expression for output(41) |
input port1(41) | (TF) | FF
input port 2 | (FT) | FF
expression for output(42) |
input port1(42) | (TF) | FF
input port 2 | (FT) | FF
expression for output(43) |
input port1(43) | (TF) | FF
input port 2 | (FT) | FF
expression for output(44) |
input port1(44) | (TF) | FF
input port 2 | (FT) | FF
expression for output(45) |
input port1(45) | (TF) | FF
input port 2 | (FT) | FF
expression for output(46) |
input port1(46) | (TF) | FF
input port 2 | (FT) | FF
expression for output(47) |
input port1(47) | (TF) | FF
input port 2 | (FT) | FF
expression for output(48) |
input port1(48) | (TF) | FF
input port 2 | (FT) | FF

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 48
Decision | 50% (48/96) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input(1) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(2) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(3) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(4) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(5) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(6) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(7) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(8) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(9) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(10) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(11) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(12) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(13) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(14) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(15) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(16) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(17) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(18) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(19) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(20) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(21) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(22) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(23) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(24) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(25) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(26) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(27) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(28) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(29) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(30) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(31) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(32) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(33) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(34) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(35) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(36) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(37) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(38) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(39) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(40) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(41) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(42) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(43) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(44) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(45) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(46) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(47) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(48) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Switch block "Switch1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### RelationalOperator block "Comparison1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (48/96) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) == input2 | 0 | 1001
input1(2) == input2 | 0 | 1001
input1(3) == input2 | 0 | 1001
input1(4) == input2 | 0 | 1001
input1(5) == input2 | 0 | 1001
input1(6) == input2 | 0 | 1001
input1(7) == input2 | 0 | 1001
input1(8) == input2 | 0 | 1001
input1(9) == input2 | 0 | 1001
input1(10) == input2 | 0 | 1001
input1(11) == input2 | 0 | 1001
input1(12) == input2 | 0 | 1001
input1(13) == input2 | 0 | 1001
input1(14) == input2 | 0 | 1001
input1(15) == input2 | 0 | 1001
input1(16) == input2 | 0 | 1001
input1(17) == input2 | 0 | 1001
input1(18) == input2 | 0 | 1001
input1(19) == input2 | 0 | 1001
input1(20) == input2 | 0 | 1001
input1(21) == input2 | 0 | 1001
input1(22) == input2 | 0 | 1001
input1(23) == input2 | 0 | 1001
input1(24) == input2 | 0 | 1001
input1(25) == input2 | 0 | 1001
input1(26) == input2 | 0 | 1001
input1(27) == input2 | 0 | 1001
input1(28) == input2 | 0 | 1001
input1(29) == input2 | 0 | 1001
input1(30) == input2 | 0 | 1001
input1(31) == input2 | 0 | 1001
input1(32) == input2 | 0 | 1001
input1(33) == input2 | 0 | 1001
input1(34) == input2 | 0 | 1001
input1(35) == input2 | 0 | 1001
input1(36) == input2 | 0 | 1001
input1(37) == input2 | 0 | 1001
input1(38) == input2 | 0 | 1001
input1(39) == input2 | 0 | 1001
input1(40) == input2 | 0 | 1001
input1(41) == input2 | 0 | 1001
input1(42) == input2 | 0 | 1001
input1(43) == input2 | 0 | 1001
input1(44) == input2 | 0 | 1001
input1(45) == input2 | 0 | 1001
input1(46) == input2 | 0 | 1001
input1(47) == input2 | 0 | 1001
input1(48) == input2 | 0 | 1001

#### RelationalOperator block "Comparison4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (48/96) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) == input2 | 1001 | 0
input1(2) == input2 | 1001 | 0
input1(3) == input2 | 1001 | 0
input1(4) == input2 | 1001 | 0
input1(5) == input2 | 1001 | 0
input1(6) == input2 | 1001 | 0
input1(7) == input2 | 1001 | 0
input1(8) == input2 | 1001 | 0
input1(9) == input2 | 1001 | 0
input1(10) == input2 | 1001 | 0
input1(11) == input2 | 1001 | 0
input1(12) == input2 | 1001 | 0
input1(13) == input2 | 1001 | 0
input1(14) == input2 | 1001 | 0
input1(15) == input2 | 1001 | 0
input1(16) == input2 | 1001 | 0
input1(17) == input2 | 1001 | 0
input1(18) == input2 | 1001 | 0
input1(19) == input2 | 1001 | 0
input1(20) == input2 | 1001 | 0
input1(21) == input2 | 1001 | 0
input1(22) == input2 | 1001 | 0
input1(23) == input2 | 1001 | 0
input1(24) == input2 | 1001 | 0
input1(25) == input2 | 1001 | 0
input1(26) == input2 | 1001 | 0
input1(27) == input2 | 1001 | 0
input1(28) == input2 | 1001 | 0
input1(29) == input2 | 1001 | 0
input1(30) == input2 | 1001 | 0
input1(31) == input2 | 1001 | 0
input1(32) == input2 | 1001 | 0
input1(33) == input2 | 1001 | 0
input1(34) == input2 | 1001 | 0
input1(35) == input2 | 1001 | 0
input1(36) == input2 | 1001 | 0
input1(37) == input2 | 1001 | 0
input1(38) == input2 | 1001 | 0
input1(39) == input2 | 1001 | 0
input1(40) == input2 | 1001 | 0
input1(41) == input2 | 1001 | 0
input1(42) == input2 | 1001 | 0
input1(43) == input2 | 1001 | 0
input1(44) == input2 | 1001 | 0
input1(45) == input2 | 1001 | 0
input1(46) == input2 | 1001 | 0
input1(47) == input2 | 1001 | 0
input1(48) == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (48/96) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) ~= input2 | 0 | 1001
input1(2) ~= input2 | 0 | 1001
input1(3) ~= input2 | 0 | 1001
input1(4) ~= input2 | 0 | 1001
input1(5) ~= input2 | 0 | 1001
input1(6) ~= input2 | 0 | 1001
input1(7) ~= input2 | 0 | 1001
input1(8) ~= input2 | 0 | 1001
input1(9) ~= input2 | 0 | 1001
input1(10) ~= input2 | 0 | 1001
input1(11) ~= input2 | 0 | 1001
input1(12) ~= input2 | 0 | 1001
input1(13) ~= input2 | 0 | 1001
input1(14) ~= input2 | 0 | 1001
input1(15) ~= input2 | 0 | 1001
input1(16) ~= input2 | 0 | 1001
input1(17) ~= input2 | 0 | 1001
input1(18) ~= input2 | 0 | 1001
input1(19) ~= input2 | 0 | 1001
input1(20) ~= input2 | 0 | 1001
input1(21) ~= input2 | 0 | 1001
input1(22) ~= input2 | 0 | 1001
input1(23) ~= input2 | 0 | 1001
input1(24) ~= input2 | 0 | 1001
input1(25) ~= input2 | 0 | 1001
input1(26) ~= input2 | 0 | 1001
input1(27) ~= input2 | 0 | 1001
input1(28) ~= input2 | 0 | 1001
input1(29) ~= input2 | 0 | 1001
input1(30) ~= input2 | 0 | 1001
input1(31) ~= input2 | 0 | 1001
input1(32) ~= input2 | 0 | 1001
input1(33) ~= input2 | 0 | 1001
input1(34) ~= input2 | 0 | 1001
input1(35) ~= input2 | 0 | 1001
input1(36) ~= input2 | 0 | 1001
input1(37) ~= input2 | 0 | 1001
input1(38) ~= input2 | 0 | 1001
input1(39) ~= input2 | 0 | 1001
input1(40) ~= input2 | 0 | 1001
input1(41) ~= input2 | 0 | 1001
input1(42) ~= input2 | 0 | 1001
input1(43) ~= input2 | 0 | 1001
input1(44) ~= input2 | 0 | 1001
input1(45) ~= input2 | 0 | 1001
input1(46) ~= input2 | 0 | 1001
input1(47) ~= input2 | 0 | 1001
input1(48) ~= input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Lookup_n-D block "1-D Lookup Table" | Execution
DataTypeConversion block "Data Type Conversion" | Execution
DataTypeConversion block "Data Type Conversion1" | Execution
S-Function block "Bitwise Logical Operator" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution
Constant block "Constant5" | Execution
Constant block "Constant6" | Execution
UnitDelay block "Unit Delay" | Execution

### 317. SubSystem block "CellTemp_SignalFilt"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output
Child Systems: | 1D_Config_Word, InputValueCalc, MaxValue_sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 26
Condition | NA | 50% (48/96) condition outcomes
Decision | NA | 30% (11/37) decision outcomes
Execution | NA | 100% (15/15) objective outcomes

#### RelationalOperator block "Comparison1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (48/96) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) == input2 | 1001 | 0
input1(2) == input2 | 1001 | 0
input1(3) == input2 | 1001 | 0
input1(4) == input2 | 1001 | 0
input1(5) == input2 | 1001 | 0
input1(6) == input2 | 1001 | 0
input1(7) == input2 | 1001 | 0
input1(8) == input2 | 1001 | 0
input1(9) == input2 | 1001 | 0
input1(10) == input2 | 1001 | 0
input1(11) == input2 | 1001 | 0
input1(12) == input2 | 1001 | 0
input1(13) == input2 | 1001 | 0
input1(14) == input2 | 1001 | 0
input1(15) == input2 | 1001 | 0
input1(16) == input2 | 1001 | 0
input1(17) == input2 | 1001 | 0
input1(18) == input2 | 1001 | 0
input1(19) == input2 | 1001 | 0
input1(20) == input2 | 1001 | 0
input1(21) == input2 | 1001 | 0
input1(22) == input2 | 1001 | 0
input1(23) == input2 | 1001 | 0
input1(24) == input2 | 1001 | 0
input1(25) == input2 | 1001 | 0
input1(26) == input2 | 1001 | 0
input1(27) == input2 | 1001 | 0
input1(28) == input2 | 1001 | 0
input1(29) == input2 | 1001 | 0
input1(30) == input2 | 1001 | 0
input1(31) == input2 | 1001 | 0
input1(32) == input2 | 1001 | 0
input1(33) == input2 | 1001 | 0
input1(34) == input2 | 1001 | 0
input1(35) == input2 | 1001 | 0
input1(36) == input2 | 1001 | 0
input1(37) == input2 | 1001 | 0
input1(38) == input2 | 1001 | 0
input1(39) == input2 | 1001 | 0
input1(40) == input2 | 1001 | 0
input1(41) == input2 | 1001 | 0
input1(42) == input2 | 1001 | 0
input1(43) == input2 | 1001 | 0
input1(44) == input2 | 1001 | 0
input1(45) == input2 | 1001 | 0
input1(46) == input2 | 1001 | 0
input1(47) == input2 | 1001 | 0
input1(48) == input2 | 1001 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant6" | Execution
UnitDelay block "Unit Delay21" | Execution

### 318. SubSystem block "1D_Config_Word"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt
Child Systems: | Switch Case Action Subsystem, Switch Case Action Subsystem1, Switch Case Action Subsystem2, Switch Case Action Subsystem3, Switch Case Action Subsystem4, Switch Case Action Subsystem5, Switch Case Action Subsystem6, Switch Case Action Subsystem7, Switch Case Action Subsystem8, Switch Case Action Subsystem9
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 11
Decision | NA | 9% (1/11) decision outcomes
Execution | NA | 100% (12/12) objective outcomes

#### SwitchCase block "Switch Case"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/1D_Config_Word
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 10
Decision | 9% (1/11) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
truncated input | 9%
= Enum_UDSCapSel_Default | 1001/1001
= Enum_UDSCapSel_CATL153Ah | 0/1001
= Enum_UDSCapSel_CATL180Ah | 0/1001
= Enum_UDSCapSel_CATL177Ah | 0/1001
= Enum_UDSCapSel_CATL203Ah | 0/1001
= Enum_UDSCapSel_CATL51Ah | 0/1001
= Enum_UDSCapSel_CATL132Ah | 0/1001
= Enum_UDSCapSel_XWD75Ah | 0/1001
= Enum_UDSCapSel_TFE177Ah | 0/1001
= Enum_UDSCapSel_CATLCTP248Ah | 0/1001
= implicit-default | 0/1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution

### 319. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 320. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 321. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 322. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 323. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 324. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 325. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 326. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 327. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 328. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 329. SubSystem block "InputValueCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt
Child Systems: | CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/InputValueCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 6
Decision | NA | 50% (5/10) decision outcomes

### 330. Chart "CellDataPrc_20ms_sys/TempDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/InputValueCalc
Child Systems: | Default, Update
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 5
Decision | 100% (2/2) decision outcomes | 50% (5/10) decision outcomes
Decisions analyzed
Substate executed | 100%
State "Default" | 1/1000
State "Update" | 999/1000

#### Transition "[i >Input_num-1]" from "Default" to "Update"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/InputValueCalc
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 0/1
true | 1/1

### 331. State "Default"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/InputValueCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 1
Decision | NA | 50% (1/2) decision outcomes

#### Transition "[i <Input_num]" from Junction #8 to Junction #9

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/InputValueCalc.Default
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1/1
true | 0/1

### 332. State "Update"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/InputValueCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Decision | NA | 25% (1/4) decision outcomes

#### Transition "[i < Input_num]" from Junction #1 to Junction #2

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/InputValueCalc.Update
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1000/1000
true | 0/1000

#### Transition "[Update[i]]" from Junction #2 to Junction #3

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/InputValueCalc.Update
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
Transition trigger expression | 0%
false | --
true | --

### 333. SubSystem block "MaxValue_sort"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt
Child Systems: | CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/MaxValue_sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 9
Decision | NA | 31% (5/16) decision outcomes

### 334. Chart "CellDataPrc_20ms_sys/TempDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/MaxValue_sort
Child Systems: | sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 8
Decision | NA | 31% (5/16) decision outcomes

### 335. State "sort"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/MaxValue_sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 8
Decision | NA | 31% (5/16) decision outcomes

#### Transition "[m >= 1]" from Junction #11 to Junction #3

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
Transition trigger expression | 0%
false | --
true | --

#### Transition "[j < Input_num]" from Junction #5 to Junction #9

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1001/1001
true | 0/1001

#### Transition "[k<Input_num]" from Junction #4 to Junction #12

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
Transition trigger expression | 0%
false | --
true | --

#### Transition "[Output_Value[n][k] > Output_Value[m][k]..." from Junction #17 to Junction #14

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
Transition trigger expression | 0%
false | --
true | --

#### Transition "[n>=0]" from Junction #7 to Junction #17

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
Transition trigger expression | 0%
false | --
true | --

#### Transition "[k<Input_num]" from Junction #19 to Junction #20

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1001/1001
true | 0/1001

#### Transition "[Input_dim == 1]" from Junction #24 to Junction #23

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/CellTemp_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 0/1001
true | 1001/1001

#### Full Coverage

Model Object | Metric
Transition "[i < Input_dim]" from Junction #8 to Junction #5 | Decision

### 336. SubSystem block "OverWrite2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/OverWrite2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 337. SubSystem block "ValidValueFilter_CellTemp"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output
Child Systems: | CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/ValidValueFilter_CellTemp
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 3
Decision | NA | 75% (3/4) decision outcomes

### 338. Chart "CellDataPrc_20ms_sys/TempDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/ValidValueFilter_CellTemp
Child Systems: | VldValueFilter
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Decision | NA | 75% (3/4) decision outcomes

### 339. State "VldValueFilter"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/ValidValueFilter_CellTemp
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Decision | NA | 75% (3/4) decision outcomes

#### Transition "[i < NumbConfig]" from Junction #2 to Junction #3

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempDataPrc_20ms_sys/NTCTemp_Output/ValidValueFilter_CellTemp.VldValueFilter
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 48048/48048
true | 0/48048

#### Full Coverage

Model Object | Metric
Transition "[i < InputNumb]" from Junction #1 to Junction #2 | Decision

### 340. SubSystem block "TempFltDet"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys
Child Systems: | BusbarTempDiffFltDet, BusbarTempHiFltDet, BusbarTempLowFltDet, BusbarTempRngFltDet, CellTempDiffFltDet, CellTempHiFltDet, CellTempHiFltDet_Chrg, CellTempLowFltDet, CellTempLowFlt_Chrg, CellTempRngFltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 52
Condition | NA | 50% (231/462) condition outcomes
Decision | NA | 50% (26/52) decision outcomes
MCDC | NA | 0% (0/104) conditions reversed the outcome
Execution | NA | 100% (438/438) objective outcomes

### 341. SubSystem block "BusbarTempDiffFltDet"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet
Child Systems: | BusbarTempDiffFltDet_Sys, DiffTempCheck_Condition
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 4
Condition | NA | 50% (22/44) condition outcomes
Decision | NA | 50% (2/4) decision outcomes
MCDC | NA | 0% (0/11) conditions reversed the outcome
Execution | NA | 100% (37/37) objective outcomes

### 342. SubSystem block "BusbarTempDiffFltDet_Sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet
Child Systems: | BusbarTempDiffFltLv1Det, BusbarTempDiffFltLv2Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 4
Condition | NA | 50% (18/36) condition outcomes
Decision | NA | 50% (2/4) decision outcomes
MCDC | NA | 0% (0/9) conditions reversed the outcome
Execution | NA | 100% (31/31) objective outcomes

#### Full Coverage

Model Object | Metric
Sum block "Add" | Execution

### 343. SubSystem block "BusbarTempDiffFltLv1Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet/BusbarTempDiffFltDet_Sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (10/20) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/5) conditions reversed the outcome
Execution | NA | 100% (16/16) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet/BusbarTempDiffFltDet_Sys/BusbarTempDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (4/8) condition outcomes
MCDC | 0% (0/5) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 1001 | 0
input port 3 | 1001 | 0
input port 4 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(((C1 && C2) && C3) && C4) && C5 |
C1 (Logical Operator1 In1) | (TTTTT) | (FTTTT)
C2 (Logical Operator1 In2) | (TTTTT) | (TFTTT)
C3 (Logical Operator In2) | (TTTTT) | (TTFTT)
C4 (Logical Operator In3) | (TTTTT) | (TTTFT)
C5 (Logical Operator In4) | (TTTTT) | (TTTTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet/BusbarTempDiffFltDet_Sys/BusbarTempDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet/BusbarTempDiffFltDet_Sys/BusbarTempDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet/BusbarTempDiffFltDet_Sys/BusbarTempDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet/BusbarTempDiffFltDet_Sys/BusbarTempDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet/BusbarTempDiffFltDet_Sys/BusbarTempDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution
Constant block "Constant7" | Execution

### 344. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet/BusbarTempDiffFltDet_Sys/BusbarTempDiffFltLv1Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet/BusbarTempDiffFltDet_Sys/BusbarTempDiffFltLv1Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 345. SubSystem block "BusbarTempDiffFltLv2Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet/BusbarTempDiffFltDet_Sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (8/16) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/4) conditions reversed the outcome
Execution | NA | 100% (14/14) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet/BusbarTempDiffFltDet_Sys/BusbarTempDiffFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (4/8) condition outcomes
MCDC | 0% (0/4) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 1001 | 0
input port 3 | 1001 | 0
input port 4 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TTTT) | (FTTT)
input port 2 | (TTTT) | (TFTT)
input port 3 | (TTTT) | (TTFT)
input port 4 | (TTTT) | (TTTF)

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet/BusbarTempDiffFltDet_Sys/BusbarTempDiffFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet/BusbarTempDiffFltDet_Sys/BusbarTempDiffFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet/BusbarTempDiffFltDet_Sys/BusbarTempDiffFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet/BusbarTempDiffFltDet_Sys/BusbarTempDiffFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution

### 346. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet/BusbarTempDiffFltDet_Sys/BusbarTempDiffFltLv2Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet/BusbarTempDiffFltDet_Sys/BusbarTempDiffFltLv2Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 347. SubSystem block "DiffTempCheck_Condition"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Condition | NA | 50% (4/8) condition outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 100% (6/6) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet/DiffTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 1001 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TT) | FT
input port 2 | (TT) | (TF)

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet/DiffTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempDiffFltDet/DiffTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 2 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution

### 348. SubSystem block "BusbarTempHiFltDet"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet
Child Systems: | BusbarTempHiFltDet_sys, MaxBusbarTempCheck_Condition
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 50% (23/46) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
MCDC | NA | 0% (0/11) conditions reversed the outcome
Execution | NA | 100% (44/44) objective outcomes

### 349. SubSystem block "BusbarTempHiFltDet_sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet
Child Systems: | BusbarTempHiFltLv1Det, BusbarTempHiFltLv2Det, BusbarTempHiFltLv3Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 50% (19/38) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
MCDC | NA | 0% (0/9) conditions reversed the outcome
Execution | NA | 100% (38/38) objective outcomes

### 350. SubSystem block "BusbarTempHiFltLv1Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (6/12) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (12/12) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys/BusbarTempHiFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys/BusbarTempHiFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys/BusbarTempHiFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys/BusbarTempHiFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant4" | Execution

### 351. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys/BusbarTempHiFltLv1Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys/BusbarTempHiFltLv1Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 352. SubSystem block "BusbarTempHiFltLv2Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (6/12) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (12/12) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys/BusbarTempHiFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys/BusbarTempHiFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys/BusbarTempHiFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys/BusbarTempHiFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant4" | Execution

### 353. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys/BusbarTempHiFltLv2Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys/BusbarTempHiFltLv2Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 354. SubSystem block "BusbarTempHiFltLv3Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (7/14) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (14/14) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys/BusbarTempHiFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys/BusbarTempHiFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Comparison"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys/BusbarTempHiFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 > input2 | 1001 | 0

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys/BusbarTempHiFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys/BusbarTempHiFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution

### 355. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys/BusbarTempHiFltLv3Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/BusbarTempHiFltDet_sys/BusbarTempHiFltLv3Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 356. SubSystem block "MaxBusbarTempCheck_Condition"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Condition | NA | 50% (4/8) condition outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 100% (6/6) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/MaxBusbarTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 1001 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TT) | FT
input port 2 | (TT) | (TF)

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/MaxBusbarTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 2 | 0

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempHiFltDet/MaxBusbarTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution

### 357. SubSystem block "BusbarTempLowFltDet"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet
Child Systems: | BusbarTempLowFltDet_sys, MinBusbarTempCheck_Condition
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 50% (23/46) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
MCDC | NA | 0% (0/11) conditions reversed the outcome
Execution | NA | 100% (44/44) objective outcomes

### 358. SubSystem block "BusbarTempLowFltDet_sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet
Child Systems: | BusbarTempLowFltLv1Det, BusbarTempLowFltLv2Det, BusbarTempLowFltLv3Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 50% (19/38) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
MCDC | NA | 0% (0/9) conditions reversed the outcome
Execution | NA | 100% (38/38) objective outcomes

### 359. SubSystem block "BusbarTempLowFltLv1Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (6/12) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (12/12) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys/BusbarTempLowFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys/BusbarTempLowFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys/BusbarTempLowFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys/BusbarTempLowFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant4" | Execution

### 360. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys/BusbarTempLowFltLv1Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys/BusbarTempLowFltLv1Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 361. SubSystem block "BusbarTempLowFltLv2Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (6/12) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (12/12) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys/BusbarTempLowFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys/BusbarTempLowFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys/BusbarTempLowFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys/BusbarTempLowFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant4" | Execution

### 362. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys/BusbarTempLowFltLv2Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys/BusbarTempLowFltLv2Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 363. SubSystem block "BusbarTempLowFltLv3Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (7/14) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (14/14) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys/BusbarTempLowFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys/BusbarTempLowFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Comparison1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys/BusbarTempLowFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 < input2 | 1001 | 0

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys/BusbarTempLowFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys/BusbarTempLowFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution

### 364. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys/BusbarTempLowFltLv3Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/BusbarTempLowFltDet_sys/BusbarTempLowFltLv3Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 365. SubSystem block "MinBusbarTempCheck_Condition"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Condition | NA | 50% (4/8) condition outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 100% (6/6) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/MinBusbarTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 1001 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TT) | FT
input port 2 | (TT) | (TF)

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/MinBusbarTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 2 | 0

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempLowFltDet/MinBusbarTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution

### 366. SubSystem block "BusbarTempRngFltDet"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet
Child Systems: | BusbarTempRngHiFltDet_sys, BusbarTempRngLowFltDet_sys, TempRngHiCheck_Condition, TempRngLowCheck_Condition
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 4
Condition | NA | 50% (14/28) condition outcomes
Decision | NA | 50% (2/4) decision outcomes
MCDC | NA | 0% (0/6) conditions reversed the outcome
Execution | NA | 100% (24/24) objective outcomes

### 367. SubSystem block "BusbarTempRngHiFltDet_sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempRngFltDet
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (3/6) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (6/6) objective outcomes

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempRngFltDet/BusbarTempRngHiFltDet_sys
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator In1) | (TTT) | (FTT)
C2 (Logical Operator In2) | (TTT) | (TFT)
C3 (Logical Operator1 In2) | (TTT) | (TTF)

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempRngFltDet/BusbarTempRngHiFltDet_sys
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution

### 368. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempRngFltDet/BusbarTempRngHiFltDet_sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempRngFltDet/BusbarTempRngHiFltDet_sys/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 369. SubSystem block "BusbarTempRngLowFltDet_sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempRngFltDet
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (3/6) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (6/6) objective outcomes

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempRngFltDet/BusbarTempRngLowFltDet_sys
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator In1) | (TTT) | (FTT)
C2 (Logical Operator In2) | (TTT) | (TFT)
C3 (Logical Operator1 In2) | (TTT) | (TTF)

#### RelationalOperator block "Comparison3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempRngFltDet/BusbarTempRngLowFltDet_sys
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Constant block "Constant1" | Execution

### 370. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempRngFltDet/BusbarTempRngLowFltDet_sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempRngFltDet/BusbarTempRngLowFltDet_sys/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 371. SubSystem block "TempRngHiCheck_Condition"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempRngFltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Condition | NA | 50% (4/8) condition outcomes
Execution | NA | 100% (6/6) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempRngFltDet/TempRngHiCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator1
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 1001 | 0

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempRngFltDet/TempRngHiCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempRngFltDet/TempRngHiCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 2 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution

### 372. SubSystem block "TempRngLowCheck_Condition"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempRngFltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Condition | NA | 50% (4/8) condition outcomes
Execution | NA | 100% (6/6) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempRngFltDet/TempRngLowCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator1
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 1001 | 0

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempRngFltDet/TempRngLowCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/BusbarTempRngFltDet/TempRngLowCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 2 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution

### 373. SubSystem block "CellTempDiffFltDet"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet
Child Systems: | CellTempDiffFltDet_Sys, DiffTempCheck_Condition
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 4
Condition | NA | 50% (23/46) condition outcomes
Decision | NA | 50% (2/4) decision outcomes
MCDC | NA | 0% (0/11) conditions reversed the outcome
Execution | NA | 100% (41/41) objective outcomes

### 374. SubSystem block "CellTempDiffFltDet_Sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet
Child Systems: | CellTempDiffFltLv1Det, CellTempDiffFltLv2Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 4
Condition | NA | 50% (19/38) condition outcomes
Decision | NA | 50% (2/4) decision outcomes
MCDC | NA | 0% (0/9) conditions reversed the outcome
Execution | NA | 100% (35/35) objective outcomes

#### Full Coverage

Model Object | Metric
Sum block "Add" | Execution

### 375. SubSystem block "CellTempDiffFltLv1Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/CellTempDiffFltDet_Sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (11/22) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/5) conditions reversed the outcome
Execution | NA | 100% (20/20) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/CellTempDiffFltDet_Sys/CellTempDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (4/8) condition outcomes
MCDC | 0% (0/5) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 1001 | 0
input port 3 | 1001 | 0
input port 4 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(((C1 && C2) && C3) && C4) && C5 |
C1 (Logical Operator1 In1) | (TTTTT) | (FTTTT)
C2 (Logical Operator1 In2) | (TTTTT) | (TFTTT)
C3 (Logical Operator In2) | (TTTTT) | (TTFTT)
C4 (Logical Operator In3) | (TTTTT) | (TTTFT)
C5 (Logical Operator In4) | (TTTTT) | (TTTTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/CellTempDiffFltDet_Sys/CellTempDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Comparison"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/CellTempDiffFltDet_Sys/CellTempDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 > input2 | 1001 | 0

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/CellTempDiffFltDet_Sys/CellTempDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/CellTempDiffFltDet_Sys/CellTempDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/CellTempDiffFltDet_Sys/CellTempDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/CellTempDiffFltDet_Sys/CellTempDiffFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add1" | Execution
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution
Constant block "Constant5" | Execution
Constant block "Constant6" | Execution
Constant block "Constant7" | Execution

### 376. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/CellTempDiffFltDet_Sys/CellTempDiffFltLv1Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/CellTempDiffFltDet_Sys/CellTempDiffFltLv1Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 377. SubSystem block "CellTempDiffFltLv2Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/CellTempDiffFltDet_Sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (8/16) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/4) conditions reversed the outcome
Execution | NA | 100% (14/14) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/CellTempDiffFltDet_Sys/CellTempDiffFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (4/8) condition outcomes
MCDC | 0% (0/4) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 1001 | 0
input port 3 | 1001 | 0
input port 4 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TTTT) | (FTTT)
input port 2 | (TTTT) | (TFTT)
input port 3 | (TTTT) | (TTFT)
input port 4 | (TTTT) | (TTTF)

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/CellTempDiffFltDet_Sys/CellTempDiffFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/CellTempDiffFltDet_Sys/CellTempDiffFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/CellTempDiffFltDet_Sys/CellTempDiffFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/CellTempDiffFltDet_Sys/CellTempDiffFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution

### 378. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/CellTempDiffFltDet_Sys/CellTempDiffFltLv2Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/CellTempDiffFltDet_Sys/CellTempDiffFltLv2Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 379. SubSystem block "DiffTempCheck_Condition"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Condition | NA | 50% (4/8) condition outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 100% (6/6) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/DiffTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 1001 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TT) | FT
input port 2 | (TT) | (TF)

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/DiffTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempDiffFltDet/DiffTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 2 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution

### 380. SubSystem block "CellTempHiFltDet"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet
Child Systems: | CellTempHiFltDet_sys, MaxTempCheck_Condition
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 50% (28/56) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
MCDC | NA | 0% (0/12) conditions reversed the outcome
Execution | NA | 100% (56/56) objective outcomes

### 381. SubSystem block "CellTempHiFltDet_sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet
Child Systems: | CellTempHiFltLv1Det, CellTempHiFltLv2Det, CellTempHiFltLv3Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 50% (21/42) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
MCDC | NA | 0% (0/9) conditions reversed the outcome
Execution | NA | 100% (46/46) objective outcomes

### 382. SubSystem block "CellTempHiFltLv1Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (7/14) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (16/16) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Comparison"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 > input2 | 1001 | 0

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add1" | Execution
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution
Constant block "Constant5" | Execution

### 383. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv1Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv1Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 384. SubSystem block "CellTempHiFltLv2Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (7/14) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (16/16) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Comparison"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 > input2 | 1001 | 0

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add1" | Execution
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution
Constant block "Constant5" | Execution

### 385. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv2Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv2Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 386. SubSystem block "CellTempHiFltLv3Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (7/14) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (14/14) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Comparison"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 > input2 | 1001 | 0

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution

### 387. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv3Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/CellTempHiFltDet_sys/CellTempHiFltLv3Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 388. SubSystem block "MaxTempCheck_Condition"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Condition | NA | 50% (7/14) condition outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (10/10) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/MaxTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (3/6) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 1001 | 0
input port 3 | 1001 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TTT) | FTT
input port 2 | (TTT) | (TFT)
input port 3 | (TTT) | (TTF)

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/MaxTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/MaxTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 2 | 0

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/MaxTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet/MaxTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution

### 389. SubSystem block "CellTempHiFltDet_Chrg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet
Child Systems: | ChrgCellTempHiFltDet_sys, ChrgMaxTempCheck_Condition
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 50% (28/56) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
MCDC | NA | 0% (0/12) conditions reversed the outcome
Execution | NA | 100% (56/56) objective outcomes

### 390. SubSystem block "ChrgCellTempHiFltDet_sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg
Child Systems: | CellTempHiFltLv1Det_Chrg, CellTempHiFltLv2Det_Chrg, CellTempHiFltLv3Det_Chrg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 50% (21/42) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
MCDC | NA | 0% (0/9) conditions reversed the outcome
Execution | NA | 100% (46/46) objective outcomes

### 391. SubSystem block "CellTempHiFltLv1Det_Chrg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (7/14) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (16/16) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv1Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv1Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Comparison"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv1Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 > input2 | 1001 | 0

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv1Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv1Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add1" | Execution
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution
Constant block "Constant5" | Execution

### 392. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv1Det_Chrg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv1Det_Chrg/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 393. SubSystem block "CellTempHiFltLv2Det_Chrg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (7/14) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (16/16) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv2Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv2Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Comparison"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv2Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 > input2 | 1001 | 0

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv2Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv2Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add1" | Execution
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution
Constant block "Constant5" | Execution

### 394. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv2Det_Chrg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv2Det_Chrg/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 395. SubSystem block "CellTempHiFltLv3Det_Chrg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (7/14) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (14/14) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv3Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv3Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Comparison"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv3Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 > input2 | 1001 | 0

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv3Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv3Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution

### 396. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv3Det_Chrg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgCellTempHiFltDet_sys/CellTempHiFltLv3Det_Chrg/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 397. SubSystem block "ChrgMaxTempCheck_Condition"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Condition | NA | 50% (7/14) condition outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (10/10) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgMaxTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (3/6) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 1001 | 0
input port 3 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TTT) | (FTT)
input port 2 | (TTT) | (TFT)
input port 3 | (TTT) | (TTF)

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgMaxTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgMaxTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 2 | 0

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgMaxTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempHiFltDet_Chrg/ChrgMaxTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution

### 398. SubSystem block "CellTempLowFltDet"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet
Child Systems: | MinCellTemp_SateSwitch_Sys, MinTempCheck_Condition
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 50% (28/56) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
MCDC | NA | 0% (0/12) conditions reversed the outcome
Execution | NA | 100% (56/56) objective outcomes

### 399. SubSystem block "MinCellTemp_SateSwitch_Sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet
Child Systems: | CellTempLowFltLv1Det, CellTempLowFltLv2Det, CellTempLowFltLv3Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 50% (21/42) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
MCDC | NA | 0% (0/9) conditions reversed the outcome
Execution | NA | 100% (46/46) objective outcomes

### 400. SubSystem block "CellTempLowFltLv1Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (7/14) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (16/16) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Comparison2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 < input2 | 1001 | 0

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv1Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add1" | Execution
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution
Constant block "Constant5" | Execution

### 401. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv1Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv1Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 402. SubSystem block "CellTempLowFltLv2Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (7/14) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (16/16) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Comparison2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 < input2 | 1001 | 0

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv2Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add1" | Execution
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution
Constant block "Constant5" | Execution

### 403. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv2Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv2Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 404. SubSystem block "CellTempLowFltLv3Det"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (7/14) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (14/14) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Comparison2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 < input2 | 0 | 1001

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv3Det
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution

### 405. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv3Det
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinCellTemp_SateSwitch_Sys/CellTempLowFltLv3Det/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 406. SubSystem block "MinTempCheck_Condition"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Condition | NA | 50% (7/14) condition outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (10/10) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (3/6) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 1001 | 0
input port 3 | 1001 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TTT) | FTT
input port 2 | (TTT) | (TFT)
input port 3 | (TTT) | (TTF)

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 2 | 0

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFltDet/MinTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution

### 407. SubSystem block "CellTempLowFlt_Chrg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet
Child Systems: | ChrgMinCellTemp_SateSwitch_Sys, ChrgMinTempCheck_Condition
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 50% (28/56) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
MCDC | NA | 0% (0/12) conditions reversed the outcome
Execution | NA | 100% (56/56) objective outcomes

### 408. SubSystem block "ChrgMinCellTemp_SateSwitch_Sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg
Child Systems: | CellTempLowFltLv1Det_Chrg, CellTempLowFltLv2Det_Chrg, CellTempLowFltLv3Det_Chrg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 50% (21/42) condition outcomes
Decision | NA | 50% (3/6) decision outcomes
MCDC | NA | 0% (0/9) conditions reversed the outcome
Execution | NA | 100% (46/46) objective outcomes

### 409. SubSystem block "CellTempLowFltLv1Det_Chrg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (7/14) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (16/16) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv1Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv1Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Comparison2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv1Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 < input2 | 1001 | 0

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv1Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv1Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add1" | Execution
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution
Constant block "Constant5" | Execution

### 410. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv1Det_Chrg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv1Det_Chrg/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 411. SubSystem block "CellTempLowFltLv2Det_Chrg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (7/14) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (16/16) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv2Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv2Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Comparison2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv2Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 < input2 | 1001 | 0

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv2Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv2Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add1" | Execution
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution
Constant block "Constant5" | Execution

### 412. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv2Det_Chrg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv2Det_Chrg/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 413. SubSystem block "CellTempLowFltLv3Det_Chrg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (7/14) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (14/14) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv3Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator1 In1) | (TTT) | (FTT)
C2 (Logical Operator1 In2) | (TTT) | (TFT)
C3 (Logical Operator In2) | (TTT) | (TTF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv3Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 0 | 1001

#### RelationalOperator block "Comparison2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv3Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 < input2 | 0 | 1001

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv3Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv3Det_Chrg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add4" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution

### 414. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv3Det_Chrg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinCellTemp_SateSwitch_Sys/CellTempLowFltLv3Det_Chrg/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 415. SubSystem block "ChrgMinTempCheck_Condition"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Condition | NA | 50% (7/14) condition outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (10/10) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (3/6) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 1001 | 0
input port 3 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TTT) | (FTT)
input port 2 | (TTT) | (TFT)
input port 3 | (TTT) | (TTF)

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 2 | 0

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempLowFlt_Chrg/ChrgMinTempCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution

### 416. SubSystem block "CellTempRngFltDet"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet
Child Systems: | CellTempRngHiFltDet_sys, CellTempRngLowFltDet_sys, TempRngHiCheck_Condition, TempRngLowCheck_Condition
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 4
Condition | NA | 50% (14/28) condition outcomes
Decision | NA | 50% (2/4) decision outcomes
MCDC | NA | 0% (0/6) conditions reversed the outcome
Execution | NA | 100% (24/24) objective outcomes

### 417. SubSystem block "CellTempRngHiFltDet_sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempRngFltDet
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (3/6) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (6/6) objective outcomes

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempRngFltDet/CellTempRngHiFltDet_sys
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator In1) | (TTT) | (FTT)
C2 (Logical Operator In2) | (TTT) | (TFT)
C3 (Logical Operator1 In2) | (TTT) | (TTF)

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempRngFltDet/CellTempRngHiFltDet_sys
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution

### 418. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempRngFltDet/CellTempRngHiFltDet_sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempRngFltDet/CellTempRngHiFltDet_sys/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 419. SubSystem block "CellTempRngLowFltDet_sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempRngFltDet
Child Systems: | CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (3/6) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/3) conditions reversed the outcome
Execution | NA | 100% (6/6) objective outcomes

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempRngFltDet/CellTempRngLowFltDet_sys
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/3) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur) Includes 2 blocks
Decision/Condition | True Out | False Out
(C1 && C2) && C3 |
C1 (Logical Operator In1) | (TTT) | (FTT)
C2 (Logical Operator In2) | (TTT) | (TFT)
C3 (Logical Operator1 In2) | (TTT) | (TTF)

#### RelationalOperator block "Comparison3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempRngFltDet/CellTempRngLowFltDet_sys
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Constant block "Constant1" | Execution

### 420. SubSystem block "CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempRngFltDet/CellTempRngLowFltDet_sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempRngFltDet/CellTempRngLowFltDet_sys/CDP_GbCDP_ChrgMaxCellVoltFltLv1_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 421. SubSystem block "TempRngHiCheck_Condition"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempRngFltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Condition | NA | 50% (4/8) condition outcomes
Execution | NA | 100% (6/6) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempRngFltDet/TempRngHiCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator1
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 1001 | 0

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempRngFltDet/TempRngHiCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempRngFltDet/TempRngHiCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 2 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution

### 422. SubSystem block "TempRngLowCheck_Condition"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempRngFltDet
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Condition | NA | 50% (4/8) condition outcomes
Execution | NA | 100% (6/6) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempRngFltDet/TempRngLowCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | see Logical Operator1
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 0 | 1001
input port 2 | 1001 | 0

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempRngFltDet/TempRngLowCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/TempFltDet/CellTempRngFltDet/TempRngLowCheck_Condition
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 2 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution

### 423. SubSystem block "VoltDataPrc_20ms_sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys
Child Systems: | CellVoltVld_Output, CellVolt_Output, CellVolt_SelfCheck, MaxMinSum_CellVolt_Get, StackVolt
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 368
Condition | NA | 50% (1834/3632) condition outcomes
Decision | NA | 54% (338/625) decision outcomes
MCDC | NA | 0% (0/1132) conditions reversed the outcome
Execution | NA | 100% (236/236) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant3" | Execution

### 424. SubSystem block "CellVoltVld_Output"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys
Child Systems: | OverWrite5
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (226/452) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/224) conditions reversed the outcome
Execution | NA | 100% (10/10) objective outcomes

#### Logic block "Logical Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVoltVld_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (113/226) condition outcomes
MCDC | 0% (0/224) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 1001 | 0
input port1(2) | 1001 | 0
input port1(3) | 1001 | 0
input port1(4) | 1001 | 0
input port1(5) | 1001 | 0
input port1(6) | 1001 | 0
input port1(7) | 1001 | 0
input port1(8) | 1001 | 0
input port1(9) | 1001 | 0
input port1(10) | 1001 | 0
input port1(11) | 1001 | 0
input port1(12) | 1001 | 0
input port1(13) | 1001 | 0
input port1(14) | 1001 | 0
input port1(15) | 1001 | 0
input port1(16) | 1001 | 0
input port1(17) | 1001 | 0
input port1(18) | 1001 | 0
input port1(19) | 1001 | 0
input port1(20) | 1001 | 0
input port1(21) | 1001 | 0
input port1(22) | 1001 | 0
input port1(23) | 1001 | 0
input port1(24) | 1001 | 0
input port1(25) | 1001 | 0
input port1(26) | 1001 | 0
input port1(27) | 1001 | 0
input port1(28) | 1001 | 0
input port1(29) | 1001 | 0
input port1(30) | 1001 | 0
input port1(31) | 1001 | 0
input port1(32) | 1001 | 0
input port1(33) | 1001 | 0
input port1(34) | 1001 | 0
input port1(35) | 1001 | 0
input port1(36) | 1001 | 0
input port1(37) | 1001 | 0
input port1(38) | 1001 | 0
input port1(39) | 1001 | 0
input port1(40) | 1001 | 0
input port1(41) | 1001 | 0
input port1(42) | 1001 | 0
input port1(43) | 1001 | 0
input port1(44) | 1001 | 0
input port1(45) | 1001 | 0
input port1(46) | 1001 | 0
input port1(47) | 1001 | 0
input port1(48) | 1001 | 0
input port1(49) | 1001 | 0
input port1(50) | 1001 | 0
input port1(51) | 1001 | 0
input port1(52) | 1001 | 0
input port1(53) | 1001 | 0
input port1(54) | 1001 | 0
input port1(55) | 1001 | 0
input port1(56) | 1001 | 0
input port1(57) | 1001 | 0
input port1(58) | 1001 | 0
input port1(59) | 1001 | 0
input port1(60) | 1001 | 0
input port1(61) | 1001 | 0
input port1(62) | 1001 | 0
input port1(63) | 1001 | 0
input port1(64) | 1001 | 0
input port1(65) | 1001 | 0
input port1(66) | 1001 | 0
input port1(67) | 1001 | 0
input port1(68) | 1001 | 0
input port1(69) | 1001 | 0
input port1(70) | 1001 | 0
input port1(71) | 1001 | 0
input port1(72) | 1001 | 0
input port1(73) | 1001 | 0
input port1(74) | 1001 | 0
input port1(75) | 1001 | 0
input port1(76) | 1001 | 0
input port1(77) | 1001 | 0
input port1(78) | 1001 | 0
input port1(79) | 1001 | 0
input port1(80) | 1001 | 0
input port1(81) | 1001 | 0
input port1(82) | 1001 | 0
input port1(83) | 1001 | 0
input port1(84) | 1001 | 0
input port1(85) | 1001 | 0
input port1(86) | 1001 | 0
input port1(87) | 1001 | 0
input port1(88) | 1001 | 0
input port1(89) | 1001 | 0
input port1(90) | 1001 | 0
input port1(91) | 1001 | 0
input port1(92) | 1001 | 0
input port1(93) | 1001 | 0
input port1(94) | 1001 | 0
input port1(95) | 1001 | 0
input port1(96) | 1001 | 0
input port1(97) | 1001 | 0
input port1(98) | 1001 | 0
input port1(99) | 1001 | 0
input port1(100) | 1001 | 0
input port1(101) | 1001 | 0
input port1(102) | 1001 | 0
input port1(103) | 1001 | 0
input port1(104) | 1001 | 0
input port1(105) | 1001 | 0
input port1(106) | 1001 | 0
input port1(107) | 1001 | 0
input port1(108) | 1001 | 0
input port1(109) | 1001 | 0
input port1(110) | 1001 | 0
input port1(111) | 1001 | 0
input port1(112) | 1001 | 0
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output(1) |
input port1(1) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(2) |
input port1(2) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(3) |
input port1(3) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(4) |
input port1(4) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(5) |
input port1(5) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(6) |
input port1(6) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(7) |
input port1(7) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(8) |
input port1(8) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(9) |
input port1(9) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(10) |
input port1(10) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(11) |
input port1(11) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(12) |
input port1(12) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(13) |
input port1(13) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(14) |
input port1(14) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(15) |
input port1(15) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(16) |
input port1(16) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(17) |
input port1(17) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(18) |
input port1(18) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(19) |
input port1(19) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(20) |
input port1(20) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(21) |
input port1(21) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(22) |
input port1(22) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(23) |
input port1(23) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(24) |
input port1(24) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(25) |
input port1(25) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(26) |
input port1(26) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(27) |
input port1(27) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(28) |
input port1(28) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(29) |
input port1(29) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(30) |
input port1(30) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(31) |
input port1(31) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(32) |
input port1(32) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(33) |
input port1(33) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(34) |
input port1(34) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(35) |
input port1(35) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(36) |
input port1(36) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(37) |
input port1(37) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(38) |
input port1(38) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(39) |
input port1(39) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(40) |
input port1(40) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(41) |
input port1(41) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(42) |
input port1(42) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(43) |
input port1(43) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(44) |
input port1(44) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(45) |
input port1(45) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(46) |
input port1(46) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(47) |
input port1(47) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(48) |
input port1(48) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(49) |
input port1(49) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(50) |
input port1(50) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(51) |
input port1(51) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(52) |
input port1(52) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(53) |
input port1(53) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(54) |
input port1(54) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(55) |
input port1(55) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(56) |
input port1(56) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(57) |
input port1(57) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(58) |
input port1(58) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(59) |
input port1(59) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(60) |
input port1(60) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(61) |
input port1(61) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(62) |
input port1(62) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(63) |
input port1(63) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(64) |
input port1(64) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(65) |
input port1(65) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(66) |
input port1(66) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(67) |
input port1(67) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(68) |
input port1(68) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(69) |
input port1(69) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(70) |
input port1(70) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(71) |
input port1(71) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(72) |
input port1(72) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(73) |
input port1(73) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(74) |
input port1(74) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(75) |
input port1(75) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(76) |
input port1(76) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(77) |
input port1(77) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(78) |
input port1(78) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(79) |
input port1(79) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(80) |
input port1(80) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(81) |
input port1(81) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(82) |
input port1(82) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(83) |
input port1(83) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(84) |
input port1(84) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(85) |
input port1(85) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(86) |
input port1(86) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(87) |
input port1(87) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(88) |
input port1(88) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(89) |
input port1(89) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(90) |
input port1(90) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(91) |
input port1(91) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(92) |
input port1(92) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(93) |
input port1(93) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(94) |
input port1(94) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(95) |
input port1(95) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(96) |
input port1(96) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(97) |
input port1(97) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(98) |
input port1(98) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(99) |
input port1(99) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(100) |
input port1(100) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(101) |
input port1(101) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(102) |
input port1(102) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(103) |
input port1(103) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(104) |
input port1(104) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(105) |
input port1(105) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(106) |
input port1(106) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(107) |
input port1(107) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(108) |
input port1(108) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(109) |
input port1(109) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(110) |
input port1(110) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(111) |
input port1(111) | TF | (FF)
input port 2 | (FT) | (FF)
expression for output(112) |
input port1(112) | TF | (FF)
input port 2 | (FT) | (FF)

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVoltVld_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVoltVld_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (112/224) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) == input2 | 1001 | 0
input1(2) == input2 | 1001 | 0
input1(3) == input2 | 1001 | 0
input1(4) == input2 | 1001 | 0
input1(5) == input2 | 1001 | 0
input1(6) == input2 | 1001 | 0
input1(7) == input2 | 1001 | 0
input1(8) == input2 | 1001 | 0
input1(9) == input2 | 1001 | 0
input1(10) == input2 | 1001 | 0
input1(11) == input2 | 1001 | 0
input1(12) == input2 | 1001 | 0
input1(13) == input2 | 1001 | 0
input1(14) == input2 | 1001 | 0
input1(15) == input2 | 1001 | 0
input1(16) == input2 | 1001 | 0
input1(17) == input2 | 1001 | 0
input1(18) == input2 | 1001 | 0
input1(19) == input2 | 1001 | 0
input1(20) == input2 | 1001 | 0
input1(21) == input2 | 1001 | 0
input1(22) == input2 | 1001 | 0
input1(23) == input2 | 1001 | 0
input1(24) == input2 | 1001 | 0
input1(25) == input2 | 1001 | 0
input1(26) == input2 | 1001 | 0
input1(27) == input2 | 1001 | 0
input1(28) == input2 | 1001 | 0
input1(29) == input2 | 1001 | 0
input1(30) == input2 | 1001 | 0
input1(31) == input2 | 1001 | 0
input1(32) == input2 | 1001 | 0
input1(33) == input2 | 1001 | 0
input1(34) == input2 | 1001 | 0
input1(35) == input2 | 1001 | 0
input1(36) == input2 | 1001 | 0
input1(37) == input2 | 1001 | 0
input1(38) == input2 | 1001 | 0
input1(39) == input2 | 1001 | 0
input1(40) == input2 | 1001 | 0
input1(41) == input2 | 1001 | 0
input1(42) == input2 | 1001 | 0
input1(43) == input2 | 1001 | 0
input1(44) == input2 | 1001 | 0
input1(45) == input2 | 1001 | 0
input1(46) == input2 | 1001 | 0
input1(47) == input2 | 1001 | 0
input1(48) == input2 | 1001 | 0
input1(49) == input2 | 1001 | 0
input1(50) == input2 | 1001 | 0
input1(51) == input2 | 1001 | 0
input1(52) == input2 | 1001 | 0
input1(53) == input2 | 1001 | 0
input1(54) == input2 | 1001 | 0
input1(55) == input2 | 1001 | 0
input1(56) == input2 | 1001 | 0
input1(57) == input2 | 1001 | 0
input1(58) == input2 | 1001 | 0
input1(59) == input2 | 1001 | 0
input1(60) == input2 | 1001 | 0
input1(61) == input2 | 1001 | 0
input1(62) == input2 | 1001 | 0
input1(63) == input2 | 1001 | 0
input1(64) == input2 | 1001 | 0
input1(65) == input2 | 1001 | 0
input1(66) == input2 | 1001 | 0
input1(67) == input2 | 1001 | 0
input1(68) == input2 | 1001 | 0
input1(69) == input2 | 1001 | 0
input1(70) == input2 | 1001 | 0
input1(71) == input2 | 1001 | 0
input1(72) == input2 | 1001 | 0
input1(73) == input2 | 1001 | 0
input1(74) == input2 | 1001 | 0
input1(75) == input2 | 1001 | 0
input1(76) == input2 | 1001 | 0
input1(77) == input2 | 1001 | 0
input1(78) == input2 | 1001 | 0
input1(79) == input2 | 1001 | 0
input1(80) == input2 | 1001 | 0
input1(81) == input2 | 1001 | 0
input1(82) == input2 | 1001 | 0
input1(83) == input2 | 1001 | 0
input1(84) == input2 | 1001 | 0
input1(85) == input2 | 1001 | 0
input1(86) == input2 | 1001 | 0
input1(87) == input2 | 1001 | 0
input1(88) == input2 | 1001 | 0
input1(89) == input2 | 1001 | 0
input1(90) == input2 | 1001 | 0
input1(91) == input2 | 1001 | 0
input1(92) == input2 | 1001 | 0
input1(93) == input2 | 1001 | 0
input1(94) == input2 | 1001 | 0
input1(95) == input2 | 1001 | 0
input1(96) == input2 | 1001 | 0
input1(97) == input2 | 1001 | 0
input1(98) == input2 | 1001 | 0
input1(99) == input2 | 1001 | 0
input1(100) == input2 | 1001 | 0
input1(101) == input2 | 1001 | 0
input1(102) == input2 | 1001 | 0
input1(103) == input2 | 1001 | 0
input1(104) == input2 | 1001 | 0
input1(105) == input2 | 1001 | 0
input1(106) == input2 | 1001 | 0
input1(107) == input2 | 1001 | 0
input1(108) == input2 | 1001 | 0
input1(109) == input2 | 1001 | 0
input1(110) == input2 | 1001 | 0
input1(111) == input2 | 1001 | 0
input1(112) == input2 | 1001 | 0

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution
S-Function block "Bitwise Logical Operator" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution

### 425. SubSystem block "OverWrite5"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVoltVld_Output
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVoltVld_Output/OverWrite5
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 426. SubSystem block "CellVolt_Output"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys
Child Systems: | CellVolt_SignalFilt
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 141
Condition | NA | 50% (786/1572) condition outcomes
Decision | NA | 47% (125/265) decision outcomes
MCDC | NA | 0% (0/448) conditions reversed the outcome
Execution | NA | 100% (34/34) objective outcomes

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (224/448) condition outcomes
MCDC | 0% (0/224) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 0 | 1001
input port1(2) | 0 | 1001
input port1(3) | 0 | 1001
input port1(4) | 0 | 1001
input port1(5) | 0 | 1001
input port1(6) | 0 | 1001
input port1(7) | 0 | 1001
input port1(8) | 0 | 1001
input port1(9) | 0 | 1001
input port1(10) | 0 | 1001
input port1(11) | 0 | 1001
input port1(12) | 0 | 1001
input port1(13) | 0 | 1001
input port1(14) | 0 | 1001
input port1(15) | 0 | 1001
input port1(16) | 0 | 1001
input port1(17) | 0 | 1001
input port1(18) | 0 | 1001
input port1(19) | 0 | 1001
input port1(20) | 0 | 1001
input port1(21) | 0 | 1001
input port1(22) | 0 | 1001
input port1(23) | 0 | 1001
input port1(24) | 0 | 1001
input port1(25) | 0 | 1001
input port1(26) | 0 | 1001
input port1(27) | 0 | 1001
input port1(28) | 0 | 1001
input port1(29) | 0 | 1001
input port1(30) | 0 | 1001
input port1(31) | 0 | 1001
input port1(32) | 0 | 1001
input port1(33) | 0 | 1001
input port1(34) | 0 | 1001
input port1(35) | 0 | 1001
input port1(36) | 0 | 1001
input port1(37) | 0 | 1001
input port1(38) | 0 | 1001
input port1(39) | 0 | 1001
input port1(40) | 0 | 1001
input port1(41) | 0 | 1001
input port1(42) | 0 | 1001
input port1(43) | 0 | 1001
input port1(44) | 0 | 1001
input port1(45) | 0 | 1001
input port1(46) | 0 | 1001
input port1(47) | 0 | 1001
input port1(48) | 0 | 1001
input port1(49) | 0 | 1001
input port1(50) | 0 | 1001
input port1(51) | 0 | 1001
input port1(52) | 0 | 1001
input port1(53) | 0 | 1001
input port1(54) | 0 | 1001
input port1(55) | 0 | 1001
input port1(56) | 0 | 1001
input port1(57) | 0 | 1001
input port1(58) | 0 | 1001
input port1(59) | 0 | 1001
input port1(60) | 0 | 1001
input port1(61) | 0 | 1001
input port1(62) | 0 | 1001
input port1(63) | 0 | 1001
input port1(64) | 0 | 1001
input port1(65) | 0 | 1001
input port1(66) | 0 | 1001
input port1(67) | 0 | 1001
input port1(68) | 0 | 1001
input port1(69) | 0 | 1001
input port1(70) | 0 | 1001
input port1(71) | 0 | 1001
input port1(72) | 0 | 1001
input port1(73) | 0 | 1001
input port1(74) | 0 | 1001
input port1(75) | 0 | 1001
input port1(76) | 0 | 1001
input port1(77) | 0 | 1001
input port1(78) | 0 | 1001
input port1(79) | 0 | 1001
input port1(80) | 0 | 1001
input port1(81) | 0 | 1001
input port1(82) | 0 | 1001
input port1(83) | 0 | 1001
input port1(84) | 0 | 1001
input port1(85) | 0 | 1001
input port1(86) | 0 | 1001
input port1(87) | 0 | 1001
input port1(88) | 0 | 1001
input port1(89) | 0 | 1001
input port1(90) | 0 | 1001
input port1(91) | 0 | 1001
input port1(92) | 0 | 1001
input port1(93) | 0 | 1001
input port1(94) | 0 | 1001
input port1(95) | 0 | 1001
input port1(96) | 0 | 1001
input port1(97) | 0 | 1001
input port1(98) | 0 | 1001
input port1(99) | 0 | 1001
input port1(100) | 0 | 1001
input port1(101) | 0 | 1001
input port1(102) | 0 | 1001
input port1(103) | 0 | 1001
input port1(104) | 0 | 1001
input port1(105) | 0 | 1001
input port1(106) | 0 | 1001
input port1(107) | 0 | 1001
input port1(108) | 0 | 1001
input port1(109) | 0 | 1001
input port1(110) | 0 | 1001
input port1(111) | 0 | 1001
input port1(112) | 0 | 1001
input port2(1) | 0 | 1001
input port2(2) | 0 | 1001
input port2(3) | 0 | 1001
input port2(4) | 0 | 1001
input port2(5) | 0 | 1001
input port2(6) | 0 | 1001
input port2(7) | 0 | 1001
input port2(8) | 0 | 1001
input port2(9) | 0 | 1001
input port2(10) | 0 | 1001
input port2(11) | 0 | 1001
input port2(12) | 0 | 1001
input port2(13) | 0 | 1001
input port2(14) | 0 | 1001
input port2(15) | 0 | 1001
input port2(16) | 0 | 1001
input port2(17) | 0 | 1001
input port2(18) | 0 | 1001
input port2(19) | 0 | 1001
input port2(20) | 0 | 1001
input port2(21) | 0 | 1001
input port2(22) | 0 | 1001
input port2(23) | 0 | 1001
input port2(24) | 0 | 1001
input port2(25) | 0 | 1001
input port2(26) | 0 | 1001
input port2(27) | 0 | 1001
input port2(28) | 0 | 1001
input port2(29) | 0 | 1001
input port2(30) | 0 | 1001
input port2(31) | 0 | 1001
input port2(32) | 0 | 1001
input port2(33) | 0 | 1001
input port2(34) | 0 | 1001
input port2(35) | 0 | 1001
input port2(36) | 0 | 1001
input port2(37) | 0 | 1001
input port2(38) | 0 | 1001
input port2(39) | 0 | 1001
input port2(40) | 0 | 1001
input port2(41) | 0 | 1001
input port2(42) | 0 | 1001
input port2(43) | 0 | 1001
input port2(44) | 0 | 1001
input port2(45) | 0 | 1001
input port2(46) | 0 | 1001
input port2(47) | 0 | 1001
input port2(48) | 0 | 1001
input port2(49) | 0 | 1001
input port2(50) | 0 | 1001
input port2(51) | 0 | 1001
input port2(52) | 0 | 1001
input port2(53) | 0 | 1001
input port2(54) | 0 | 1001
input port2(55) | 0 | 1001
input port2(56) | 0 | 1001
input port2(57) | 0 | 1001
input port2(58) | 0 | 1001
input port2(59) | 0 | 1001
input port2(60) | 0 | 1001
input port2(61) | 0 | 1001
input port2(62) | 0 | 1001
input port2(63) | 0 | 1001
input port2(64) | 0 | 1001
input port2(65) | 0 | 1001
input port2(66) | 0 | 1001
input port2(67) | 0 | 1001
input port2(68) | 0 | 1001
input port2(69) | 0 | 1001
input port2(70) | 0 | 1001
input port2(71) | 0 | 1001
input port2(72) | 0 | 1001
input port2(73) | 0 | 1001
input port2(74) | 0 | 1001
input port2(75) | 0 | 1001
input port2(76) | 0 | 1001
input port2(77) | 0 | 1001
input port2(78) | 0 | 1001
input port2(79) | 0 | 1001
input port2(80) | 0 | 1001
input port2(81) | 0 | 1001
input port2(82) | 0 | 1001
input port2(83) | 0 | 1001
input port2(84) | 0 | 1001
input port2(85) | 0 | 1001
input port2(86) | 0 | 1001
input port2(87) | 0 | 1001
input port2(88) | 0 | 1001
input port2(89) | 0 | 1001
input port2(90) | 0 | 1001
input port2(91) | 0 | 1001
input port2(92) | 0 | 1001
input port2(93) | 0 | 1001
input port2(94) | 0 | 1001
input port2(95) | 0 | 1001
input port2(96) | 0 | 1001
input port2(97) | 0 | 1001
input port2(98) | 0 | 1001
input port2(99) | 0 | 1001
input port2(100) | 0 | 1001
input port2(101) | 0 | 1001
input port2(102) | 0 | 1001
input port2(103) | 0 | 1001
input port2(104) | 0 | 1001
input port2(105) | 0 | 1001
input port2(106) | 0 | 1001
input port2(107) | 0 | 1001
input port2(108) | 0 | 1001
input port2(109) | 0 | 1001
input port2(110) | 0 | 1001
input port2(111) | 0 | 1001
input port2(112) | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output(1) |
input port1(1) | (TF) | FF
input port2(1) | (FT) | FF
expression for output(2) |
input port1(2) | (TF) | FF
input port2(2) | (FT) | FF
expression for output(3) |
input port1(3) | (TF) | FF
input port2(3) | (FT) | FF
expression for output(4) |
input port1(4) | (TF) | FF
input port2(4) | (FT) | FF
expression for output(5) |
input port1(5) | (TF) | FF
input port2(5) | (FT) | FF
expression for output(6) |
input port1(6) | (TF) | FF
input port2(6) | (FT) | FF
expression for output(7) |
input port1(7) | (TF) | FF
input port2(7) | (FT) | FF
expression for output(8) |
input port1(8) | (TF) | FF
input port2(8) | (FT) | FF
expression for output(9) |
input port1(9) | (TF) | FF
input port2(9) | (FT) | FF
expression for output(10) |
input port1(10) | (TF) | FF
input port2(10) | (FT) | FF
expression for output(11) |
input port1(11) | (TF) | FF
input port2(11) | (FT) | FF
expression for output(12) |
input port1(12) | (TF) | FF
input port2(12) | (FT) | FF
expression for output(13) |
input port1(13) | (TF) | FF
input port2(13) | (FT) | FF
expression for output(14) |
input port1(14) | (TF) | FF
input port2(14) | (FT) | FF
expression for output(15) |
input port1(15) | (TF) | FF
input port2(15) | (FT) | FF
expression for output(16) |
input port1(16) | (TF) | FF
input port2(16) | (FT) | FF
expression for output(17) |
input port1(17) | (TF) | FF
input port2(17) | (FT) | FF
expression for output(18) |
input port1(18) | (TF) | FF
input port2(18) | (FT) | FF
expression for output(19) |
input port1(19) | (TF) | FF
input port2(19) | (FT) | FF
expression for output(20) |
input port1(20) | (TF) | FF
input port2(20) | (FT) | FF
expression for output(21) |
input port1(21) | (TF) | FF
input port2(21) | (FT) | FF
expression for output(22) |
input port1(22) | (TF) | FF
input port2(22) | (FT) | FF
expression for output(23) |
input port1(23) | (TF) | FF
input port2(23) | (FT) | FF
expression for output(24) |
input port1(24) | (TF) | FF
input port2(24) | (FT) | FF
expression for output(25) |
input port1(25) | (TF) | FF
input port2(25) | (FT) | FF
expression for output(26) |
input port1(26) | (TF) | FF
input port2(26) | (FT) | FF
expression for output(27) |
input port1(27) | (TF) | FF
input port2(27) | (FT) | FF
expression for output(28) |
input port1(28) | (TF) | FF
input port2(28) | (FT) | FF
expression for output(29) |
input port1(29) | (TF) | FF
input port2(29) | (FT) | FF
expression for output(30) |
input port1(30) | (TF) | FF
input port2(30) | (FT) | FF
expression for output(31) |
input port1(31) | (TF) | FF
input port2(31) | (FT) | FF
expression for output(32) |
input port1(32) | (TF) | FF
input port2(32) | (FT) | FF
expression for output(33) |
input port1(33) | (TF) | FF
input port2(33) | (FT) | FF
expression for output(34) |
input port1(34) | (TF) | FF
input port2(34) | (FT) | FF
expression for output(35) |
input port1(35) | (TF) | FF
input port2(35) | (FT) | FF
expression for output(36) |
input port1(36) | (TF) | FF
input port2(36) | (FT) | FF
expression for output(37) |
input port1(37) | (TF) | FF
input port2(37) | (FT) | FF
expression for output(38) |
input port1(38) | (TF) | FF
input port2(38) | (FT) | FF
expression for output(39) |
input port1(39) | (TF) | FF
input port2(39) | (FT) | FF
expression for output(40) |
input port1(40) | (TF) | FF
input port2(40) | (FT) | FF
expression for output(41) |
input port1(41) | (TF) | FF
input port2(41) | (FT) | FF
expression for output(42) |
input port1(42) | (TF) | FF
input port2(42) | (FT) | FF
expression for output(43) |
input port1(43) | (TF) | FF
input port2(43) | (FT) | FF
expression for output(44) |
input port1(44) | (TF) | FF
input port2(44) | (FT) | FF
expression for output(45) |
input port1(45) | (TF) | FF
input port2(45) | (FT) | FF
expression for output(46) |
input port1(46) | (TF) | FF
input port2(46) | (FT) | FF
expression for output(47) |
input port1(47) | (TF) | FF
input port2(47) | (FT) | FF
expression for output(48) |
input port1(48) | (TF) | FF
input port2(48) | (FT) | FF
expression for output(49) |
input port1(49) | (TF) | FF
input port2(49) | (FT) | FF
expression for output(50) |
input port1(50) | (TF) | FF
input port2(50) | (FT) | FF
expression for output(51) |
input port1(51) | (TF) | FF
input port2(51) | (FT) | FF
expression for output(52) |
input port1(52) | (TF) | FF
input port2(52) | (FT) | FF
expression for output(53) |
input port1(53) | (TF) | FF
input port2(53) | (FT) | FF
expression for output(54) |
input port1(54) | (TF) | FF
input port2(54) | (FT) | FF
expression for output(55) |
input port1(55) | (TF) | FF
input port2(55) | (FT) | FF
expression for output(56) |
input port1(56) | (TF) | FF
input port2(56) | (FT) | FF
expression for output(57) |
input port1(57) | (TF) | FF
input port2(57) | (FT) | FF
expression for output(58) |
input port1(58) | (TF) | FF
input port2(58) | (FT) | FF
expression for output(59) |
input port1(59) | (TF) | FF
input port2(59) | (FT) | FF
expression for output(60) |
input port1(60) | (TF) | FF
input port2(60) | (FT) | FF
expression for output(61) |
input port1(61) | (TF) | FF
input port2(61) | (FT) | FF
expression for output(62) |
input port1(62) | (TF) | FF
input port2(62) | (FT) | FF
expression for output(63) |
input port1(63) | (TF) | FF
input port2(63) | (FT) | FF
expression for output(64) |
input port1(64) | (TF) | FF
input port2(64) | (FT) | FF
expression for output(65) |
input port1(65) | (TF) | FF
input port2(65) | (FT) | FF
expression for output(66) |
input port1(66) | (TF) | FF
input port2(66) | (FT) | FF
expression for output(67) |
input port1(67) | (TF) | FF
input port2(67) | (FT) | FF
expression for output(68) |
input port1(68) | (TF) | FF
input port2(68) | (FT) | FF
expression for output(69) |
input port1(69) | (TF) | FF
input port2(69) | (FT) | FF
expression for output(70) |
input port1(70) | (TF) | FF
input port2(70) | (FT) | FF
expression for output(71) |
input port1(71) | (TF) | FF
input port2(71) | (FT) | FF
expression for output(72) |
input port1(72) | (TF) | FF
input port2(72) | (FT) | FF
expression for output(73) |
input port1(73) | (TF) | FF
input port2(73) | (FT) | FF
expression for output(74) |
input port1(74) | (TF) | FF
input port2(74) | (FT) | FF
expression for output(75) |
input port1(75) | (TF) | FF
input port2(75) | (FT) | FF
expression for output(76) |
input port1(76) | (TF) | FF
input port2(76) | (FT) | FF
expression for output(77) |
input port1(77) | (TF) | FF
input port2(77) | (FT) | FF
expression for output(78) |
input port1(78) | (TF) | FF
input port2(78) | (FT) | FF
expression for output(79) |
input port1(79) | (TF) | FF
input port2(79) | (FT) | FF
expression for output(80) |
input port1(80) | (TF) | FF
input port2(80) | (FT) | FF
expression for output(81) |
input port1(81) | (TF) | FF
input port2(81) | (FT) | FF
expression for output(82) |
input port1(82) | (TF) | FF
input port2(82) | (FT) | FF
expression for output(83) |
input port1(83) | (TF) | FF
input port2(83) | (FT) | FF
expression for output(84) |
input port1(84) | (TF) | FF
input port2(84) | (FT) | FF
expression for output(85) |
input port1(85) | (TF) | FF
input port2(85) | (FT) | FF
expression for output(86) |
input port1(86) | (TF) | FF
input port2(86) | (FT) | FF
expression for output(87) |
input port1(87) | (TF) | FF
input port2(87) | (FT) | FF
expression for output(88) |
input port1(88) | (TF) | FF
input port2(88) | (FT) | FF
expression for output(89) |
input port1(89) | (TF) | FF
input port2(89) | (FT) | FF
expression for output(90) |
input port1(90) | (TF) | FF
input port2(90) | (FT) | FF
expression for output(91) |
input port1(91) | (TF) | FF
input port2(91) | (FT) | FF
expression for output(92) |
input port1(92) | (TF) | FF
input port2(92) | (FT) | FF
expression for output(93) |
input port1(93) | (TF) | FF
input port2(93) | (FT) | FF
expression for output(94) |
input port1(94) | (TF) | FF
input port2(94) | (FT) | FF
expression for output(95) |
input port1(95) | (TF) | FF
input port2(95) | (FT) | FF
expression for output(96) |
input port1(96) | (TF) | FF
input port2(96) | (FT) | FF
expression for output(97) |
input port1(97) | (TF) | FF
input port2(97) | (FT) | FF
expression for output(98) |
input port1(98) | (TF) | FF
input port2(98) | (FT) | FF
expression for output(99) |
input port1(99) | (TF) | FF
input port2(99) | (FT) | FF
expression for output(100) |
input port1(100) | (TF) | FF
input port2(100) | (FT) | FF
expression for output(101) |
input port1(101) | (TF) | FF
input port2(101) | (FT) | FF
expression for output(102) |
input port1(102) | (TF) | FF
input port2(102) | (FT) | FF
expression for output(103) |
input port1(103) | (TF) | FF
input port2(103) | (FT) | FF
expression for output(104) |
input port1(104) | (TF) | FF
input port2(104) | (FT) | FF
expression for output(105) |
input port1(105) | (TF) | FF
input port2(105) | (FT) | FF
expression for output(106) |
input port1(106) | (TF) | FF
input port2(106) | (FT) | FF
expression for output(107) |
input port1(107) | (TF) | FF
input port2(107) | (FT) | FF
expression for output(108) |
input port1(108) | (TF) | FF
input port2(108) | (FT) | FF
expression for output(109) |
input port1(109) | (TF) | FF
input port2(109) | (FT) | FF
expression for output(110) |
input port1(110) | (TF) | FF
input port2(110) | (FT) | FF
expression for output(111) |
input port1(111) | (TF) | FF
input port2(111) | (FT) | FF
expression for output(112) |
input port1(112) | (TF) | FF
input port2(112) | (FT) | FF

#### Logic block "Logical Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (113/226) condition outcomes
MCDC | 0% (0/224) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 0 | 1001
input port1(2) | 0 | 1001
input port1(3) | 0 | 1001
input port1(4) | 0 | 1001
input port1(5) | 0 | 1001
input port1(6) | 0 | 1001
input port1(7) | 0 | 1001
input port1(8) | 0 | 1001
input port1(9) | 0 | 1001
input port1(10) | 0 | 1001
input port1(11) | 0 | 1001
input port1(12) | 0 | 1001
input port1(13) | 0 | 1001
input port1(14) | 0 | 1001
input port1(15) | 0 | 1001
input port1(16) | 0 | 1001
input port1(17) | 0 | 1001
input port1(18) | 0 | 1001
input port1(19) | 0 | 1001
input port1(20) | 0 | 1001
input port1(21) | 0 | 1001
input port1(22) | 0 | 1001
input port1(23) | 0 | 1001
input port1(24) | 0 | 1001
input port1(25) | 0 | 1001
input port1(26) | 0 | 1001
input port1(27) | 0 | 1001
input port1(28) | 0 | 1001
input port1(29) | 0 | 1001
input port1(30) | 0 | 1001
input port1(31) | 0 | 1001
input port1(32) | 0 | 1001
input port1(33) | 0 | 1001
input port1(34) | 0 | 1001
input port1(35) | 0 | 1001
input port1(36) | 0 | 1001
input port1(37) | 0 | 1001
input port1(38) | 0 | 1001
input port1(39) | 0 | 1001
input port1(40) | 0 | 1001
input port1(41) | 0 | 1001
input port1(42) | 0 | 1001
input port1(43) | 0 | 1001
input port1(44) | 0 | 1001
input port1(45) | 0 | 1001
input port1(46) | 0 | 1001
input port1(47) | 0 | 1001
input port1(48) | 0 | 1001
input port1(49) | 0 | 1001
input port1(50) | 0 | 1001
input port1(51) | 0 | 1001
input port1(52) | 0 | 1001
input port1(53) | 0 | 1001
input port1(54) | 0 | 1001
input port1(55) | 0 | 1001
input port1(56) | 0 | 1001
input port1(57) | 0 | 1001
input port1(58) | 0 | 1001
input port1(59) | 0 | 1001
input port1(60) | 0 | 1001
input port1(61) | 0 | 1001
input port1(62) | 0 | 1001
input port1(63) | 0 | 1001
input port1(64) | 0 | 1001
input port1(65) | 0 | 1001
input port1(66) | 0 | 1001
input port1(67) | 0 | 1001
input port1(68) | 0 | 1001
input port1(69) | 0 | 1001
input port1(70) | 0 | 1001
input port1(71) | 0 | 1001
input port1(72) | 0 | 1001
input port1(73) | 0 | 1001
input port1(74) | 0 | 1001
input port1(75) | 0 | 1001
input port1(76) | 0 | 1001
input port1(77) | 0 | 1001
input port1(78) | 0 | 1001
input port1(79) | 0 | 1001
input port1(80) | 0 | 1001
input port1(81) | 0 | 1001
input port1(82) | 0 | 1001
input port1(83) | 0 | 1001
input port1(84) | 0 | 1001
input port1(85) | 0 | 1001
input port1(86) | 0 | 1001
input port1(87) | 0 | 1001
input port1(88) | 0 | 1001
input port1(89) | 0 | 1001
input port1(90) | 0 | 1001
input port1(91) | 0 | 1001
input port1(92) | 0 | 1001
input port1(93) | 0 | 1001
input port1(94) | 0 | 1001
input port1(95) | 0 | 1001
input port1(96) | 0 | 1001
input port1(97) | 0 | 1001
input port1(98) | 0 | 1001
input port1(99) | 0 | 1001
input port1(100) | 0 | 1001
input port1(101) | 0 | 1001
input port1(102) | 0 | 1001
input port1(103) | 0 | 1001
input port1(104) | 0 | 1001
input port1(105) | 0 | 1001
input port1(106) | 0 | 1001
input port1(107) | 0 | 1001
input port1(108) | 0 | 1001
input port1(109) | 0 | 1001
input port1(110) | 0 | 1001
input port1(111) | 0 | 1001
input port1(112) | 0 | 1001
input port 2 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output(1) |
input port1(1) | (TF) | FF
input port 2 | (FT) | FF
expression for output(2) |
input port1(2) | (TF) | FF
input port 2 | (FT) | FF
expression for output(3) |
input port1(3) | (TF) | FF
input port 2 | (FT) | FF
expression for output(4) |
input port1(4) | (TF) | FF
input port 2 | (FT) | FF
expression for output(5) |
input port1(5) | (TF) | FF
input port 2 | (FT) | FF
expression for output(6) |
input port1(6) | (TF) | FF
input port 2 | (FT) | FF
expression for output(7) |
input port1(7) | (TF) | FF
input port 2 | (FT) | FF
expression for output(8) |
input port1(8) | (TF) | FF
input port 2 | (FT) | FF
expression for output(9) |
input port1(9) | (TF) | FF
input port 2 | (FT) | FF
expression for output(10) |
input port1(10) | (TF) | FF
input port 2 | (FT) | FF
expression for output(11) |
input port1(11) | (TF) | FF
input port 2 | (FT) | FF
expression for output(12) |
input port1(12) | (TF) | FF
input port 2 | (FT) | FF
expression for output(13) |
input port1(13) | (TF) | FF
input port 2 | (FT) | FF
expression for output(14) |
input port1(14) | (TF) | FF
input port 2 | (FT) | FF
expression for output(15) |
input port1(15) | (TF) | FF
input port 2 | (FT) | FF
expression for output(16) |
input port1(16) | (TF) | FF
input port 2 | (FT) | FF
expression for output(17) |
input port1(17) | (TF) | FF
input port 2 | (FT) | FF
expression for output(18) |
input port1(18) | (TF) | FF
input port 2 | (FT) | FF
expression for output(19) |
input port1(19) | (TF) | FF
input port 2 | (FT) | FF
expression for output(20) |
input port1(20) | (TF) | FF
input port 2 | (FT) | FF
expression for output(21) |
input port1(21) | (TF) | FF
input port 2 | (FT) | FF
expression for output(22) |
input port1(22) | (TF) | FF
input port 2 | (FT) | FF
expression for output(23) |
input port1(23) | (TF) | FF
input port 2 | (FT) | FF
expression for output(24) |
input port1(24) | (TF) | FF
input port 2 | (FT) | FF
expression for output(25) |
input port1(25) | (TF) | FF
input port 2 | (FT) | FF
expression for output(26) |
input port1(26) | (TF) | FF
input port 2 | (FT) | FF
expression for output(27) |
input port1(27) | (TF) | FF
input port 2 | (FT) | FF
expression for output(28) |
input port1(28) | (TF) | FF
input port 2 | (FT) | FF
expression for output(29) |
input port1(29) | (TF) | FF
input port 2 | (FT) | FF
expression for output(30) |
input port1(30) | (TF) | FF
input port 2 | (FT) | FF
expression for output(31) |
input port1(31) | (TF) | FF
input port 2 | (FT) | FF
expression for output(32) |
input port1(32) | (TF) | FF
input port 2 | (FT) | FF
expression for output(33) |
input port1(33) | (TF) | FF
input port 2 | (FT) | FF
expression for output(34) |
input port1(34) | (TF) | FF
input port 2 | (FT) | FF
expression for output(35) |
input port1(35) | (TF) | FF
input port 2 | (FT) | FF
expression for output(36) |
input port1(36) | (TF) | FF
input port 2 | (FT) | FF
expression for output(37) |
input port1(37) | (TF) | FF
input port 2 | (FT) | FF
expression for output(38) |
input port1(38) | (TF) | FF
input port 2 | (FT) | FF
expression for output(39) |
input port1(39) | (TF) | FF
input port 2 | (FT) | FF
expression for output(40) |
input port1(40) | (TF) | FF
input port 2 | (FT) | FF
expression for output(41) |
input port1(41) | (TF) | FF
input port 2 | (FT) | FF
expression for output(42) |
input port1(42) | (TF) | FF
input port 2 | (FT) | FF
expression for output(43) |
input port1(43) | (TF) | FF
input port 2 | (FT) | FF
expression for output(44) |
input port1(44) | (TF) | FF
input port 2 | (FT) | FF
expression for output(45) |
input port1(45) | (TF) | FF
input port 2 | (FT) | FF
expression for output(46) |
input port1(46) | (TF) | FF
input port 2 | (FT) | FF
expression for output(47) |
input port1(47) | (TF) | FF
input port 2 | (FT) | FF
expression for output(48) |
input port1(48) | (TF) | FF
input port 2 | (FT) | FF
expression for output(49) |
input port1(49) | (TF) | FF
input port 2 | (FT) | FF
expression for output(50) |
input port1(50) | (TF) | FF
input port 2 | (FT) | FF
expression for output(51) |
input port1(51) | (TF) | FF
input port 2 | (FT) | FF
expression for output(52) |
input port1(52) | (TF) | FF
input port 2 | (FT) | FF
expression for output(53) |
input port1(53) | (TF) | FF
input port 2 | (FT) | FF
expression for output(54) |
input port1(54) | (TF) | FF
input port 2 | (FT) | FF
expression for output(55) |
input port1(55) | (TF) | FF
input port 2 | (FT) | FF
expression for output(56) |
input port1(56) | (TF) | FF
input port 2 | (FT) | FF
expression for output(57) |
input port1(57) | (TF) | FF
input port 2 | (FT) | FF
expression for output(58) |
input port1(58) | (TF) | FF
input port 2 | (FT) | FF
expression for output(59) |
input port1(59) | (TF) | FF
input port 2 | (FT) | FF
expression for output(60) |
input port1(60) | (TF) | FF
input port 2 | (FT) | FF
expression for output(61) |
input port1(61) | (TF) | FF
input port 2 | (FT) | FF
expression for output(62) |
input port1(62) | (TF) | FF
input port 2 | (FT) | FF
expression for output(63) |
input port1(63) | (TF) | FF
input port 2 | (FT) | FF
expression for output(64) |
input port1(64) | (TF) | FF
input port 2 | (FT) | FF
expression for output(65) |
input port1(65) | (TF) | FF
input port 2 | (FT) | FF
expression for output(66) |
input port1(66) | (TF) | FF
input port 2 | (FT) | FF
expression for output(67) |
input port1(67) | (TF) | FF
input port 2 | (FT) | FF
expression for output(68) |
input port1(68) | (TF) | FF
input port 2 | (FT) | FF
expression for output(69) |
input port1(69) | (TF) | FF
input port 2 | (FT) | FF
expression for output(70) |
input port1(70) | (TF) | FF
input port 2 | (FT) | FF
expression for output(71) |
input port1(71) | (TF) | FF
input port 2 | (FT) | FF
expression for output(72) |
input port1(72) | (TF) | FF
input port 2 | (FT) | FF
expression for output(73) |
input port1(73) | (TF) | FF
input port 2 | (FT) | FF
expression for output(74) |
input port1(74) | (TF) | FF
input port 2 | (FT) | FF
expression for output(75) |
input port1(75) | (TF) | FF
input port 2 | (FT) | FF
expression for output(76) |
input port1(76) | (TF) | FF
input port 2 | (FT) | FF
expression for output(77) |
input port1(77) | (TF) | FF
input port 2 | (FT) | FF
expression for output(78) |
input port1(78) | (TF) | FF
input port 2 | (FT) | FF
expression for output(79) |
input port1(79) | (TF) | FF
input port 2 | (FT) | FF
expression for output(80) |
input port1(80) | (TF) | FF
input port 2 | (FT) | FF
expression for output(81) |
input port1(81) | (TF) | FF
input port 2 | (FT) | FF
expression for output(82) |
input port1(82) | (TF) | FF
input port 2 | (FT) | FF
expression for output(83) |
input port1(83) | (TF) | FF
input port 2 | (FT) | FF
expression for output(84) |
input port1(84) | (TF) | FF
input port 2 | (FT) | FF
expression for output(85) |
input port1(85) | (TF) | FF
input port 2 | (FT) | FF
expression for output(86) |
input port1(86) | (TF) | FF
input port 2 | (FT) | FF
expression for output(87) |
input port1(87) | (TF) | FF
input port 2 | (FT) | FF
expression for output(88) |
input port1(88) | (TF) | FF
input port 2 | (FT) | FF
expression for output(89) |
input port1(89) | (TF) | FF
input port 2 | (FT) | FF
expression for output(90) |
input port1(90) | (TF) | FF
input port 2 | (FT) | FF
expression for output(91) |
input port1(91) | (TF) | FF
input port 2 | (FT) | FF
expression for output(92) |
input port1(92) | (TF) | FF
input port 2 | (FT) | FF
expression for output(93) |
input port1(93) | (TF) | FF
input port 2 | (FT) | FF
expression for output(94) |
input port1(94) | (TF) | FF
input port 2 | (FT) | FF
expression for output(95) |
input port1(95) | (TF) | FF
input port 2 | (FT) | FF
expression for output(96) |
input port1(96) | (TF) | FF
input port 2 | (FT) | FF
expression for output(97) |
input port1(97) | (TF) | FF
input port 2 | (FT) | FF
expression for output(98) |
input port1(98) | (TF) | FF
input port 2 | (FT) | FF
expression for output(99) |
input port1(99) | (TF) | FF
input port 2 | (FT) | FF
expression for output(100) |
input port1(100) | (TF) | FF
input port 2 | (FT) | FF
expression for output(101) |
input port1(101) | (TF) | FF
input port 2 | (FT) | FF
expression for output(102) |
input port1(102) | (TF) | FF
input port 2 | (FT) | FF
expression for output(103) |
input port1(103) | (TF) | FF
input port 2 | (FT) | FF
expression for output(104) |
input port1(104) | (TF) | FF
input port 2 | (FT) | FF
expression for output(105) |
input port1(105) | (TF) | FF
input port 2 | (FT) | FF
expression for output(106) |
input port1(106) | (TF) | FF
input port 2 | (FT) | FF
expression for output(107) |
input port1(107) | (TF) | FF
input port 2 | (FT) | FF
expression for output(108) |
input port1(108) | (TF) | FF
input port 2 | (FT) | FF
expression for output(109) |
input port1(109) | (TF) | FF
input port 2 | (FT) | FF
expression for output(110) |
input port1(110) | (TF) | FF
input port 2 | (FT) | FF
expression for output(111) |
input port1(111) | (TF) | FF
input port 2 | (FT) | FF
expression for output(112) |
input port1(112) | (TF) | FF
input port 2 | (FT) | FF

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 112
Decision | 50% (112/224) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input(1) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(2) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(3) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(4) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(5) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(6) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(7) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(8) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(9) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(10) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(11) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(12) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(13) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(14) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(15) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(16) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(17) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(18) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(19) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(20) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(21) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(22) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(23) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(24) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(25) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(26) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(27) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(28) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(29) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(30) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(31) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(32) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(33) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(34) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(35) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(36) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(37) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(38) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(39) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(40) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(41) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(42) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(43) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(44) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(45) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(46) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(47) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(48) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(49) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(50) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(51) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(52) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(53) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(54) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(55) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(56) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(57) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(58) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(59) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(60) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(61) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(62) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(63) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(64) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(65) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(66) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(67) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(68) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(69) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(70) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(71) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(72) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(73) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(74) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(75) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(76) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(77) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(78) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(79) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(80) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(81) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(82) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(83) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(84) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(85) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(86) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(87) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(88) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(89) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(90) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(91) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(92) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(93) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(94) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(95) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(96) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(97) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(98) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(99) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(100) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(101) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(102) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(103) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(104) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(105) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(106) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(107) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(108) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(109) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(110) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(111) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(112) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Switch block "Switch1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### RelationalOperator block "Comparison1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (112/224) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) == input2 | 0 | 1001
input1(2) == input2 | 0 | 1001
input1(3) == input2 | 0 | 1001
input1(4) == input2 | 0 | 1001
input1(5) == input2 | 0 | 1001
input1(6) == input2 | 0 | 1001
input1(7) == input2 | 0 | 1001
input1(8) == input2 | 0 | 1001
input1(9) == input2 | 0 | 1001
input1(10) == input2 | 0 | 1001
input1(11) == input2 | 0 | 1001
input1(12) == input2 | 0 | 1001
input1(13) == input2 | 0 | 1001
input1(14) == input2 | 0 | 1001
input1(15) == input2 | 0 | 1001
input1(16) == input2 | 0 | 1001
input1(17) == input2 | 0 | 1001
input1(18) == input2 | 0 | 1001
input1(19) == input2 | 0 | 1001
input1(20) == input2 | 0 | 1001
input1(21) == input2 | 0 | 1001
input1(22) == input2 | 0 | 1001
input1(23) == input2 | 0 | 1001
input1(24) == input2 | 0 | 1001
input1(25) == input2 | 0 | 1001
input1(26) == input2 | 0 | 1001
input1(27) == input2 | 0 | 1001
input1(28) == input2 | 0 | 1001
input1(29) == input2 | 0 | 1001
input1(30) == input2 | 0 | 1001
input1(31) == input2 | 0 | 1001
input1(32) == input2 | 0 | 1001
input1(33) == input2 | 0 | 1001
input1(34) == input2 | 0 | 1001
input1(35) == input2 | 0 | 1001
input1(36) == input2 | 0 | 1001
input1(37) == input2 | 0 | 1001
input1(38) == input2 | 0 | 1001
input1(39) == input2 | 0 | 1001
input1(40) == input2 | 0 | 1001
input1(41) == input2 | 0 | 1001
input1(42) == input2 | 0 | 1001
input1(43) == input2 | 0 | 1001
input1(44) == input2 | 0 | 1001
input1(45) == input2 | 0 | 1001
input1(46) == input2 | 0 | 1001
input1(47) == input2 | 0 | 1001
input1(48) == input2 | 0 | 1001
input1(49) == input2 | 0 | 1001
input1(50) == input2 | 0 | 1001
input1(51) == input2 | 0 | 1001
input1(52) == input2 | 0 | 1001
input1(53) == input2 | 0 | 1001
input1(54) == input2 | 0 | 1001
input1(55) == input2 | 0 | 1001
input1(56) == input2 | 0 | 1001
input1(57) == input2 | 0 | 1001
input1(58) == input2 | 0 | 1001
input1(59) == input2 | 0 | 1001
input1(60) == input2 | 0 | 1001
input1(61) == input2 | 0 | 1001
input1(62) == input2 | 0 | 1001
input1(63) == input2 | 0 | 1001
input1(64) == input2 | 0 | 1001
input1(65) == input2 | 0 | 1001
input1(66) == input2 | 0 | 1001
input1(67) == input2 | 0 | 1001
input1(68) == input2 | 0 | 1001
input1(69) == input2 | 0 | 1001
input1(70) == input2 | 0 | 1001
input1(71) == input2 | 0 | 1001
input1(72) == input2 | 0 | 1001
input1(73) == input2 | 0 | 1001
input1(74) == input2 | 0 | 1001
input1(75) == input2 | 0 | 1001
input1(76) == input2 | 0 | 1001
input1(77) == input2 | 0 | 1001
input1(78) == input2 | 0 | 1001
input1(79) == input2 | 0 | 1001
input1(80) == input2 | 0 | 1001
input1(81) == input2 | 0 | 1001
input1(82) == input2 | 0 | 1001
input1(83) == input2 | 0 | 1001
input1(84) == input2 | 0 | 1001
input1(85) == input2 | 0 | 1001
input1(86) == input2 | 0 | 1001
input1(87) == input2 | 0 | 1001
input1(88) == input2 | 0 | 1001
input1(89) == input2 | 0 | 1001
input1(90) == input2 | 0 | 1001
input1(91) == input2 | 0 | 1001
input1(92) == input2 | 0 | 1001
input1(93) == input2 | 0 | 1001
input1(94) == input2 | 0 | 1001
input1(95) == input2 | 0 | 1001
input1(96) == input2 | 0 | 1001
input1(97) == input2 | 0 | 1001
input1(98) == input2 | 0 | 1001
input1(99) == input2 | 0 | 1001
input1(100) == input2 | 0 | 1001
input1(101) == input2 | 0 | 1001
input1(102) == input2 | 0 | 1001
input1(103) == input2 | 0 | 1001
input1(104) == input2 | 0 | 1001
input1(105) == input2 | 0 | 1001
input1(106) == input2 | 0 | 1001
input1(107) == input2 | 0 | 1001
input1(108) == input2 | 0 | 1001
input1(109) == input2 | 0 | 1001
input1(110) == input2 | 0 | 1001
input1(111) == input2 | 0 | 1001
input1(112) == input2 | 0 | 1001

#### RelationalOperator block "Comparison4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (112/224) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) == input2 | 1001 | 0
input1(2) == input2 | 1001 | 0
input1(3) == input2 | 1001 | 0
input1(4) == input2 | 1001 | 0
input1(5) == input2 | 1001 | 0
input1(6) == input2 | 1001 | 0
input1(7) == input2 | 1001 | 0
input1(8) == input2 | 1001 | 0
input1(9) == input2 | 1001 | 0
input1(10) == input2 | 1001 | 0
input1(11) == input2 | 1001 | 0
input1(12) == input2 | 1001 | 0
input1(13) == input2 | 1001 | 0
input1(14) == input2 | 1001 | 0
input1(15) == input2 | 1001 | 0
input1(16) == input2 | 1001 | 0
input1(17) == input2 | 1001 | 0
input1(18) == input2 | 1001 | 0
input1(19) == input2 | 1001 | 0
input1(20) == input2 | 1001 | 0
input1(21) == input2 | 1001 | 0
input1(22) == input2 | 1001 | 0
input1(23) == input2 | 1001 | 0
input1(24) == input2 | 1001 | 0
input1(25) == input2 | 1001 | 0
input1(26) == input2 | 1001 | 0
input1(27) == input2 | 1001 | 0
input1(28) == input2 | 1001 | 0
input1(29) == input2 | 1001 | 0
input1(30) == input2 | 1001 | 0
input1(31) == input2 | 1001 | 0
input1(32) == input2 | 1001 | 0
input1(33) == input2 | 1001 | 0
input1(34) == input2 | 1001 | 0
input1(35) == input2 | 1001 | 0
input1(36) == input2 | 1001 | 0
input1(37) == input2 | 1001 | 0
input1(38) == input2 | 1001 | 0
input1(39) == input2 | 1001 | 0
input1(40) == input2 | 1001 | 0
input1(41) == input2 | 1001 | 0
input1(42) == input2 | 1001 | 0
input1(43) == input2 | 1001 | 0
input1(44) == input2 | 1001 | 0
input1(45) == input2 | 1001 | 0
input1(46) == input2 | 1001 | 0
input1(47) == input2 | 1001 | 0
input1(48) == input2 | 1001 | 0
input1(49) == input2 | 1001 | 0
input1(50) == input2 | 1001 | 0
input1(51) == input2 | 1001 | 0
input1(52) == input2 | 1001 | 0
input1(53) == input2 | 1001 | 0
input1(54) == input2 | 1001 | 0
input1(55) == input2 | 1001 | 0
input1(56) == input2 | 1001 | 0
input1(57) == input2 | 1001 | 0
input1(58) == input2 | 1001 | 0
input1(59) == input2 | 1001 | 0
input1(60) == input2 | 1001 | 0
input1(61) == input2 | 1001 | 0
input1(62) == input2 | 1001 | 0
input1(63) == input2 | 1001 | 0
input1(64) == input2 | 1001 | 0
input1(65) == input2 | 1001 | 0
input1(66) == input2 | 1001 | 0
input1(67) == input2 | 1001 | 0
input1(68) == input2 | 1001 | 0
input1(69) == input2 | 1001 | 0
input1(70) == input2 | 1001 | 0
input1(71) == input2 | 1001 | 0
input1(72) == input2 | 1001 | 0
input1(73) == input2 | 1001 | 0
input1(74) == input2 | 1001 | 0
input1(75) == input2 | 1001 | 0
input1(76) == input2 | 1001 | 0
input1(77) == input2 | 1001 | 0
input1(78) == input2 | 1001 | 0
input1(79) == input2 | 1001 | 0
input1(80) == input2 | 1001 | 0
input1(81) == input2 | 1001 | 0
input1(82) == input2 | 1001 | 0
input1(83) == input2 | 1001 | 0
input1(84) == input2 | 1001 | 0
input1(85) == input2 | 1001 | 0
input1(86) == input2 | 1001 | 0
input1(87) == input2 | 1001 | 0
input1(88) == input2 | 1001 | 0
input1(89) == input2 | 1001 | 0
input1(90) == input2 | 1001 | 0
input1(91) == input2 | 1001 | 0
input1(92) == input2 | 1001 | 0
input1(93) == input2 | 1001 | 0
input1(94) == input2 | 1001 | 0
input1(95) == input2 | 1001 | 0
input1(96) == input2 | 1001 | 0
input1(97) == input2 | 1001 | 0
input1(98) == input2 | 1001 | 0
input1(99) == input2 | 1001 | 0
input1(100) == input2 | 1001 | 0
input1(101) == input2 | 1001 | 0
input1(102) == input2 | 1001 | 0
input1(103) == input2 | 1001 | 0
input1(104) == input2 | 1001 | 0
input1(105) == input2 | 1001 | 0
input1(106) == input2 | 1001 | 0
input1(107) == input2 | 1001 | 0
input1(108) == input2 | 1001 | 0
input1(109) == input2 | 1001 | 0
input1(110) == input2 | 1001 | 0
input1(111) == input2 | 1001 | 0
input1(112) == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (112/224) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) ~= input2 | 0 | 1001
input1(2) ~= input2 | 0 | 1001
input1(3) ~= input2 | 0 | 1001
input1(4) ~= input2 | 0 | 1001
input1(5) ~= input2 | 0 | 1001
input1(6) ~= input2 | 0 | 1001
input1(7) ~= input2 | 0 | 1001
input1(8) ~= input2 | 0 | 1001
input1(9) ~= input2 | 0 | 1001
input1(10) ~= input2 | 0 | 1001
input1(11) ~= input2 | 0 | 1001
input1(12) ~= input2 | 0 | 1001
input1(13) ~= input2 | 0 | 1001
input1(14) ~= input2 | 0 | 1001
input1(15) ~= input2 | 0 | 1001
input1(16) ~= input2 | 0 | 1001
input1(17) ~= input2 | 0 | 1001
input1(18) ~= input2 | 0 | 1001
input1(19) ~= input2 | 0 | 1001
input1(20) ~= input2 | 0 | 1001
input1(21) ~= input2 | 0 | 1001
input1(22) ~= input2 | 0 | 1001
input1(23) ~= input2 | 0 | 1001
input1(24) ~= input2 | 0 | 1001
input1(25) ~= input2 | 0 | 1001
input1(26) ~= input2 | 0 | 1001
input1(27) ~= input2 | 0 | 1001
input1(28) ~= input2 | 0 | 1001
input1(29) ~= input2 | 0 | 1001
input1(30) ~= input2 | 0 | 1001
input1(31) ~= input2 | 0 | 1001
input1(32) ~= input2 | 0 | 1001
input1(33) ~= input2 | 0 | 1001
input1(34) ~= input2 | 0 | 1001
input1(35) ~= input2 | 0 | 1001
input1(36) ~= input2 | 0 | 1001
input1(37) ~= input2 | 0 | 1001
input1(38) ~= input2 | 0 | 1001
input1(39) ~= input2 | 0 | 1001
input1(40) ~= input2 | 0 | 1001
input1(41) ~= input2 | 0 | 1001
input1(42) ~= input2 | 0 | 1001
input1(43) ~= input2 | 0 | 1001
input1(44) ~= input2 | 0 | 1001
input1(45) ~= input2 | 0 | 1001
input1(46) ~= input2 | 0 | 1001
input1(47) ~= input2 | 0 | 1001
input1(48) ~= input2 | 0 | 1001
input1(49) ~= input2 | 0 | 1001
input1(50) ~= input2 | 0 | 1001
input1(51) ~= input2 | 0 | 1001
input1(52) ~= input2 | 0 | 1001
input1(53) ~= input2 | 0 | 1001
input1(54) ~= input2 | 0 | 1001
input1(55) ~= input2 | 0 | 1001
input1(56) ~= input2 | 0 | 1001
input1(57) ~= input2 | 0 | 1001
input1(58) ~= input2 | 0 | 1001
input1(59) ~= input2 | 0 | 1001
input1(60) ~= input2 | 0 | 1001
input1(61) ~= input2 | 0 | 1001
input1(62) ~= input2 | 0 | 1001
input1(63) ~= input2 | 0 | 1001
input1(64) ~= input2 | 0 | 1001
input1(65) ~= input2 | 0 | 1001
input1(66) ~= input2 | 0 | 1001
input1(67) ~= input2 | 0 | 1001
input1(68) ~= input2 | 0 | 1001
input1(69) ~= input2 | 0 | 1001
input1(70) ~= input2 | 0 | 1001
input1(71) ~= input2 | 0 | 1001
input1(72) ~= input2 | 0 | 1001
input1(73) ~= input2 | 0 | 1001
input1(74) ~= input2 | 0 | 1001
input1(75) ~= input2 | 0 | 1001
input1(76) ~= input2 | 0 | 1001
input1(77) ~= input2 | 0 | 1001
input1(78) ~= input2 | 0 | 1001
input1(79) ~= input2 | 0 | 1001
input1(80) ~= input2 | 0 | 1001
input1(81) ~= input2 | 0 | 1001
input1(82) ~= input2 | 0 | 1001
input1(83) ~= input2 | 0 | 1001
input1(84) ~= input2 | 0 | 1001
input1(85) ~= input2 | 0 | 1001
input1(86) ~= input2 | 0 | 1001
input1(87) ~= input2 | 0 | 1001
input1(88) ~= input2 | 0 | 1001
input1(89) ~= input2 | 0 | 1001
input1(90) ~= input2 | 0 | 1001
input1(91) ~= input2 | 0 | 1001
input1(92) ~= input2 | 0 | 1001
input1(93) ~= input2 | 0 | 1001
input1(94) ~= input2 | 0 | 1001
input1(95) ~= input2 | 0 | 1001
input1(96) ~= input2 | 0 | 1001
input1(97) ~= input2 | 0 | 1001
input1(98) ~= input2 | 0 | 1001
input1(99) ~= input2 | 0 | 1001
input1(100) ~= input2 | 0 | 1001
input1(101) ~= input2 | 0 | 1001
input1(102) ~= input2 | 0 | 1001
input1(103) ~= input2 | 0 | 1001
input1(104) ~= input2 | 0 | 1001
input1(105) ~= input2 | 0 | 1001
input1(106) ~= input2 | 0 | 1001
input1(107) ~= input2 | 0 | 1001
input1(108) ~= input2 | 0 | 1001
input1(109) ~= input2 | 0 | 1001
input1(110) ~= input2 | 0 | 1001
input1(111) ~= input2 | 0 | 1001
input1(112) ~= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution
S-Function block "Bitwise Logical Operator" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution
Constant block "Constant5" | Execution
UnitDelay block "Unit Delay" | Execution

### 427. SubSystem block "CellVolt_SignalFilt"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output
Child Systems: | 1D_Config_Word, InputValueCalc, MaxValue_sort, OverWrite
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 28
Condition | NA | 50% (112/224) condition outcomes
Decision | NA | 31% (12/39) decision outcomes
Execution | NA | 100% (18/18) objective outcomes

#### RelationalOperator block "Comparison1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (112/224) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) == input2 | 1001 | 0
input1(2) == input2 | 1001 | 0
input1(3) == input2 | 1001 | 0
input1(4) == input2 | 1001 | 0
input1(5) == input2 | 1001 | 0
input1(6) == input2 | 1001 | 0
input1(7) == input2 | 1001 | 0
input1(8) == input2 | 1001 | 0
input1(9) == input2 | 1001 | 0
input1(10) == input2 | 1001 | 0
input1(11) == input2 | 1001 | 0
input1(12) == input2 | 1001 | 0
input1(13) == input2 | 1001 | 0
input1(14) == input2 | 1001 | 0
input1(15) == input2 | 1001 | 0
input1(16) == input2 | 1001 | 0
input1(17) == input2 | 1001 | 0
input1(18) == input2 | 1001 | 0
input1(19) == input2 | 1001 | 0
input1(20) == input2 | 1001 | 0
input1(21) == input2 | 1001 | 0
input1(22) == input2 | 1001 | 0
input1(23) == input2 | 1001 | 0
input1(24) == input2 | 1001 | 0
input1(25) == input2 | 1001 | 0
input1(26) == input2 | 1001 | 0
input1(27) == input2 | 1001 | 0
input1(28) == input2 | 1001 | 0
input1(29) == input2 | 1001 | 0
input1(30) == input2 | 1001 | 0
input1(31) == input2 | 1001 | 0
input1(32) == input2 | 1001 | 0
input1(33) == input2 | 1001 | 0
input1(34) == input2 | 1001 | 0
input1(35) == input2 | 1001 | 0
input1(36) == input2 | 1001 | 0
input1(37) == input2 | 1001 | 0
input1(38) == input2 | 1001 | 0
input1(39) == input2 | 1001 | 0
input1(40) == input2 | 1001 | 0
input1(41) == input2 | 1001 | 0
input1(42) == input2 | 1001 | 0
input1(43) == input2 | 1001 | 0
input1(44) == input2 | 1001 | 0
input1(45) == input2 | 1001 | 0
input1(46) == input2 | 1001 | 0
input1(47) == input2 | 1001 | 0
input1(48) == input2 | 1001 | 0
input1(49) == input2 | 1001 | 0
input1(50) == input2 | 1001 | 0
input1(51) == input2 | 1001 | 0
input1(52) == input2 | 1001 | 0
input1(53) == input2 | 1001 | 0
input1(54) == input2 | 1001 | 0
input1(55) == input2 | 1001 | 0
input1(56) == input2 | 1001 | 0
input1(57) == input2 | 1001 | 0
input1(58) == input2 | 1001 | 0
input1(59) == input2 | 1001 | 0
input1(60) == input2 | 1001 | 0
input1(61) == input2 | 1001 | 0
input1(62) == input2 | 1001 | 0
input1(63) == input2 | 1001 | 0
input1(64) == input2 | 1001 | 0
input1(65) == input2 | 1001 | 0
input1(66) == input2 | 1001 | 0
input1(67) == input2 | 1001 | 0
input1(68) == input2 | 1001 | 0
input1(69) == input2 | 1001 | 0
input1(70) == input2 | 1001 | 0
input1(71) == input2 | 1001 | 0
input1(72) == input2 | 1001 | 0
input1(73) == input2 | 1001 | 0
input1(74) == input2 | 1001 | 0
input1(75) == input2 | 1001 | 0
input1(76) == input2 | 1001 | 0
input1(77) == input2 | 1001 | 0
input1(78) == input2 | 1001 | 0
input1(79) == input2 | 1001 | 0
input1(80) == input2 | 1001 | 0
input1(81) == input2 | 1001 | 0
input1(82) == input2 | 1001 | 0
input1(83) == input2 | 1001 | 0
input1(84) == input2 | 1001 | 0
input1(85) == input2 | 1001 | 0
input1(86) == input2 | 1001 | 0
input1(87) == input2 | 1001 | 0
input1(88) == input2 | 1001 | 0
input1(89) == input2 | 1001 | 0
input1(90) == input2 | 1001 | 0
input1(91) == input2 | 1001 | 0
input1(92) == input2 | 1001 | 0
input1(93) == input2 | 1001 | 0
input1(94) == input2 | 1001 | 0
input1(95) == input2 | 1001 | 0
input1(96) == input2 | 1001 | 0
input1(97) == input2 | 1001 | 0
input1(98) == input2 | 1001 | 0
input1(99) == input2 | 1001 | 0
input1(100) == input2 | 1001 | 0
input1(101) == input2 | 1001 | 0
input1(102) == input2 | 1001 | 0
input1(103) == input2 | 1001 | 0
input1(104) == input2 | 1001 | 0
input1(105) == input2 | 1001 | 0
input1(106) == input2 | 1001 | 0
input1(107) == input2 | 1001 | 0
input1(108) == input2 | 1001 | 0
input1(109) == input2 | 1001 | 0
input1(110) == input2 | 1001 | 0
input1(111) == input2 | 1001 | 0
input1(112) == input2 | 1001 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant2" | Execution
UnitDelay block "Unit Delay21" | Execution

### 428. SubSystem block "1D_Config_Word"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt
Child Systems: | Switch Case Action Subsystem, Switch Case Action Subsystem1, Switch Case Action Subsystem2, Switch Case Action Subsystem3, Switch Case Action Subsystem4, Switch Case Action Subsystem5, Switch Case Action Subsystem6, Switch Case Action Subsystem7, Switch Case Action Subsystem8, Switch Case Action Subsystem9
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 11
Decision | NA | 9% (1/11) decision outcomes
Execution | NA | 100% (12/12) objective outcomes

#### SwitchCase block "Switch Case"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/1D_Config_Word
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 10
Decision | 9% (1/11) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
truncated input | 9%
= Enum_UDSCapSel_Default | 1001/1001
= Enum_UDSCapSel_CATL153Ah | 0/1001
= Enum_UDSCapSel_CATL180Ah | 0/1001
= Enum_UDSCapSel_CATL177Ah | 0/1001
= Enum_UDSCapSel_CATL203Ah | 0/1001
= Enum_UDSCapSel_CATL51Ah | 0/1001
= Enum_UDSCapSel_CATL132Ah | 0/1001
= Enum_UDSCapSel_XWD75Ah | 0/1001
= Enum_UDSCapSel_TFE177Ah | 0/1001
= Enum_UDSCapSel_CATLCTP248Ah | 0/1001
= implicit-default | 0/1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution

### 429. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 430. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 431. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 432. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 433. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 434. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 435. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 436. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 437. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 438. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 439. SubSystem block "InputValueCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt
Child Systems: | CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/InputValueCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 6
Decision | NA | 50% (5/10) decision outcomes

### 440. Chart "CellDataPrc_20ms_sys/VoltDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/InputValueCalc
Child Systems: | Default, Update
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 5
Decision | 100% (2/2) decision outcomes | 50% (5/10) decision outcomes
Decisions analyzed
Substate executed | 100%
State "Default" | 1/1000
State "Update" | 999/1000

#### Transition "[i >Input_num-1]" from "Default" to "Update"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/InputValueCalc
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 0/1
true | 1/1

### 441. State "Default"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/InputValueCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 1
Decision | NA | 50% (1/2) decision outcomes

#### Transition "[i <Input_num]" from Junction #8 to Junction #9

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/InputValueCalc.Default
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1/1
true | 0/1

### 442. State "Update"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/InputValueCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Decision | NA | 25% (1/4) decision outcomes

#### Transition "[i < Input_num]" from Junction #1 to Junction #2

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/InputValueCalc.Update
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1000/1000
true | 0/1000

#### Transition "[Update[i]]" from Junction #2 to Junction #3

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/InputValueCalc.Update
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
Transition trigger expression | 0%
false | --
true | --

### 443. SubSystem block "MaxValue_sort"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt
Child Systems: | CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/MaxValue_sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 9
Decision | NA | 31% (5/16) decision outcomes

### 444. Chart "CellDataPrc_20ms_sys/VoltDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/MaxValue_sort
Child Systems: | sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 8
Decision | NA | 31% (5/16) decision outcomes

### 445. State "sort"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/MaxValue_sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 8
Decision | NA | 31% (5/16) decision outcomes

#### Transition "[m >= 1]" from Junction #11 to Junction #3

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
Transition trigger expression | 0%
false | --
true | --

#### Transition "[j < Input_num]" from Junction #5 to Junction #9

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1001/1001
true | 0/1001

#### Transition "[k<Input_num]" from Junction #4 to Junction #12

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
Transition trigger expression | 0%
false | --
true | --

#### Transition "[Output_Value[n][k] > Output_Value[m][k]..." from Junction #17 to Junction #14

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
Transition trigger expression | 0%
false | --
true | --

#### Transition "[n>=0]" from Junction #7 to Junction #17

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 0% (0/2) decision outcomes
Decisions analyzed
Transition trigger expression | 0%
false | --
true | --

#### Transition "[k<Input_num]" from Junction #19 to Junction #20

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1001/1001
true | 0/1001

#### Transition "[Input_dim == 1]" from Junction #24 to Junction #23

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 0/1001
true | 1001/1001

#### Full Coverage

Model Object | Metric
Transition "[i < Input_dim]" from Junction #8 to Junction #5 | Decision

### 446. SubSystem block "OverWrite"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_Output/CellVolt_SignalFilt/OverWrite
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 447. SubSystem block "CellVolt_SelfCheck"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys
Child Systems: | OverWrite
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Condition | NA | 50% (8/16) condition outcomes
Decision | NA | 50% (1/2) decision outcomes
MCDC | NA | 0% (0/4) conditions reversed the outcome
Execution | NA | 100% (13/13) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_SelfCheck
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (4/8) condition outcomes
MCDC | 0% (0/4) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 1001 | 0
input port 2 | 1001 | 0
input port 3 | 0 | 1001
input port 4 | 0 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | (TTTT) | (FTTT)
input port 2 | (TTTT) | (TFTT)
input port 3 | (TTTT) | (TTFT)
input port 4 | (TTTT) | (TTTF)

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_SelfCheck
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 1001 | 0

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_SelfCheck
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 0 | 1001

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_SelfCheck
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 1001 | 0

#### RelationalOperator block "Relational Operator4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_SelfCheck
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion1" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution

### 448. SubSystem block "OverWrite"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_SelfCheck
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/CellVolt_SelfCheck/OverWrite
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 449. SubSystem block "MaxMinSum_CellVolt_Get"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys
Child Systems: | CellVoltMax_SignalFilt, CellVoltMin_SignalFilt, MaxMin_CellVolt_Get_Sys, OverWrite, OverWrite1, OverWrite2, OverWrite3, SumCellVoltVld, Sum_CellVolt_Get_Sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 83
Condition | NA | 50% (685/1366) condition outcomes
Decision | NA | 57% (59/104) decision outcomes
MCDC | NA | 0% (0/456) conditions reversed the outcome
Execution | NA | 100% (128/128) objective outcomes

### 450. SubSystem block "CellVoltMax_SignalFilt"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get
Child Systems: | 1D_Config_Word, InputValueCalc, MaxValue_sort, ValueCalc, ValueIndexCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 25
Decision | NA | 52% (16/31) decision outcomes
Execution | NA | 100% (25/25) objective outcomes

#### Full Coverage

Model Object | Metric
UnitDelay block "Unit Delay21" | Execution

### 451. SubSystem block "1D_Config_Word"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt
Child Systems: | Switch Case Action Subsystem, Switch Case Action Subsystem1, Switch Case Action Subsystem2, Switch Case Action Subsystem3, Switch Case Action Subsystem4, Switch Case Action Subsystem5, Switch Case Action Subsystem6, Switch Case Action Subsystem7, Switch Case Action Subsystem8, Switch Case Action Subsystem9
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 11
Decision | NA | 9% (1/11) decision outcomes
Execution | NA | 100% (12/12) objective outcomes

#### SwitchCase block "Switch Case"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/1D_Config_Word
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 10
Decision | 9% (1/11) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
truncated input | 9%
= Enum_UDSCapSel_Default | 1001/1001
= Enum_UDSCapSel_CATL153Ah | 0/1001
= Enum_UDSCapSel_CATL180Ah | 0/1001
= Enum_UDSCapSel_CATL177Ah | 0/1001
= Enum_UDSCapSel_CATL203Ah | 0/1001
= Enum_UDSCapSel_CATL51Ah | 0/1001
= Enum_UDSCapSel_CATL132Ah | 0/1001
= Enum_UDSCapSel_XWD75Ah | 0/1001
= Enum_UDSCapSel_TFE177Ah | 0/1001
= Enum_UDSCapSel_CATLCTP248Ah | 0/1001
= implicit-default | 0/1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution

### 452. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 453. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 454. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 455. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 456. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 457. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 458. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 459. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 460. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 461. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 462. SubSystem block "InputValueCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt
Child Systems: | CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/InputValueCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 4
Decision | NA | 60% (3/5) decision outcomes

### 463. Chart "CellDataPrc_20ms_sys/VoltDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/InputValueCalc
Child Systems: | VldValueFilter
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 3
Decision | NA | 60% (3/5) decision outcomes

### 464. State "VldValueFilter"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/InputValueCalc
Uncovered Links: |
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 2 | 3
Decision | 67% (2/3) decision outcomes | 60% (3/5) decision outcomes
Decisions analyzed
Substate exited when parent exits | 67%
State "Default" | 1/1000
State "NotUpdate" | 0/1000
State "Update" | 999/1000

#### Transition "[Rige]" from Junction #0 to Junction #1

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/InputValueCalc.VldValueFilter
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 0/1000
true | 1000/1000

### 465. SubSystem block "MaxValue_sort"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt
Child Systems: | CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/MaxValue_sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 6
Decision | NA | 90% (9/10) decision outcomes

### 466. Chart "CellDataPrc_20ms_sys/VoltDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/MaxValue_sort
Child Systems: | sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 5
Decision | NA | 90% (9/10) decision outcomes

### 467. State "sort"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/MaxValue_sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 5
Decision | NA | 90% (9/10) decision outcomes

#### Transition "[Output_Value[j] > temp]" from Junction #6 to Junction #5

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/MaxValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1001/1001
true | 0/1001

#### Full Coverage

Model Object | Metric
Transition "[j < Input_dim]" from Junction #13 to Junction #6 | Decision
Transition "[i < Input_dim]" from Junction #10 to Junction #9 | Decision
Transition "[i < Input_dim]" from Junction #15 to Junction #11 | Decision
Transition "[i < Input_dim]" from Junction #4 to Junction #7 | Decision

### 468. SubSystem block "ValueCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (10/10) objective outcomes

#### Full Coverage

Model Object | Metric
Product block "Product1" | Execution
Product block "Product2" | Execution
Sum block "Sum" | Execution
Sum block "Sum1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant4" | Execution
Constant block "Constant6" | Execution
Constant block "Constant7" | Execution
Selector block "Selector" | Execution
Selector block "Selector1" | Execution

### 469. SubSystem block "ValueIndexCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt
Child Systems: | InputValueCalc1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 4
Decision | NA | 60% (3/5) decision outcomes
Execution | NA | 100% (2/2) objective outcomes

#### Full Coverage

Model Object | Metric
Selector block "Selector2" | Execution
UnitDelay block "Unit Delay1" | Execution

### 470. SubSystem block "InputValueCalc1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/ValueIndexCalc
Child Systems: | CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/ValueIndexCalc/InputValueCalc1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 4
Decision | NA | 60% (3/5) decision outcomes

### 471. Chart "CellDataPrc_20ms_sys/VoltDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/ValueIndexCalc/InputValueCalc1
Child Systems: | VldValueFilter
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 3
Decision | NA | 60% (3/5) decision outcomes

### 472. State "VldValueFilter"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/ValueIndexCalc/InputValueCalc1
Uncovered Links: |
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 2 | 3
Decision | 67% (2/3) decision outcomes | 60% (3/5) decision outcomes
Decisions analyzed
Substate exited when parent exits | 67%
State "Default" | 1/1000
State "NotUpdate" | 0/1000
State "Update" | 999/1000

#### Transition "[Rige]" from Junction #0 to Junction #1

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMax_SignalFilt/ValueIndexCalc/InputValueCalc1.VldValueFilter
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 0/1000
true | 1000/1000

### 473. SubSystem block "CellVoltMin_SignalFilt"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get
Child Systems: | 1D_Config_Word, InputValueCalc, MinValue_sort, ValueCalc, ValueIndexCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 25
Decision | NA | 52% (16/31) decision outcomes
Execution | NA | 100% (27/27) objective outcomes

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution
DataTypeConversion block "Data Type Conversion1" | Execution
UnitDelay block "Unit Delay21" | Execution

### 474. SubSystem block "1D_Config_Word"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt
Child Systems: | Switch Case Action Subsystem, Switch Case Action Subsystem1, Switch Case Action Subsystem2, Switch Case Action Subsystem3, Switch Case Action Subsystem4, Switch Case Action Subsystem5, Switch Case Action Subsystem6, Switch Case Action Subsystem7, Switch Case Action Subsystem8, Switch Case Action Subsystem9
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 11
Decision | NA | 9% (1/11) decision outcomes
Execution | NA | 100% (12/12) objective outcomes

#### SwitchCase block "Switch Case"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/1D_Config_Word
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 10
Decision | 9% (1/11) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
truncated input | 9%
= Enum_UDSCapSel_Default | 1001/1001
= Enum_UDSCapSel_CATL153Ah | 0/1001
= Enum_UDSCapSel_CATL180Ah | 0/1001
= Enum_UDSCapSel_CATL177Ah | 0/1001
= Enum_UDSCapSel_CATL203Ah | 0/1001
= Enum_UDSCapSel_CATL51Ah | 0/1001
= Enum_UDSCapSel_CATL132Ah | 0/1001
= Enum_UDSCapSel_XWD75Ah | 0/1001
= Enum_UDSCapSel_TFE177Ah | 0/1001
= Enum_UDSCapSel_CATLCTP248Ah | 0/1001
= implicit-default | 0/1001

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution

### 475. SubSystem block "Switch Case Action Subsystem"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 476. SubSystem block "Switch Case Action Subsystem1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 477. SubSystem block "Switch Case Action Subsystem2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 478. SubSystem block "Switch Case Action Subsystem3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 479. SubSystem block "Switch Case Action Subsystem4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 480. SubSystem block "Switch Case Action Subsystem5"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 481. SubSystem block "Switch Case Action Subsystem6"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 482. SubSystem block "Switch Case Action Subsystem7"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 483. SubSystem block "Switch Case Action Subsystem8"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 484. SubSystem block "Switch Case Action Subsystem9"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/1D_Config_Word
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (1/1) objective outcomes

#### Full Coverage

Model Object | Metric
Constant block "Constant0" | Execution

### 485. SubSystem block "InputValueCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt
Child Systems: | CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/InputValueCalc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 4
Decision | NA | 60% (3/5) decision outcomes

### 486. Chart "CellDataPrc_20ms_sys/VoltDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/InputValueCalc
Child Systems: | VldValueFilter
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 3
Decision | NA | 60% (3/5) decision outcomes

### 487. State "VldValueFilter"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/InputValueCalc
Uncovered Links: |
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 2 | 3
Decision | 67% (2/3) decision outcomes | 60% (3/5) decision outcomes
Decisions analyzed
Substate exited when parent exits | 67%
State "Default" | 1/1000
State "NotUpdate" | 0/1000
State "Update" | 999/1000

#### Transition "[Rige]" from Junction #0 to Junction #1

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/InputValueCalc.VldValueFilter
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 0/1000
true | 1000/1000

### 488. SubSystem block "MinValue_sort"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt
Child Systems: | CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/MinValue_sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 6
Decision | NA | 90% (9/10) decision outcomes

### 489. Chart "CellDataPrc_20ms_sys/VoltDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/MinValue_sort
Child Systems: | sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 5
Decision | NA | 90% (9/10) decision outcomes

### 490. State "sort"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/MinValue_sort
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 5
Decision | NA | 90% (9/10) decision outcomes

#### Transition "[Output_Value[j] > temp]" from Junction #6 to Junction #5

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/MinValue_sort.sort
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 1001/1001
true | 0/1001

#### Full Coverage

Model Object | Metric
Transition "[j < Input_dim]" from Junction #13 to Junction #6 | Decision
Transition "[i < Input_dim]" from Junction #10 to Junction #9 | Decision
Transition "[i < Input_dim]" from Junction #15 to Junction #11 | Decision
Transition "[i < Input_dim]" from Junction #4 to Junction #7 | Decision

### 491. SubSystem block "ValueCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 0
Execution | NA | 100% (10/10) objective outcomes

#### Full Coverage

Model Object | Metric
Product block "Product1" | Execution
Product block "Product2" | Execution
Sum block "Sum" | Execution
Sum block "Sum1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant4" | Execution
Constant block "Constant6" | Execution
Constant block "Constant7" | Execution
Selector block "Selector" | Execution
Selector block "Selector1" | Execution

### 492. SubSystem block "ValueIndexCalc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt
Child Systems: | InputValueCalc1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 4
Decision | NA | 60% (3/5) decision outcomes
Execution | NA | 100% (2/2) objective outcomes

#### Full Coverage

Model Object | Metric
Selector block "Selector2" | Execution
UnitDelay block "Unit Delay1" | Execution

### 493. SubSystem block "InputValueCalc1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/ValueIndexCalc
Child Systems: | CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/ValueIndexCalc/InputValueCalc1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 4
Decision | NA | 60% (3/5) decision outcomes

### 494. Chart "CellDataPrc_20ms_sys/VoltDataPrc_20ms_sy..."

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/ValueIndexCalc/InputValueCalc1
Child Systems: | VldValueFilter
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 3
Decision | NA | 60% (3/5) decision outcomes

### 495. State "VldValueFilter"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/ValueIndexCalc/InputValueCalc1
Uncovered Links: |
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 2 | 3
Decision | 67% (2/3) decision outcomes | 60% (3/5) decision outcomes
Decisions analyzed
Substate exited when parent exits | 67%
State "Default" | 1/1000
State "NotUpdate" | 0/1000
State "Update" | 999/1000

#### Transition "[Rige]" from Junction #0 to Junction #1

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/CellVoltMin_SignalFilt/ValueIndexCalc/InputValueCalc1.VldValueFilter
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Decisions analyzed
Transition trigger expression | 50%
false | 0/1000
true | 1000/1000

### 496. SubSystem block "MaxMin_CellVolt_Get_Sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get
Child Systems: | MaxMin_CellVolt_ForIterator
Uncovered Links: |
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 2 | 14
Condition | NA | 50% (342/684) condition outcomes
Decision | 50% (1/2) decision outcomes | 70% (14/20) decision outcomes
MCDC | NA | 0% (0/228) conditions reversed the outcome
Execution | NA | 100% (30/30) objective outcomes
Decisions analyzed
enable logical value | 50%
false | 0/1001
true | 1001/1001

#### Logic block "Logical"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/MaxMin_CellVolt_Get_Sys
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (224/448) condition outcomes
MCDC | 0% (0/224) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 1001 | 0
input port1(2) | 1001 | 0
input port1(3) | 1001 | 0
input port1(4) | 1001 | 0
input port1(5) | 1001 | 0
input port1(6) | 1001 | 0
input port1(7) | 1001 | 0
input port1(8) | 1001 | 0
input port1(9) | 1001 | 0
input port1(10) | 1001 | 0
input port1(11) | 1001 | 0
input port1(12) | 1001 | 0
input port1(13) | 1001 | 0
input port1(14) | 1001 | 0
input port1(15) | 1001 | 0
input port1(16) | 1001 | 0
input port1(17) | 1001 | 0
input port1(18) | 1001 | 0
input port1(19) | 1001 | 0
input port1(20) | 1001 | 0
input port1(21) | 1001 | 0
input port1(22) | 1001 | 0
input port1(23) | 1001 | 0
input port1(24) | 1001 | 0
input port1(25) | 1001 | 0
input port1(26) | 1001 | 0
input port1(27) | 1001 | 0
input port1(28) | 1001 | 0
input port1(29) | 1001 | 0
input port1(30) | 1001 | 0
input port1(31) | 1001 | 0
input port1(32) | 1001 | 0
input port1(33) | 1001 | 0
input port1(34) | 1001 | 0
input port1(35) | 1001 | 0
input port1(36) | 1001 | 0
input port1(37) | 1001 | 0
input port1(38) | 1001 | 0
input port1(39) | 1001 | 0
input port1(40) | 1001 | 0
input port1(41) | 1001 | 0
input port1(42) | 1001 | 0
input port1(43) | 1001 | 0
input port1(44) | 1001 | 0
input port1(45) | 1001 | 0
input port1(46) | 1001 | 0
input port1(47) | 1001 | 0
input port1(48) | 1001 | 0
input port1(49) | 1001 | 0
input port1(50) | 1001 | 0
input port1(51) | 1001 | 0
input port1(52) | 1001 | 0
input port1(53) | 1001 | 0
input port1(54) | 1001 | 0
input port1(55) | 1001 | 0
input port1(56) | 1001 | 0
input port1(57) | 1001 | 0
input port1(58) | 1001 | 0
input port1(59) | 1001 | 0
input port1(60) | 1001 | 0
input port1(61) | 1001 | 0
input port1(62) | 1001 | 0
input port1(63) | 1001 | 0
input port1(64) | 1001 | 0
input port1(65) | 1001 | 0
input port1(66) | 1001 | 0
input port1(67) | 1001 | 0
input port1(68) | 1001 | 0
input port1(69) | 1001 | 0
input port1(70) | 1001 | 0
input port1(71) | 1001 | 0
input port1(72) | 1001 | 0
input port1(73) | 1001 | 0
input port1(74) | 1001 | 0
input port1(75) | 1001 | 0
input port1(76) | 1001 | 0
input port1(77) | 1001 | 0
input port1(78) | 1001 | 0
input port1(79) | 1001 | 0
input port1(80) | 1001 | 0
input port1(81) | 1001 | 0
input port1(82) | 1001 | 0
input port1(83) | 1001 | 0
input port1(84) | 1001 | 0
input port1(85) | 1001 | 0
input port1(86) | 1001 | 0
input port1(87) | 1001 | 0
input port1(88) | 1001 | 0
input port1(89) | 1001 | 0
input port1(90) | 1001 | 0
input port1(91) | 1001 | 0
input port1(92) | 1001 | 0
input port1(93) | 1001 | 0
input port1(94) | 1001 | 0
input port1(95) | 1001 | 0
input port1(96) | 1001 | 0
input port1(97) | 1001 | 0
input port1(98) | 1001 | 0
input port1(99) | 1001 | 0
input port1(100) | 1001 | 0
input port1(101) | 1001 | 0
input port1(102) | 1001 | 0
input port1(103) | 1001 | 0
input port1(104) | 1001 | 0
input port1(105) | 1001 | 0
input port1(106) | 1001 | 0
input port1(107) | 1001 | 0
input port1(108) | 1001 | 0
input port1(109) | 1001 | 0
input port1(110) | 1001 | 0
input port1(111) | 1001 | 0
input port1(112) | 1001 | 0
input port2(1) | 1001 | 0
input port2(2) | 1001 | 0
input port2(3) | 1001 | 0
input port2(4) | 1001 | 0
input port2(5) | 1001 | 0
input port2(6) | 1001 | 0
input port2(7) | 1001 | 0
input port2(8) | 1001 | 0
input port2(9) | 1001 | 0
input port2(10) | 1001 | 0
input port2(11) | 1001 | 0
input port2(12) | 1001 | 0
input port2(13) | 1001 | 0
input port2(14) | 1001 | 0
input port2(15) | 1001 | 0
input port2(16) | 1001 | 0
input port2(17) | 1001 | 0
input port2(18) | 1001 | 0
input port2(19) | 1001 | 0
input port2(20) | 1001 | 0
input port2(21) | 1001 | 0
input port2(22) | 1001 | 0
input port2(23) | 1001 | 0
input port2(24) | 1001 | 0
input port2(25) | 1001 | 0
input port2(26) | 1001 | 0
input port2(27) | 1001 | 0
input port2(28) | 1001 | 0
input port2(29) | 1001 | 0
input port2(30) | 1001 | 0
input port2(31) | 1001 | 0
input port2(32) | 1001 | 0
input port2(33) | 1001 | 0
input port2(34) | 1001 | 0
input port2(35) | 1001 | 0
input port2(36) | 1001 | 0
input port2(37) | 1001 | 0
input port2(38) | 1001 | 0
input port2(39) | 1001 | 0
input port2(40) | 1001 | 0
input port2(41) | 1001 | 0
input port2(42) | 1001 | 0
input port2(43) | 1001 | 0
input port2(44) | 1001 | 0
input port2(45) | 1001 | 0
input port2(46) | 1001 | 0
input port2(47) | 1001 | 0
input port2(48) | 1001 | 0
input port2(49) | 1001 | 0
input port2(50) | 1001 | 0
input port2(51) | 1001 | 0
input port2(52) | 1001 | 0
input port2(53) | 1001 | 0
input port2(54) | 1001 | 0
input port2(55) | 1001 | 0
input port2(56) | 1001 | 0
input port2(57) | 1001 | 0
input port2(58) | 1001 | 0
input port2(59) | 1001 | 0
input port2(60) | 1001 | 0
input port2(61) | 1001 | 0
input port2(62) | 1001 | 0
input port2(63) | 1001 | 0
input port2(64) | 1001 | 0
input port2(65) | 1001 | 0
input port2(66) | 1001 | 0
input port2(67) | 1001 | 0
input port2(68) | 1001 | 0
input port2(69) | 1001 | 0
input port2(70) | 1001 | 0
input port2(71) | 1001 | 0
input port2(72) | 1001 | 0
input port2(73) | 1001 | 0
input port2(74) | 1001 | 0
input port2(75) | 1001 | 0
input port2(76) | 1001 | 0
input port2(77) | 1001 | 0
input port2(78) | 1001 | 0
input port2(79) | 1001 | 0
input port2(80) | 1001 | 0
input port2(81) | 1001 | 0
input port2(82) | 1001 | 0
input port2(83) | 1001 | 0
input port2(84) | 1001 | 0
input port2(85) | 1001 | 0
input port2(86) | 1001 | 0
input port2(87) | 1001 | 0
input port2(88) | 1001 | 0
input port2(89) | 1001 | 0
input port2(90) | 1001 | 0
input port2(91) | 1001 | 0
input port2(92) | 1001 | 0
input port2(93) | 1001 | 0
input port2(94) | 1001 | 0
input port2(95) | 1001 | 0
input port2(96) | 1001 | 0
input port2(97) | 1001 | 0
input port2(98) | 1001 | 0
input port2(99) | 1001 | 0
input port2(100) | 1001 | 0
input port2(101) | 1001 | 0
input port2(102) | 1001 | 0
input port2(103) | 1001 | 0
input port2(104) | 1001 | 0
input port2(105) | 1001 | 0
input port2(106) | 1001 | 0
input port2(107) | 1001 | 0
input port2(108) | 1001 | 0
input port2(109) | 1001 | 0
input port2(110) | 1001 | 0
input port2(111) | 1001 | 0
input port2(112) | 1001 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output(1) |
input port1(1) | TT | (FT)
input port2(1) | TT | (TF)
expression for output(2) |
input port1(2) | TT | (FT)
input port2(2) | TT | (TF)
expression for output(3) |
input port1(3) | TT | (FT)
input port2(3) | TT | (TF)
expression for output(4) |
input port1(4) | TT | (FT)
input port2(4) | TT | (TF)
expression for output(5) |
input port1(5) | TT | (FT)
input port2(5) | TT | (TF)
expression for output(6) |
input port1(6) | TT | (FT)
input port2(6) | TT | (TF)
expression for output(7) |
input port1(7) | TT | (FT)
input port2(7) | TT | (TF)
expression for output(8) |
input port1(8) | TT | (FT)
input port2(8) | TT | (TF)
expression for output(9) |
input port1(9) | TT | (FT)
input port2(9) | TT | (TF)
expression for output(10) |
input port1(10) | TT | (FT)
input port2(10) | TT | (TF)
expression for output(11) |
input port1(11) | TT | (FT)
input port2(11) | TT | (TF)
expression for output(12) |
input port1(12) | TT | (FT)
input port2(12) | TT | (TF)
expression for output(13) |
input port1(13) | TT | (FT)
input port2(13) | TT | (TF)
expression for output(14) |
input port1(14) | TT | (FT)
input port2(14) | TT | (TF)
expression for output(15) |
input port1(15) | TT | (FT)
input port2(15) | TT | (TF)
expression for output(16) |
input port1(16) | TT | (FT)
input port2(16) | TT | (TF)
expression for output(17) |
input port1(17) | TT | (FT)
input port2(17) | TT | (TF)
expression for output(18) |
input port1(18) | TT | (FT)
input port2(18) | TT | (TF)
expression for output(19) |
input port1(19) | TT | (FT)
input port2(19) | TT | (TF)
expression for output(20) |
input port1(20) | TT | (FT)
input port2(20) | TT | (TF)
expression for output(21) |
input port1(21) | TT | (FT)
input port2(21) | TT | (TF)
expression for output(22) |
input port1(22) | TT | (FT)
input port2(22) | TT | (TF)
expression for output(23) |
input port1(23) | TT | (FT)
input port2(23) | TT | (TF)
expression for output(24) |
input port1(24) | TT | (FT)
input port2(24) | TT | (TF)
expression for output(25) |
input port1(25) | TT | (FT)
input port2(25) | TT | (TF)
expression for output(26) |
input port1(26) | TT | (FT)
input port2(26) | TT | (TF)
expression for output(27) |
input port1(27) | TT | (FT)
input port2(27) | TT | (TF)
expression for output(28) |
input port1(28) | TT | (FT)
input port2(28) | TT | (TF)
expression for output(29) |
input port1(29) | TT | (FT)
input port2(29) | TT | (TF)
expression for output(30) |
input port1(30) | TT | (FT)
input port2(30) | TT | (TF)
expression for output(31) |
input port1(31) | TT | (FT)
input port2(31) | TT | (TF)
expression for output(32) |
input port1(32) | TT | (FT)
input port2(32) | TT | (TF)
expression for output(33) |
input port1(33) | TT | (FT)
input port2(33) | TT | (TF)
expression for output(34) |
input port1(34) | TT | (FT)
input port2(34) | TT | (TF)
expression for output(35) |
input port1(35) | TT | (FT)
input port2(35) | TT | (TF)
expression for output(36) |
input port1(36) | TT | (FT)
input port2(36) | TT | (TF)
expression for output(37) |
input port1(37) | TT | (FT)
input port2(37) | TT | (TF)
expression for output(38) |
input port1(38) | TT | (FT)
input port2(38) | TT | (TF)
expression for output(39) |
input port1(39) | TT | (FT)
input port2(39) | TT | (TF)
expression for output(40) |
input port1(40) | TT | (FT)
input port2(40) | TT | (TF)
expression for output(41) |
input port1(41) | TT | (FT)
input port2(41) | TT | (TF)
expression for output(42) |
input port1(42) | TT | (FT)
input port2(42) | TT | (TF)
expression for output(43) |
input port1(43) | TT | (FT)
input port2(43) | TT | (TF)
expression for output(44) |
input port1(44) | TT | (FT)
input port2(44) | TT | (TF)
expression for output(45) |
input port1(45) | TT | (FT)
input port2(45) | TT | (TF)
expression for output(46) |
input port1(46) | TT | (FT)
input port2(46) | TT | (TF)
expression for output(47) |
input port1(47) | TT | (FT)
input port2(47) | TT | (TF)
expression for output(48) |
input port1(48) | TT | (FT)
input port2(48) | TT | (TF)
expression for output(49) |
input port1(49) | TT | (FT)
input port2(49) | TT | (TF)
expression for output(50) |
input port1(50) | TT | (FT)
input port2(50) | TT | (TF)
expression for output(51) |
input port1(51) | TT | (FT)
input port2(51) | TT | (TF)
expression for output(52) |
input port1(52) | TT | (FT)
input port2(52) | TT | (TF)
expression for output(53) |
input port1(53) | TT | (FT)
input port2(53) | TT | (TF)
expression for output(54) |
input port1(54) | TT | (FT)
input port2(54) | TT | (TF)
expression for output(55) |
input port1(55) | TT | (FT)
input port2(55) | TT | (TF)
expression for output(56) |
input port1(56) | TT | (FT)
input port2(56) | TT | (TF)
expression for output(57) |
input port1(57) | TT | (FT)
input port2(57) | TT | (TF)
expression for output(58) |
input port1(58) | TT | (FT)
input port2(58) | TT | (TF)
expression for output(59) |
input port1(59) | TT | (FT)
input port2(59) | TT | (TF)
expression for output(60) |
input port1(60) | TT | (FT)
input port2(60) | TT | (TF)
expression for output(61) |
input port1(61) | TT | (FT)
input port2(61) | TT | (TF)
expression for output(62) |
input port1(62) | TT | (FT)
input port2(62) | TT | (TF)
expression for output(63) |
input port1(63) | TT | (FT)
input port2(63) | TT | (TF)
expression for output(64) |
input port1(64) | TT | (FT)
input port2(64) | TT | (TF)
expression for output(65) |
input port1(65) | TT | (FT)
input port2(65) | TT | (TF)
expression for output(66) |
input port1(66) | TT | (FT)
input port2(66) | TT | (TF)
expression for output(67) |
input port1(67) | TT | (FT)
input port2(67) | TT | (TF)
expression for output(68) |
input port1(68) | TT | (FT)
input port2(68) | TT | (TF)
expression for output(69) |
input port1(69) | TT | (FT)
input port2(69) | TT | (TF)
expression for output(70) |
input port1(70) | TT | (FT)
input port2(70) | TT | (TF)
expression for output(71) |
input port1(71) | TT | (FT)
input port2(71) | TT | (TF)
expression for output(72) |
input port1(72) | TT | (FT)
input port2(72) | TT | (TF)
expression for output(73) |
input port1(73) | TT | (FT)
input port2(73) | TT | (TF)
expression for output(74) |
input port1(74) | TT | (FT)
input port2(74) | TT | (TF)
expression for output(75) |
input port1(75) | TT | (FT)
input port2(75) | TT | (TF)
expression for output(76) |
input port1(76) | TT | (FT)
input port2(76) | TT | (TF)
expression for output(77) |
input port1(77) | TT | (FT)
input port2(77) | TT | (TF)
expression for output(78) |
input port1(78) | TT | (FT)
input port2(78) | TT | (TF)
expression for output(79) |
input port1(79) | TT | (FT)
input port2(79) | TT | (TF)
expression for output(80) |
input port1(80) | TT | (FT)
input port2(80) | TT | (TF)
expression for output(81) |
input port1(81) | TT | (FT)
input port2(81) | TT | (TF)
expression for output(82) |
input port1(82) | TT | (FT)
input port2(82) | TT | (TF)
expression for output(83) |
input port1(83) | TT | (FT)
input port2(83) | TT | (TF)
expression for output(84) |
input port1(84) | TT | (FT)
input port2(84) | TT | (TF)
expression for output(85) |
input port1(85) | TT | (FT)
input port2(85) | TT | (TF)
expression for output(86) |
input port1(86) | TT | (FT)
input port2(86) | TT | (TF)
expression for output(87) |
input port1(87) | TT | (FT)
input port2(87) | TT | (TF)
expression for output(88) |
input port1(88) | TT | (FT)
input port2(88) | TT | (TF)
expression for output(89) |
input port1(89) | TT | (FT)
input port2(89) | TT | (TF)
expression for output(90) |
input port1(90) | TT | (FT)
input port2(90) | TT | (TF)
expression for output(91) |
input port1(91) | TT | (FT)
input port2(91) | TT | (TF)
expression for output(92) |
input port1(92) | TT | (FT)
input port2(92) | TT | (TF)
expression for output(93) |
input port1(93) | TT | (FT)
input port2(93) | TT | (TF)
expression for output(94) |
input port1(94) | TT | (FT)
input port2(94) | TT | (TF)
expression for output(95) |
input port1(95) | TT | (FT)
input port2(95) | TT | (TF)
expression for output(96) |
input port1(96) | TT | (FT)
input port2(96) | TT | (TF)
expression for output(97) |
input port1(97) | TT | (FT)
input port2(97) | TT | (TF)
expression for output(98) |
input port1(98) | TT | (FT)
input port2(98) | TT | (TF)
expression for output(99) |
input port1(99) | TT | (FT)
input port2(99) | TT | (TF)
expression for output(100) |
input port1(100) | TT | (FT)
input port2(100) | TT | (TF)
expression for output(101) |
input port1(101) | TT | (FT)
input port2(101) | TT | (TF)
expression for output(102) |
input port1(102) | TT | (FT)
input port2(102) | TT | (TF)
expression for output(103) |
input port1(103) | TT | (FT)
input port2(103) | TT | (TF)
expression for output(104) |
input port1(104) | TT | (FT)
input port2(104) | TT | (TF)
expression for output(105) |
input port1(105) | TT | (FT)
input port2(105) | TT | (TF)
expression for output(106) |
input port1(106) | TT | (FT)
input port2(106) | TT | (TF)
expression for output(107) |
input port1(107) | TT | (FT)
input port2(107) | TT | (TF)
expression for output(108) |
input port1(108) | TT | (FT)
input port2(108) | TT | (TF)
expression for output(109) |
input port1(109) | TT | (FT)
input port2(109) | TT | (TF)
expression for output(110) |
input port1(110) | TT | (FT)
input port2(110) | TT | (TF)
expression for output(111) |
input port1(111) | TT | (FT)
input port2(111) | TT | (TF)
expression for output(112) |
input port1(112) | TT | (FT)
input port2(112) | TT | (TF)

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/MaxMin_CellVolt_Get_Sys
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### RelationalOperator block "Comparison4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/MaxMin_CellVolt_Get_Sys
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (112/224) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) == input2 | 1001 | 0
input1(2) == input2 | 1001 | 0
input1(3) == input2 | 1001 | 0
input1(4) == input2 | 1001 | 0
input1(5) == input2 | 1001 | 0
input1(6) == input2 | 1001 | 0
input1(7) == input2 | 1001 | 0
input1(8) == input2 | 1001 | 0
input1(9) == input2 | 1001 | 0
input1(10) == input2 | 1001 | 0
input1(11) == input2 | 1001 | 0
input1(12) == input2 | 1001 | 0
input1(13) == input2 | 1001 | 0
input1(14) == input2 | 1001 | 0
input1(15) == input2 | 1001 | 0
input1(16) == input2 | 1001 | 0
input1(17) == input2 | 1001 | 0
input1(18) == input2 | 1001 | 0
input1(19) == input2 | 1001 | 0
input1(20) == input2 | 1001 | 0
input1(21) == input2 | 1001 | 0
input1(22) == input2 | 1001 | 0
input1(23) == input2 | 1001 | 0
input1(24) == input2 | 1001 | 0
input1(25) == input2 | 1001 | 0
input1(26) == input2 | 1001 | 0
input1(27) == input2 | 1001 | 0
input1(28) == input2 | 1001 | 0
input1(29) == input2 | 1001 | 0
input1(30) == input2 | 1001 | 0
input1(31) == input2 | 1001 | 0
input1(32) == input2 | 1001 | 0
input1(33) == input2 | 1001 | 0
input1(34) == input2 | 1001 | 0
input1(35) == input2 | 1001 | 0
input1(36) == input2 | 1001 | 0
input1(37) == input2 | 1001 | 0
input1(38) == input2 | 1001 | 0
input1(39) == input2 | 1001 | 0
input1(40) == input2 | 1001 | 0
input1(41) == input2 | 1001 | 0
input1(42) == input2 | 1001 | 0
input1(43) == input2 | 1001 | 0
input1(44) == input2 | 1001 | 0
input1(45) == input2 | 1001 | 0
input1(46) == input2 | 1001 | 0
input1(47) == input2 | 1001 | 0
input1(48) == input2 | 1001 | 0
input1(49) == input2 | 1001 | 0
input1(50) == input2 | 1001 | 0
input1(51) == input2 | 1001 | 0
input1(52) == input2 | 1001 | 0
input1(53) == input2 | 1001 | 0
input1(54) == input2 | 1001 | 0
input1(55) == input2 | 1001 | 0
input1(56) == input2 | 1001 | 0
input1(57) == input2 | 1001 | 0
input1(58) == input2 | 1001 | 0
input1(59) == input2 | 1001 | 0
input1(60) == input2 | 1001 | 0
input1(61) == input2 | 1001 | 0
input1(62) == input2 | 1001 | 0
input1(63) == input2 | 1001 | 0
input1(64) == input2 | 1001 | 0
input1(65) == input2 | 1001 | 0
input1(66) == input2 | 1001 | 0
input1(67) == input2 | 1001 | 0
input1(68) == input2 | 1001 | 0
input1(69) == input2 | 1001 | 0
input1(70) == input2 | 1001 | 0
input1(71) == input2 | 1001 | 0
input1(72) == input2 | 1001 | 0
input1(73) == input2 | 1001 | 0
input1(74) == input2 | 1001 | 0
input1(75) == input2 | 1001 | 0
input1(76) == input2 | 1001 | 0
input1(77) == input2 | 1001 | 0
input1(78) == input2 | 1001 | 0
input1(79) == input2 | 1001 | 0
input1(80) == input2 | 1001 | 0
input1(81) == input2 | 1001 | 0
input1(82) == input2 | 1001 | 0
input1(83) == input2 | 1001 | 0
input1(84) == input2 | 1001 | 0
input1(85) == input2 | 1001 | 0
input1(86) == input2 | 1001 | 0
input1(87) == input2 | 1001 | 0
input1(88) == input2 | 1001 | 0
input1(89) == input2 | 1001 | 0
input1(90) == input2 | 1001 | 0
input1(91) == input2 | 1001 | 0
input1(92) == input2 | 1001 | 0
input1(93) == input2 | 1001 | 0
input1(94) == input2 | 1001 | 0
input1(95) == input2 | 1001 | 0
input1(96) == input2 | 1001 | 0
input1(97) == input2 | 1001 | 0
input1(98) == input2 | 1001 | 0
input1(99) == input2 | 1001 | 0
input1(100) == input2 | 1001 | 0
input1(101) == input2 | 1001 | 0
input1(102) == input2 | 1001 | 0
input1(103) == input2 | 1001 | 0
input1(104) == input2 | 1001 | 0
input1(105) == input2 | 1001 | 0
input1(106) == input2 | 1001 | 0
input1(107) == input2 | 1001 | 0
input1(108) == input2 | 1001 | 0
input1(109) == input2 | 1001 | 0
input1(110) == input2 | 1001 | 0
input1(111) == input2 | 1001 | 0
input1(112) == input2 | 1001 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution

### 497. SubSystem block "MaxMin_CellVolt_ForIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/MaxMin_CellVolt_Get_Sys
Child Systems: | MaxCellVoltNumb_ForIterator, MinCellVoltNumb_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 11
Condition | NA | 50% (6/12) condition outcomes
Decision | NA | 75% (12/16) decision outcomes
MCDC | NA | 0% (0/4) conditions reversed the outcome
Execution | NA | 100% (24/24) objective outcomes

#### Full Coverage

Model Object | Metric
ForIterator block "MaxCellVoltNumbIterator" | Decision
DataTypeConversion block "Data Type Conversion" | Execution
Selector block "Selector" | Execution
Selector block "Selector1" | Execution

### 498. SubSystem block "MaxCellVoltNumb_ForIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/MaxMin_CellVolt_Get_Sys/MaxMin_CellVolt_ForIterator
Child Systems: | Unit Delay External IC1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 4
Condition | NA | 50% (3/6) condition outcomes
Decision | NA | 67% (4/6) decision outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 100% (9/9) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/MaxMin_CellVolt_Get_Sys/MaxMin_CellVolt_ForIterator/MaxCellVoltNumb_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 96096 | 0
input port 2 | 96096 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | TT | (FT)
input port 2 | TT | (TF)

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/MaxMin_CellVolt_Get_Sys/MaxMin_CellVolt_ForIterator/MaxCellVoltNumb_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 0/96096
true (output is from 1st input port) | 96096/96096

#### Switch block "Switch1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/MaxMin_CellVolt_Get_Sys/MaxMin_CellVolt_ForIterator/MaxCellVoltNumb_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 0/96096
true (output is from 1st input port) | 96096/96096

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/MaxMin_CellVolt_Get_Sys/MaxMin_CellVolt_ForIterator/MaxCellVoltNumb_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 <= input2 | 96096 | 0

#### Full Coverage

Model Object | Metric
UnitDelay block "Unit Delay" | Execution
UnitDelay block "Unit Delay1" | Execution

### 499. SubSystem block "Unit Delay External IC1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/MaxMin_CellVolt_Get_Sys/MaxMin_CellVolt_ForIterator/MaxCellVoltNumb_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 100% (2/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Full Coverage

Model Object | Metric
Switch block "Init" | Decision, Execution
UnitDelay block "Unit Delay" | Execution
UnitDelay block "Unit Delay1" | Execution

### 500. SubSystem block "MinCellVoltNumb_ForIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/MaxMin_CellVolt_Get_Sys/MaxMin_CellVolt_ForIterator
Child Systems: | Unit Delay External IC1, Unit Delay External IC2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 6
Condition | NA | 50% (3/6) condition outcomes
Decision | NA | 75% (6/8) decision outcomes
MCDC | NA | 0% (0/2) conditions reversed the outcome
Execution | NA | 100% (12/12) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/MaxMin_CellVolt_Get_Sys/MaxMin_CellVolt_ForIterator/MinCellVoltNumb_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 96096 | 0
input port 2 | 96096 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | TT | (FT)
input port 2 | TT | (TF)

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/MaxMin_CellVolt_Get_Sys/MaxMin_CellVolt_ForIterator/MinCellVoltNumb_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 0/96096
true (output is from 1st input port) | 96096/96096

#### Switch block "Switch1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/MaxMin_CellVolt_Get_Sys/MaxMin_CellVolt_ForIterator/MinCellVoltNumb_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 0/96096
true (output is from 1st input port) | 96096/96096

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/MaxMin_CellVolt_Get_Sys/MaxMin_CellVolt_ForIterator/MinCellVoltNumb_ForIterator
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 >= input2 | 96096 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant3" | Execution
UnitDelay block "Unit Delay1" | Execution

### 501. SubSystem block "Unit Delay External IC1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/MaxMin_CellVolt_Get_Sys/MaxMin_CellVolt_ForIterator/MinCellVoltNumb_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 100% (2/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Full Coverage

Model Object | Metric
Switch block "Init" | Decision, Execution
UnitDelay block "Unit Delay" | Execution
UnitDelay block "Unit Delay1" | Execution

### 502. SubSystem block "Unit Delay External IC2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/MaxMin_CellVolt_Get_Sys/MaxMin_CellVolt_ForIterator/MinCellVoltNumb_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 100% (2/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Full Coverage

Model Object | Metric
Switch block "Init" | Decision, Execution
UnitDelay block "Unit Delay" | Execution
UnitDelay block "Unit Delay1" | Execution

### 503. SubSystem block "OverWrite"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/OverWrite
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 504. SubSystem block "OverWrite1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/OverWrite1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 505. SubSystem block "OverWrite2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/OverWrite2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 506. SubSystem block "OverWrite3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/OverWrite3
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 507. SubSystem block "SumCellVoltVld"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get
Child Systems: | CellVoltVld, OverWrite
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 4
Condition | NA | 50% (343/682) condition outcomes
Decision | NA | 67% (4/6) decision outcomes
MCDC | NA | 0% (0/228) conditions reversed the outcome
Execution | NA | 100% (19/19) objective outcomes

#### Logic block "Logical"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/SumCellVoltVld
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (224/448) condition outcomes
MCDC | 0% (0/224) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 1001 | 0
input port1(2) | 1001 | 0
input port1(3) | 1001 | 0
input port1(4) | 1001 | 0
input port1(5) | 1001 | 0
input port1(6) | 1001 | 0
input port1(7) | 1001 | 0
input port1(8) | 1001 | 0
input port1(9) | 1001 | 0
input port1(10) | 1001 | 0
input port1(11) | 1001 | 0
input port1(12) | 1001 | 0
input port1(13) | 1001 | 0
input port1(14) | 1001 | 0
input port1(15) | 1001 | 0
input port1(16) | 1001 | 0
input port1(17) | 1001 | 0
input port1(18) | 1001 | 0
input port1(19) | 1001 | 0
input port1(20) | 1001 | 0
input port1(21) | 1001 | 0
input port1(22) | 1001 | 0
input port1(23) | 1001 | 0
input port1(24) | 1001 | 0
input port1(25) | 1001 | 0
input port1(26) | 1001 | 0
input port1(27) | 1001 | 0
input port1(28) | 1001 | 0
input port1(29) | 1001 | 0
input port1(30) | 1001 | 0
input port1(31) | 1001 | 0
input port1(32) | 1001 | 0
input port1(33) | 1001 | 0
input port1(34) | 1001 | 0
input port1(35) | 1001 | 0
input port1(36) | 1001 | 0
input port1(37) | 1001 | 0
input port1(38) | 1001 | 0
input port1(39) | 1001 | 0
input port1(40) | 1001 | 0
input port1(41) | 1001 | 0
input port1(42) | 1001 | 0
input port1(43) | 1001 | 0
input port1(44) | 1001 | 0
input port1(45) | 1001 | 0
input port1(46) | 1001 | 0
input port1(47) | 1001 | 0
input port1(48) | 1001 | 0
input port1(49) | 1001 | 0
input port1(50) | 1001 | 0
input port1(51) | 1001 | 0
input port1(52) | 1001 | 0
input port1(53) | 1001 | 0
input port1(54) | 1001 | 0
input port1(55) | 1001 | 0
input port1(56) | 1001 | 0
input port1(57) | 1001 | 0
input port1(58) | 1001 | 0
input port1(59) | 1001 | 0
input port1(60) | 1001 | 0
input port1(61) | 1001 | 0
input port1(62) | 1001 | 0
input port1(63) | 1001 | 0
input port1(64) | 1001 | 0
input port1(65) | 1001 | 0
input port1(66) | 1001 | 0
input port1(67) | 1001 | 0
input port1(68) | 1001 | 0
input port1(69) | 1001 | 0
input port1(70) | 1001 | 0
input port1(71) | 1001 | 0
input port1(72) | 1001 | 0
input port1(73) | 1001 | 0
input port1(74) | 1001 | 0
input port1(75) | 1001 | 0
input port1(76) | 1001 | 0
input port1(77) | 1001 | 0
input port1(78) | 1001 | 0
input port1(79) | 1001 | 0
input port1(80) | 1001 | 0
input port1(81) | 1001 | 0
input port1(82) | 1001 | 0
input port1(83) | 1001 | 0
input port1(84) | 1001 | 0
input port1(85) | 1001 | 0
input port1(86) | 1001 | 0
input port1(87) | 1001 | 0
input port1(88) | 1001 | 0
input port1(89) | 1001 | 0
input port1(90) | 1001 | 0
input port1(91) | 1001 | 0
input port1(92) | 1001 | 0
input port1(93) | 1001 | 0
input port1(94) | 1001 | 0
input port1(95) | 1001 | 0
input port1(96) | 1001 | 0
input port1(97) | 1001 | 0
input port1(98) | 1001 | 0
input port1(99) | 1001 | 0
input port1(100) | 1001 | 0
input port1(101) | 1001 | 0
input port1(102) | 1001 | 0
input port1(103) | 1001 | 0
input port1(104) | 1001 | 0
input port1(105) | 1001 | 0
input port1(106) | 1001 | 0
input port1(107) | 1001 | 0
input port1(108) | 1001 | 0
input port1(109) | 1001 | 0
input port1(110) | 1001 | 0
input port1(111) | 1001 | 0
input port1(112) | 1001 | 0
input port2(1) | 1001 | 0
input port2(2) | 1001 | 0
input port2(3) | 1001 | 0
input port2(4) | 1001 | 0
input port2(5) | 1001 | 0
input port2(6) | 1001 | 0
input port2(7) | 1001 | 0
input port2(8) | 1001 | 0
input port2(9) | 1001 | 0
input port2(10) | 1001 | 0
input port2(11) | 1001 | 0
input port2(12) | 1001 | 0
input port2(13) | 1001 | 0
input port2(14) | 1001 | 0
input port2(15) | 1001 | 0
input port2(16) | 1001 | 0
input port2(17) | 1001 | 0
input port2(18) | 1001 | 0
input port2(19) | 1001 | 0
input port2(20) | 1001 | 0
input port2(21) | 1001 | 0
input port2(22) | 1001 | 0
input port2(23) | 1001 | 0
input port2(24) | 1001 | 0
input port2(25) | 1001 | 0
input port2(26) | 1001 | 0
input port2(27) | 1001 | 0
input port2(28) | 1001 | 0
input port2(29) | 1001 | 0
input port2(30) | 1001 | 0
input port2(31) | 1001 | 0
input port2(32) | 1001 | 0
input port2(33) | 1001 | 0
input port2(34) | 1001 | 0
input port2(35) | 1001 | 0
input port2(36) | 1001 | 0
input port2(37) | 1001 | 0
input port2(38) | 1001 | 0
input port2(39) | 1001 | 0
input port2(40) | 1001 | 0
input port2(41) | 1001 | 0
input port2(42) | 1001 | 0
input port2(43) | 1001 | 0
input port2(44) | 1001 | 0
input port2(45) | 1001 | 0
input port2(46) | 1001 | 0
input port2(47) | 1001 | 0
input port2(48) | 1001 | 0
input port2(49) | 1001 | 0
input port2(50) | 1001 | 0
input port2(51) | 1001 | 0
input port2(52) | 1001 | 0
input port2(53) | 1001 | 0
input port2(54) | 1001 | 0
input port2(55) | 1001 | 0
input port2(56) | 1001 | 0
input port2(57) | 1001 | 0
input port2(58) | 1001 | 0
input port2(59) | 1001 | 0
input port2(60) | 1001 | 0
input port2(61) | 1001 | 0
input port2(62) | 1001 | 0
input port2(63) | 1001 | 0
input port2(64) | 1001 | 0
input port2(65) | 1001 | 0
input port2(66) | 1001 | 0
input port2(67) | 1001 | 0
input port2(68) | 1001 | 0
input port2(69) | 1001 | 0
input port2(70) | 1001 | 0
input port2(71) | 1001 | 0
input port2(72) | 1001 | 0
input port2(73) | 1001 | 0
input port2(74) | 1001 | 0
input port2(75) | 1001 | 0
input port2(76) | 1001 | 0
input port2(77) | 1001 | 0
input port2(78) | 1001 | 0
input port2(79) | 1001 | 0
input port2(80) | 1001 | 0
input port2(81) | 1001 | 0
input port2(82) | 1001 | 0
input port2(83) | 1001 | 0
input port2(84) | 1001 | 0
input port2(85) | 1001 | 0
input port2(86) | 1001 | 0
input port2(87) | 1001 | 0
input port2(88) | 1001 | 0
input port2(89) | 1001 | 0
input port2(90) | 1001 | 0
input port2(91) | 1001 | 0
input port2(92) | 1001 | 0
input port2(93) | 1001 | 0
input port2(94) | 1001 | 0
input port2(95) | 1001 | 0
input port2(96) | 1001 | 0
input port2(97) | 1001 | 0
input port2(98) | 1001 | 0
input port2(99) | 1001 | 0
input port2(100) | 1001 | 0
input port2(101) | 1001 | 0
input port2(102) | 1001 | 0
input port2(103) | 1001 | 0
input port2(104) | 1001 | 0
input port2(105) | 1001 | 0
input port2(106) | 1001 | 0
input port2(107) | 1001 | 0
input port2(108) | 1001 | 0
input port2(109) | 1001 | 0
input port2(110) | 1001 | 0
input port2(111) | 1001 | 0
input port2(112) | 1001 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output(1) |
input port1(1) | TT | (FT)
input port2(1) | TT | (TF)
expression for output(2) |
input port1(2) | TT | (FT)
input port2(2) | TT | (TF)
expression for output(3) |
input port1(3) | TT | (FT)
input port2(3) | TT | (TF)
expression for output(4) |
input port1(4) | TT | (FT)
input port2(4) | TT | (TF)
expression for output(5) |
input port1(5) | TT | (FT)
input port2(5) | TT | (TF)
expression for output(6) |
input port1(6) | TT | (FT)
input port2(6) | TT | (TF)
expression for output(7) |
input port1(7) | TT | (FT)
input port2(7) | TT | (TF)
expression for output(8) |
input port1(8) | TT | (FT)
input port2(8) | TT | (TF)
expression for output(9) |
input port1(9) | TT | (FT)
input port2(9) | TT | (TF)
expression for output(10) |
input port1(10) | TT | (FT)
input port2(10) | TT | (TF)
expression for output(11) |
input port1(11) | TT | (FT)
input port2(11) | TT | (TF)
expression for output(12) |
input port1(12) | TT | (FT)
input port2(12) | TT | (TF)
expression for output(13) |
input port1(13) | TT | (FT)
input port2(13) | TT | (TF)
expression for output(14) |
input port1(14) | TT | (FT)
input port2(14) | TT | (TF)
expression for output(15) |
input port1(15) | TT | (FT)
input port2(15) | TT | (TF)
expression for output(16) |
input port1(16) | TT | (FT)
input port2(16) | TT | (TF)
expression for output(17) |
input port1(17) | TT | (FT)
input port2(17) | TT | (TF)
expression for output(18) |
input port1(18) | TT | (FT)
input port2(18) | TT | (TF)
expression for output(19) |
input port1(19) | TT | (FT)
input port2(19) | TT | (TF)
expression for output(20) |
input port1(20) | TT | (FT)
input port2(20) | TT | (TF)
expression for output(21) |
input port1(21) | TT | (FT)
input port2(21) | TT | (TF)
expression for output(22) |
input port1(22) | TT | (FT)
input port2(22) | TT | (TF)
expression for output(23) |
input port1(23) | TT | (FT)
input port2(23) | TT | (TF)
expression for output(24) |
input port1(24) | TT | (FT)
input port2(24) | TT | (TF)
expression for output(25) |
input port1(25) | TT | (FT)
input port2(25) | TT | (TF)
expression for output(26) |
input port1(26) | TT | (FT)
input port2(26) | TT | (TF)
expression for output(27) |
input port1(27) | TT | (FT)
input port2(27) | TT | (TF)
expression for output(28) |
input port1(28) | TT | (FT)
input port2(28) | TT | (TF)
expression for output(29) |
input port1(29) | TT | (FT)
input port2(29) | TT | (TF)
expression for output(30) |
input port1(30) | TT | (FT)
input port2(30) | TT | (TF)
expression for output(31) |
input port1(31) | TT | (FT)
input port2(31) | TT | (TF)
expression for output(32) |
input port1(32) | TT | (FT)
input port2(32) | TT | (TF)
expression for output(33) |
input port1(33) | TT | (FT)
input port2(33) | TT | (TF)
expression for output(34) |
input port1(34) | TT | (FT)
input port2(34) | TT | (TF)
expression for output(35) |
input port1(35) | TT | (FT)
input port2(35) | TT | (TF)
expression for output(36) |
input port1(36) | TT | (FT)
input port2(36) | TT | (TF)
expression for output(37) |
input port1(37) | TT | (FT)
input port2(37) | TT | (TF)
expression for output(38) |
input port1(38) | TT | (FT)
input port2(38) | TT | (TF)
expression for output(39) |
input port1(39) | TT | (FT)
input port2(39) | TT | (TF)
expression for output(40) |
input port1(40) | TT | (FT)
input port2(40) | TT | (TF)
expression for output(41) |
input port1(41) | TT | (FT)
input port2(41) | TT | (TF)
expression for output(42) |
input port1(42) | TT | (FT)
input port2(42) | TT | (TF)
expression for output(43) |
input port1(43) | TT | (FT)
input port2(43) | TT | (TF)
expression for output(44) |
input port1(44) | TT | (FT)
input port2(44) | TT | (TF)
expression for output(45) |
input port1(45) | TT | (FT)
input port2(45) | TT | (TF)
expression for output(46) |
input port1(46) | TT | (FT)
input port2(46) | TT | (TF)
expression for output(47) |
input port1(47) | TT | (FT)
input port2(47) | TT | (TF)
expression for output(48) |
input port1(48) | TT | (FT)
input port2(48) | TT | (TF)
expression for output(49) |
input port1(49) | TT | (FT)
input port2(49) | TT | (TF)
expression for output(50) |
input port1(50) | TT | (FT)
input port2(50) | TT | (TF)
expression for output(51) |
input port1(51) | TT | (FT)
input port2(51) | TT | (TF)
expression for output(52) |
input port1(52) | TT | (FT)
input port2(52) | TT | (TF)
expression for output(53) |
input port1(53) | TT | (FT)
input port2(53) | TT | (TF)
expression for output(54) |
input port1(54) | TT | (FT)
input port2(54) | TT | (TF)
expression for output(55) |
input port1(55) | TT | (FT)
input port2(55) | TT | (TF)
expression for output(56) |
input port1(56) | TT | (FT)
input port2(56) | TT | (TF)
expression for output(57) |
input port1(57) | TT | (FT)
input port2(57) | TT | (TF)
expression for output(58) |
input port1(58) | TT | (FT)
input port2(58) | TT | (TF)
expression for output(59) |
input port1(59) | TT | (FT)
input port2(59) | TT | (TF)
expression for output(60) |
input port1(60) | TT | (FT)
input port2(60) | TT | (TF)
expression for output(61) |
input port1(61) | TT | (FT)
input port2(61) | TT | (TF)
expression for output(62) |
input port1(62) | TT | (FT)
input port2(62) | TT | (TF)
expression for output(63) |
input port1(63) | TT | (FT)
input port2(63) | TT | (TF)
expression for output(64) |
input port1(64) | TT | (FT)
input port2(64) | TT | (TF)
expression for output(65) |
input port1(65) | TT | (FT)
input port2(65) | TT | (TF)
expression for output(66) |
input port1(66) | TT | (FT)
input port2(66) | TT | (TF)
expression for output(67) |
input port1(67) | TT | (FT)
input port2(67) | TT | (TF)
expression for output(68) |
input port1(68) | TT | (FT)
input port2(68) | TT | (TF)
expression for output(69) |
input port1(69) | TT | (FT)
input port2(69) | TT | (TF)
expression for output(70) |
input port1(70) | TT | (FT)
input port2(70) | TT | (TF)
expression for output(71) |
input port1(71) | TT | (FT)
input port2(71) | TT | (TF)
expression for output(72) |
input port1(72) | TT | (FT)
input port2(72) | TT | (TF)
expression for output(73) |
input port1(73) | TT | (FT)
input port2(73) | TT | (TF)
expression for output(74) |
input port1(74) | TT | (FT)
input port2(74) | TT | (TF)
expression for output(75) |
input port1(75) | TT | (FT)
input port2(75) | TT | (TF)
expression for output(76) |
input port1(76) | TT | (FT)
input port2(76) | TT | (TF)
expression for output(77) |
input port1(77) | TT | (FT)
input port2(77) | TT | (TF)
expression for output(78) |
input port1(78) | TT | (FT)
input port2(78) | TT | (TF)
expression for output(79) |
input port1(79) | TT | (FT)
input port2(79) | TT | (TF)
expression for output(80) |
input port1(80) | TT | (FT)
input port2(80) | TT | (TF)
expression for output(81) |
input port1(81) | TT | (FT)
input port2(81) | TT | (TF)
expression for output(82) |
input port1(82) | TT | (FT)
input port2(82) | TT | (TF)
expression for output(83) |
input port1(83) | TT | (FT)
input port2(83) | TT | (TF)
expression for output(84) |
input port1(84) | TT | (FT)
input port2(84) | TT | (TF)
expression for output(85) |
input port1(85) | TT | (FT)
input port2(85) | TT | (TF)
expression for output(86) |
input port1(86) | TT | (FT)
input port2(86) | TT | (TF)
expression for output(87) |
input port1(87) | TT | (FT)
input port2(87) | TT | (TF)
expression for output(88) |
input port1(88) | TT | (FT)
input port2(88) | TT | (TF)
expression for output(89) |
input port1(89) | TT | (FT)
input port2(89) | TT | (TF)
expression for output(90) |
input port1(90) | TT | (FT)
input port2(90) | TT | (TF)
expression for output(91) |
input port1(91) | TT | (FT)
input port2(91) | TT | (TF)
expression for output(92) |
input port1(92) | TT | (FT)
input port2(92) | TT | (TF)
expression for output(93) |
input port1(93) | TT | (FT)
input port2(93) | TT | (TF)
expression for output(94) |
input port1(94) | TT | (FT)
input port2(94) | TT | (TF)
expression for output(95) |
input port1(95) | TT | (FT)
input port2(95) | TT | (TF)
expression for output(96) |
input port1(96) | TT | (FT)
input port2(96) | TT | (TF)
expression for output(97) |
input port1(97) | TT | (FT)
input port2(97) | TT | (TF)
expression for output(98) |
input port1(98) | TT | (FT)
input port2(98) | TT | (TF)
expression for output(99) |
input port1(99) | TT | (FT)
input port2(99) | TT | (TF)
expression for output(100) |
input port1(100) | TT | (FT)
input port2(100) | TT | (TF)
expression for output(101) |
input port1(101) | TT | (FT)
input port2(101) | TT | (TF)
expression for output(102) |
input port1(102) | TT | (FT)
input port2(102) | TT | (TF)
expression for output(103) |
input port1(103) | TT | (FT)
input port2(103) | TT | (TF)
expression for output(104) |
input port1(104) | TT | (FT)
input port2(104) | TT | (TF)
expression for output(105) |
input port1(105) | TT | (FT)
input port2(105) | TT | (TF)
expression for output(106) |
input port1(106) | TT | (FT)
input port2(106) | TT | (TF)
expression for output(107) |
input port1(107) | TT | (FT)
input port2(107) | TT | (TF)
expression for output(108) |
input port1(108) | TT | (FT)
input port2(108) | TT | (TF)
expression for output(109) |
input port1(109) | TT | (FT)
input port2(109) | TT | (TF)
expression for output(110) |
input port1(110) | TT | (FT)
input port2(110) | TT | (TF)
expression for output(111) |
input port1(111) | TT | (FT)
input port2(111) | TT | (TF)
expression for output(112) |
input port1(112) | TT | (FT)
input port2(112) | TT | (TF)

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/SumCellVoltVld
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### RelationalOperator block "Comparison4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/SumCellVoltVld
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (112/224) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) == input2 | 1001 | 0
input1(2) == input2 | 1001 | 0
input1(3) == input2 | 1001 | 0
input1(4) == input2 | 1001 | 0
input1(5) == input2 | 1001 | 0
input1(6) == input2 | 1001 | 0
input1(7) == input2 | 1001 | 0
input1(8) == input2 | 1001 | 0
input1(9) == input2 | 1001 | 0
input1(10) == input2 | 1001 | 0
input1(11) == input2 | 1001 | 0
input1(12) == input2 | 1001 | 0
input1(13) == input2 | 1001 | 0
input1(14) == input2 | 1001 | 0
input1(15) == input2 | 1001 | 0
input1(16) == input2 | 1001 | 0
input1(17) == input2 | 1001 | 0
input1(18) == input2 | 1001 | 0
input1(19) == input2 | 1001 | 0
input1(20) == input2 | 1001 | 0
input1(21) == input2 | 1001 | 0
input1(22) == input2 | 1001 | 0
input1(23) == input2 | 1001 | 0
input1(24) == input2 | 1001 | 0
input1(25) == input2 | 1001 | 0
input1(26) == input2 | 1001 | 0
input1(27) == input2 | 1001 | 0
input1(28) == input2 | 1001 | 0
input1(29) == input2 | 1001 | 0
input1(30) == input2 | 1001 | 0
input1(31) == input2 | 1001 | 0
input1(32) == input2 | 1001 | 0
input1(33) == input2 | 1001 | 0
input1(34) == input2 | 1001 | 0
input1(35) == input2 | 1001 | 0
input1(36) == input2 | 1001 | 0
input1(37) == input2 | 1001 | 0
input1(38) == input2 | 1001 | 0
input1(39) == input2 | 1001 | 0
input1(40) == input2 | 1001 | 0
input1(41) == input2 | 1001 | 0
input1(42) == input2 | 1001 | 0
input1(43) == input2 | 1001 | 0
input1(44) == input2 | 1001 | 0
input1(45) == input2 | 1001 | 0
input1(46) == input2 | 1001 | 0
input1(47) == input2 | 1001 | 0
input1(48) == input2 | 1001 | 0
input1(49) == input2 | 1001 | 0
input1(50) == input2 | 1001 | 0
input1(51) == input2 | 1001 | 0
input1(52) == input2 | 1001 | 0
input1(53) == input2 | 1001 | 0
input1(54) == input2 | 1001 | 0
input1(55) == input2 | 1001 | 0
input1(56) == input2 | 1001 | 0
input1(57) == input2 | 1001 | 0
input1(58) == input2 | 1001 | 0
input1(59) == input2 | 1001 | 0
input1(60) == input2 | 1001 | 0
input1(61) == input2 | 1001 | 0
input1(62) == input2 | 1001 | 0
input1(63) == input2 | 1001 | 0
input1(64) == input2 | 1001 | 0
input1(65) == input2 | 1001 | 0
input1(66) == input2 | 1001 | 0
input1(67) == input2 | 1001 | 0
input1(68) == input2 | 1001 | 0
input1(69) == input2 | 1001 | 0
input1(70) == input2 | 1001 | 0
input1(71) == input2 | 1001 | 0
input1(72) == input2 | 1001 | 0
input1(73) == input2 | 1001 | 0
input1(74) == input2 | 1001 | 0
input1(75) == input2 | 1001 | 0
input1(76) == input2 | 1001 | 0
input1(77) == input2 | 1001 | 0
input1(78) == input2 | 1001 | 0
input1(79) == input2 | 1001 | 0
input1(80) == input2 | 1001 | 0
input1(81) == input2 | 1001 | 0
input1(82) == input2 | 1001 | 0
input1(83) == input2 | 1001 | 0
input1(84) == input2 | 1001 | 0
input1(85) == input2 | 1001 | 0
input1(86) == input2 | 1001 | 0
input1(87) == input2 | 1001 | 0
input1(88) == input2 | 1001 | 0
input1(89) == input2 | 1001 | 0
input1(90) == input2 | 1001 | 0
input1(91) == input2 | 1001 | 0
input1(92) == input2 | 1001 | 0
input1(93) == input2 | 1001 | 0
input1(94) == input2 | 1001 | 0
input1(95) == input2 | 1001 | 0
input1(96) == input2 | 1001 | 0
input1(97) == input2 | 1001 | 0
input1(98) == input2 | 1001 | 0
input1(99) == input2 | 1001 | 0
input1(100) == input2 | 1001 | 0
input1(101) == input2 | 1001 | 0
input1(102) == input2 | 1001 | 0
input1(103) == input2 | 1001 | 0
input1(104) == input2 | 1001 | 0
input1(105) == input2 | 1001 | 0
input1(106) == input2 | 1001 | 0
input1(107) == input2 | 1001 | 0
input1(108) == input2 | 1001 | 0
input1(109) == input2 | 1001 | 0
input1(110) == input2 | 1001 | 0
input1(111) == input2 | 1001 | 0
input1(112) == input2 | 1001 | 0

#### Full Coverage

Model Object | Metric
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant4" | Execution

### 508. SubSystem block "CellVoltVld"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/SumCellVoltVld
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 1
Condition | NA | 70% (7/10) condition outcomes
Decision | NA | 100% (2/2) decision outcomes
MCDC | NA | 0% (0/4) conditions reversed the outcome
Execution | NA | 100% (10/10) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/SumCellVoltVld/CellVoltVld
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 75% (3/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 96096 | 0
input port 2 | 95095 | 1001
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | TF | (FF)
input port 2 | (FT) | (FF)

#### Logic block "Logical Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/SumCellVoltVld/CellVoltVld
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (2/4) condition outcomes
MCDC | 0% (0/2) conditions reversed the outcome
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port 1 | 96096 | 0
input port 2 | 96096 | 0
MC/DC analysis (combinations in parentheses did not occur)
Decision/Condition | True Out | False Out
expression for output |
input port 1 | TT | (FT)
input port 2 | TT | (TF)

#### Full Coverage

Model Object | Metric
ForIterator block "CellVolt" | Decision
DataTypeConversion block "Data Type Conversion" | Execution
Sum block "Sum" | Execution
RelationalOperator block "Comparison1" | Condition, Execution
Constant block "Constant4" | Execution
Selector block "Selector" | Execution
UnitDelay block "Unit Delay" | Execution
UnitDelay block "Unit Delay1" | Execution
UnitDelay block "Unit Delay2" | Execution

### 509. SubSystem block "OverWrite"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/SumCellVoltVld
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/SumCellVoltVld/OverWrite
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 510. SubSystem block "Sum_CellVolt_Get_Sys"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get
Child Systems: | SumCellVot_Calculation, Sum_CellVolt_ForIterator
Uncovered Links: |
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 2 | 7
Decision | 50% (1/2) decision outcomes | 63% (5/8) decision outcomes
Execution | NA | 100% (15/15) objective outcomes
Decisions analyzed
enable logical value | 50%
false | 0/1001
true | 1001/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant3" | Execution

### 511. SubSystem block "SumCellVot_Calculation"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/Sum_CellVolt_Get_Sys
Child Systems: | OverWrite1, OverWrite2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 4
Decision | NA | 50% (2/4) decision outcomes
Execution | NA | 100% (11/11) objective outcomes

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution
Product block "Divide1" | Execution
Product block "Divide2" | Execution
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 512. SubSystem block "OverWrite1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/Sum_CellVolt_Get_Sys/SumCellVot_Calculation
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/Sum_CellVolt_Get_Sys/SumCellVot_Calculation/OverWrite1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 513. SubSystem block "OverWrite2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/Sum_CellVolt_Get_Sys/SumCellVot_Calculation
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/Sum_CellVolt_Get_Sys/SumCellVot_Calculation/OverWrite2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 514. SubSystem block "Sum_CellVolt_ForIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/MaxMinSum_CellVolt_Get/Sum_CellVolt_Get_Sys
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 1
Decision | NA | 100% (2/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Full Coverage

Model Object | Metric
ForIterator block "MaxCellVoltNumbIterator" | Decision
Sum block "Add" | Execution
Selector block "Selector" | Execution
UnitDelay block "Unit Delay" | Execution

### 515. SubSystem block "StackVolt"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys
Child Systems: | BMSDelay, BMSDelay1, CDP_GaCDP_StackVoltHighFlt_flg, CDP_GaCDP_StackVoltLowFlt_flg, OverWrite, OverWrite2, SumModellVot_Calc, Sum_ModelVolt_ForIterator
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 140
Condition | NA | 57% (129/226) condition outcomes
Decision | NA | 60% (152/252) decision outcomes
Execution | NA | 100% (50/50) objective outcomes

#### MinMax block "MinMax"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 15
Decision | 6% (1/16) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
Logic to determine output | 6%
input 1 is the minimum | 1001/1001
input 2 is the minimum | 0/1001
input 3 is the minimum | 0/1001
input 4 is the minimum | 0/1001
input 5 is the minimum | 0/1001
input 6 is the minimum | 0/1001
input 7 is the minimum | 0/1001
input 8 is the minimum | 0/1001
input 9 is the minimum | 0/1001
input 10 is the minimum | 0/1001
input 11 is the minimum | 0/1001
input 12 is the minimum | 0/1001
input 13 is the minimum | 0/1001
input 14 is the minimum | 0/1001
input 15 is the minimum | 0/1001
input 16 is the minimum | 0/1001

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 16
Decision | 50% (16/32) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input(1) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(2) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(3) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(4) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(5) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(6) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(7) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(8) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(9) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(10) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(11) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(12) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(13) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(14) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(15) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(16) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### RelationalOperator block "Comparison4"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (1/2) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1 == input2 | 0 | 1001

#### RelationalOperator block "Relational Operator1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (16/32) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) > input2 | 0 | 1001
input1(2) > input2 | 0 | 1001
input1(3) > input2 | 0 | 1001
input1(4) > input2 | 0 | 1001
input1(5) > input2 | 0 | 1001
input1(6) > input2 | 0 | 1001
input1(7) > input2 | 0 | 1001
input1(8) > input2 | 0 | 1001
input1(9) > input2 | 0 | 1001
input1(10) > input2 | 0 | 1001
input1(11) > input2 | 0 | 1001
input1(12) > input2 | 0 | 1001
input1(13) > input2 | 0 | 1001
input1(14) > input2 | 0 | 1001
input1(15) > input2 | 0 | 1001
input1(16) > input2 | 0 | 1001

#### RelationalOperator block "Relational Operator2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (16/32) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) < input2 | 1001 | 0
input1(2) < input2 | 1001 | 0
input1(3) < input2 | 1001 | 0
input1(4) < input2 | 1001 | 0
input1(5) < input2 | 1001 | 0
input1(6) < input2 | 1001 | 0
input1(7) < input2 | 1001 | 0
input1(8) < input2 | 1001 | 0
input1(9) < input2 | 1001 | 0
input1(10) < input2 | 1001 | 0
input1(11) < input2 | 1001 | 0
input1(12) < input2 | 1001 | 0
input1(13) < input2 | 1001 | 0
input1(14) < input2 | 1001 | 0
input1(15) < input2 | 1001 | 0
input1(16) < input2 | 1001 | 0

#### RelationalOperator block "Relational Operator3"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (16/32) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) == input2 | 0 | 1001
input1(2) == input2 | 0 | 1001
input1(3) == input2 | 0 | 1001
input1(4) == input2 | 0 | 1001
input1(5) == input2 | 0 | 1001
input1(6) == input2 | 0 | 1001
input1(7) == input2 | 0 | 1001
input1(8) == input2 | 0 | 1001
input1(9) == input2 | 0 | 1001
input1(10) == input2 | 0 | 1001
input1(11) == input2 | 0 | 1001
input1(12) == input2 | 0 | 1001
input1(13) == input2 | 0 | 1001
input1(14) == input2 | 0 | 1001
input1(15) == input2 | 0 | 1001
input1(16) == input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Constant block "Constant1" | Execution
Constant block "Constant2" | Execution
Constant block "Constant3" | Execution
Constant block "Constant4" | Execution
Constant block "Constant6" | Execution
Constant block "Constant7" | Execution
Constant block "Constant8" | Execution
Constant block "Constant9" | Execution
UnitDelay block "Unit Delay21" | Execution

### 516. SubSystem block "BMSDelay"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt
Child Systems: | Unit Delay Resettable
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 49
Condition | NA | 50% (32/64) condition outcomes
Decision | NA | 50% (48/96) decision outcomes
Execution | NA | 100% (7/7) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt/BMSDelay
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (16/32) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 0 | 1001
input port1(2) | 0 | 1001
input port1(3) | 0 | 1001
input port1(4) | 0 | 1001
input port1(5) | 0 | 1001
input port1(6) | 0 | 1001
input port1(7) | 0 | 1001
input port1(8) | 0 | 1001
input port1(9) | 0 | 1001
input port1(10) | 0 | 1001
input port1(11) | 0 | 1001
input port1(12) | 0 | 1001
input port1(13) | 0 | 1001
input port1(14) | 0 | 1001
input port1(15) | 0 | 1001
input port1(16) | 0 | 1001

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt/BMSDelay
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 16
Decision | 50% (16/32) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input(1) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(2) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(3) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(4) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(5) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(6) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(7) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(8) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(9) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(10) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(11) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(12) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(13) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(14) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(15) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(16) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### RelationalOperator block "Relational Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt/BMSDelay
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (16/32) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input1(1) >= input2 | 0 | 1001
input1(2) >= input2 | 0 | 1001
input1(3) >= input2 | 0 | 1001
input1(4) >= input2 | 0 | 1001
input1(5) >= input2 | 0 | 1001
input1(6) >= input2 | 0 | 1001
input1(7) >= input2 | 0 | 1001
input1(8) >= input2 | 0 | 1001
input1(9) >= input2 | 0 | 1001
input1(10) >= input2 | 0 | 1001
input1(11) >= input2 | 0 | 1001
input1(12) >= input2 | 0 | 1001
input1(13) >= input2 | 0 | 1001
input1(14) >= input2 | 0 | 1001
input1(15) >= input2 | 0 | 1001
input1(16) >= input2 | 0 | 1001

#### Full Coverage

Model Object | Metric
Sum block "Add" | Execution
Constant block "Constant" | Execution

### 517. SubSystem block "Unit Delay Resettable"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt/BMSDelay
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 32
Decision | NA | 50% (32/64) decision outcomes
Execution | NA | 100% (2/2) objective outcomes

#### Switch block "Init"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt/BMSDelay/Unit Delay Resettable
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 16
Decision | 50% (16/32) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input(1) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(2) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(3) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(4) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(5) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(6) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(7) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(8) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(9) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(10) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(11) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(12) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(13) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(14) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(15) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(16) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001

#### Switch block "Reset"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt/BMSDelay/Unit Delay Resettable
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 16
Decision | 50% (16/32) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input(1) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(2) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(3) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(4) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(5) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(6) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(7) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(8) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(9) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(10) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(11) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(12) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(13) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(14) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(15) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001
logical trigger input(16) | 50%
false (output is from 3rd input port) | 0/1001
true (output is from 1st input port) | 1001/1001

### 518. SubSystem block "BMSDelay1"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt
Child Systems: | Unit Delay Resettable
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 49
Condition | NA | 75% (48/64) condition outcomes
Decision | NA | 83% (80/96) decision outcomes
Execution | NA | 100% (7/7) objective outcomes

#### Logic block "Logical Operator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt/BMSDelay1
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 0
Condition | 50% (16/32) condition outcomes
Execution | 100% (1/1) objective outcomes
Conditions analyzed
Description | True | False
input port1(1) | 1001 | 0
input port1(2) | 1001 | 0
input port1(3) | 1001 | 0
input port1(4) | 1001 | 0
input port1(5) | 1001 | 0
input port1(6) | 1001 | 0
input port1(7) | 1001 | 0
input port1(8) | 1001 | 0
input port1(9) | 1001 | 0
input port1(10) | 1001 | 0
input port1(11) | 1001 | 0
input port1(12) | 1001 | 0
input port1(13) | 1001 | 0
input port1(14) | 1001 | 0
input port1(15) | 1001 | 0
input port1(16) | 1001 | 0

#### Full Coverage

Model Object | Metric
Switch block "Switch" | Decision, Execution
Sum block "Add" | Execution
RelationalOperator block "Relational Operator" | Condition, Execution
Constant block "Constant" | Execution

### 519. SubSystem block "Unit Delay Resettable"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt/BMSDelay1
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 32
Decision | NA | 75% (48/64) decision outcomes
Execution | NA | 100% (2/2) objective outcomes

#### Switch block "Reset"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt/BMSDelay1/Unit Delay Resettable
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 16
Decision | 50% (16/32) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input(1) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(2) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(3) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(4) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(5) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(6) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(7) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(8) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(9) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(10) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(11) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(12) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(13) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(14) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(15) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001
logical trigger input(16) | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Switch block "Init" | Decision, Execution

### 520. SubSystem block "CDP_GaCDP_StackVoltHighFlt_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt/CDP_GaCDP_StackVoltHighFlt_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 521. SubSystem block "CDP_GaCDP_StackVoltLowFlt_flg"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt/CDP_GaCDP_StackVoltLowFlt_flg
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 522. SubSystem block "OverWrite"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt/OverWrite
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 523. SubSystem block "OverWrite2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt/OverWrite2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 524. SubSystem block "SumModellVot_Calc"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt
Child Systems: | OverWrite2
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (6/6) objective outcomes

#### Full Coverage

Model Object | Metric
DataTypeConversion block "Data Type Conversion" | Execution
Product block "Divide2" | Execution
Constant block "Constant" | Execution

### 525. SubSystem block "OverWrite2"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt/SumModellVot_Calc
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 1 | 2
Decision | NA | 50% (1/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Switch block "Switch"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt/SumModellVot_Calc/OverWrite2
Uncovered Links: |
Metric | Coverage
Cyclomatic Complexity | 1
Decision | 50% (1/2) decision outcomes
Execution | 100% (1/1) objective outcomes
Decisions analyzed
logical trigger input | 50%
false (output is from 3rd input port) | 1001/1001
true (output is from 1st input port) | 0/1001

#### Full Coverage

Model Object | Metric
Constant block "Constant" | Execution
Constant block "Constant1" | Execution

### 526. SubSystem block "Sum_ModelVolt_ForIterator"

Justify or Exclude
Parent: | CDP_UT/CellDataPrc_20ms_sys/VoltDataPrc_20ms_sys/StackVolt
Metric | Coverage (this object) | Coverage (inc. descendants)
Cyclomatic Complexity | 0 | 1
Decision | NA | 100% (2/2) decision outcomes
Execution | NA | 100% (3/3) objective outcomes

#### Full Coverage

Model Object | Metric
ForIterator block "MaxStackVoltNumbIterator" | Decision
Sum block "Add" | Execution
Selector block "Selector" | Execution
UnitDelay block "Unit Delay" | Execution