/*
 * File: BCMR_DChrgParaCalc.h
 *
 * Code generated for Simulink model 'BCMR_DChrgParaCalc'.
 *
 * Model version                  : 1.703
 * Simulink Coder version         : 8.11 (R2016b) 25-Aug-2016
 * C/C++ source code generated on : Fri Aug 27 14:36:36 2021
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#ifndef RTW_HEADER_BCMR_DChrgParaCalc_h_
#define RTW_HEADER_BCMR_DChrgParaCalc_h_
#include <math.h>
#include <string.h>
#include <stddef.h>
#ifndef BCMR_DChrgParaCalc_COMMON_INCLUDES_
# define BCMR_DChrgParaCalc_COMMON_INCLUDES_
#include "rtwtypes.h"
#include "zero_crossing_types.h"
#endif                                 /* BCMR_DChrgParaCalc_COMMON_INCLUDES_ */

#include "BCMR_DChrgParaCalc_types.h"

/* Includes for objects with custom storage classes. */
#include "dchrg_para_parameters.h"
#include "look2_iflf_binlcapw.h"
#include "plook_u32f_bincka.h"

/* Macros for accessing real-time model data structure */

/* user code (top of header file) */
#include "ASW_Interface.h"

/* Block signals for system '<S55>/HoldOn' */
typedef struct {
  real32_T CurrCalc;                   /* '<S55>/HoldOn' */
  uint8_T CurrMethod;                  /* '<S55>/HoldOn' */
} B_HoldOn_BCMR_DChrgParaCalc_T;

/* Block states (auto storage) for system '<S55>/HoldOn' */
typedef struct {
  real32_T CurrCompare;                /* '<S55>/HoldOn' */
  uint32_T temporalCounter_i1;         /* '<S55>/HoldOn' */
  uint8_T is_active_c2_BCMR_DChrgParaCalc;/* '<S55>/HoldOn' */
  uint8_T is_c2_BCMR_DChrgParaCalc;    /* '<S55>/HoldOn' */
  uint8_T is_CurrCalc;                 /* '<S55>/HoldOn' */
  uint8_T is_ChkTable;                 /* '<S55>/HoldOn' */
  uint8_T StepKeepL;                   /* '<S55>/HoldOn' */
  uint8_T StepKeepN;                   /* '<S55>/HoldOn' */
  uint8_T TempKeepL;                   /* '<S55>/HoldOn' */
  uint8_T TempKeepN;                   /* '<S55>/HoldOn' */
  boolean_T FirstFlg;                  /* '<S55>/HoldOn' */
  boolean_T TableChkFlg;               /* '<S55>/HoldOn' */
  boolean_T VoltStepFlg;               /* '<S55>/HoldOn' */
} DW_HoldOn_BCMR_DChrgParaCalc_T;

/* Block signals for system '<S21>/ParaStep' */
typedef struct {
  uint8_T ParaStep;                    /* '<S21>/ParaStep' */
} B_ParaStep_BCMR_DChrgParaCalc_T;

/* Block states (auto storage) for system '<S21>/ParaStep' */
typedef struct {
  uint32_T temporalCounter_i1;         /* '<S21>/ParaStep' */
  uint8_T is_active_c4_BCMR_DChrgParaCalc;/* '<S21>/ParaStep' */
  uint8_T is_c4_BCMR_DChrgParaCalc;    /* '<S21>/ParaStep' */
} DW_ParaStep_BCMR_DChrgParaCal_T;

/* Block signals for system '<S21>/ParaStep2' */
typedef struct {
  uint8_T ParaStep;                    /* '<S21>/ParaStep2' */
} B_ParaStep2_BCMR_DChrgParaCal_T;

/* Block states (auto storage) for system '<S21>/ParaStep2' */
typedef struct {
  uint8_T is_active_c1_BCMR_DChrgParaCalc;/* '<S21>/ParaStep2' */
  uint8_T is_c1_BCMR_DChrgParaCalc;    /* '<S21>/ParaStep2' */
} DW_ParaStep2_BCMR_DChrgParaCa_T;

/* Block signals for system '<S22>/ParaStep1' */
typedef struct {
  uint8_T ParaStep;                    /* '<S22>/ParaStep1' */
} B_ParaStep1_BCMR_DChrgParaCal_T;

/* Block states (auto storage) for system '<S22>/ParaStep1' */
typedef struct {
  uint8_T is_active_c18_BCMR_DChrgParaCal;/* '<S22>/ParaStep1' */
  uint8_T is_c18_BCMR_DChrgParaCalc;   /* '<S22>/ParaStep1' */
} DW_ParaStep1_BCMR_DChrgParaCa_T;

/* Block signals (auto storage) */
typedef struct {
  real32_T MinMax;                     /* '<S15>/MinMax' */
  real32_T MinMax2;                    /* '<S26>/MinMax2' */
  real32_T Gain1;                      /* '<S25>/Gain1' */
  real32_T Switch2;                    /* '<S29>/Switch2' */
  real32_T BCMR_rSocInit;              /* '<S2>/Chart' */
  B_ParaStep1_BCMR_DChrgParaCal_T sf_ParaStep1;/* '<S22>/ParaStep1' */
  B_ParaStep_BCMR_DChrgParaCalc_T sf_ParaStep_c;/* '<S22>/ParaStep' */
  B_HoldOn_BCMR_DChrgParaCalc_T sf_HoldOn_i;/* '<S60>/HoldOn' */
  B_ParaStep2_BCMR_DChrgParaCal_T sf_ParaStep2;/* '<S21>/ParaStep2' */
  B_ParaStep_BCMR_DChrgParaCalc_T sf_ParaStep;/* '<S21>/ParaStep' */
  B_HoldOn_BCMR_DChrgParaCalc_T sf_HoldOn;/* '<S55>/HoldOn' */
} B_BCMR_DChrgParaCalc_T;

/* Block states (auto storage) for system '<Root>' */
typedef struct {
  real32_T Delay_DSTATE;                 /* '<S41>/Delay' */
  real32_T UnitDelay1_DSTATE;          /* '<S99>/Unit Delay1' */
  real32_T Delay_DSTATE_e;             /* '<S106>/Delay' */
  real32_T Delay_DSTATE_m;             /* '<S105>/Delay' */
  real32_T Delay_DSTATE_g;             /* '<S14>/Delay' */
  real32_T Delay_DSTATE_o;             /* '<S97>/Delay' */
  real32_T Delay_DSTATE_ej;            /* '<S94>/Delay' */
  real32_T UnitDelay_DSTATE;           /* '<S89>/Unit Delay' */
  real32_T UnitDelay_DSTATE_k;         /* '<S92>/Unit Delay' */
  real32_T UnitDelay4_DSTATE;          /* '<S38>/Unit Delay4' */
  real32_T Delay1_DSTATE[2];           /* '<S42>/Delay1' */
  real32_T Delay1_DSTATE_p[2];         /* '<S43>/Delay1' */
  real32_T Delay_DSTATE_ml;            /* '<S20>/Delay' */
  real32_T Delay1_DSTATE_e;            /* '<S34>/Delay1' */
  real32_T Delay_DSTATE_p;             /* '<S44>/Delay' */
  real32_T Delay_DSTATE_c[2];          /* '<S53>/Delay' */
  real32_T Delay_DSTATE_h[2];          /* '<S52>/Delay' */
  real32_T Delay_DSTATE_k[2];          /* '<S48>/Delay' */
  real32_T UnitDelay_DSTATE_c;         /* '<S41>/Unit Delay' */
  real32_T Delay_DSTATE_my;            /* '<S37>/Delay' */
  real32_T Delay_DSTATE_ea;            /* '<S32>/Delay' */
  real32_T UnitDelay4_DSTATE_h;        /* '<S16>/Unit Delay4' */
  uint16_T StateName;                  /* '<S73>/Unit Delay' */
  uint16_T StateName_l;                /* '<S74>/Unit Delay1' */
  uint8_T UnitDelay_DSTATE_f;          /* '<S86>/Unit Delay' */
  uint8_T Delay2_DSTATE;               /* '<S21>/Delay2' */
  uint8_T Delay3_DSTATE;               /* '<S21>/Delay3' */
  uint8_T Delay2_DSTATE_c;             /* '<S22>/Delay2' */
  uint8_T Delay3_DSTATE_o;             /* '<S22>/Delay3' */
  boolean_T Delay2_DSTATE_ch;          /* '<S70>/Delay2' */
  boolean_T Delay_DSTATE_ol;           /* '<S88>/Delay' */
  boolean_T Delay2_DSTATE_p;           /* '<S71>/Delay2' */
  boolean_T Delay_DSTATE_i;            /* '<S91>/Delay' */
  boolean_T Delay1_DSTATE_k;           /* '<S90>/Delay1' */
  boolean_T Delay1_DSTATE_d;           /* '<S87>/Delay1' */
  boolean_T Delay1_DSTATE_o;           /* '<S85>/Delay1' */
  boolean_T Delay1_DSTATE_i;           /* '<S84>/Delay1' */
  boolean_T StateName_o;               /* '<S64>/Unit Delay' */
  boolean_T StateName_c;               /* '<S73>/Unit Delay1' */
  boolean_T StateName_co;              /* '<S74>/Unit Delay2' */
  boolean_T UnitDelay1_DSTATE_a;       /* '<S42>/Unit Delay1' */
  boolean_T UnitDelay1_DSTATE_h;       /* '<S43>/Unit Delay1' */
  boolean_T UnitDelay_DSTATE_n;        /* '<S20>/Unit Delay' */
  boolean_T UnitDelay1_DSTATE_c;       /* '<S34>/Unit Delay1' */
  uint8_T is_active_c7_BCMR_DChrgParaCalc;/* '<S20>/CurrFilt' */
  uint8_T is_c7_BCMR_DChrgParaCalc;    /* '<S20>/CurrFilt' */
  uint8_T is_active_c3_BCMR_DChrgParaCalc;/* '<S2>/Chart' */
  boolean_T IC_FirstOutputTime;        /* '<S16>/IC' */
  boolean_T DcChgParaCalc_MODE;        /* '<S1>/DcChgParaCalc' */
  boolean_T AccumAhCalc_MODE;          /* '<S2>/AccumAhCalc' */
  boolean_T CurrReqCalc_MODE;          /* '<S2>/CurrReqCalc' */
  boolean_T CurrPro_MODE;              /* '<S21>/CurrPro' */
  boolean_T CurrPro_MODE_m;            /* '<S22>/CurrPro' */
  DW_ParaStep1_BCMR_DChrgParaCa_T sf_ParaStep1;/* '<S22>/ParaStep1' */
  DW_ParaStep_BCMR_DChrgParaCal_T sf_ParaStep_c;/* '<S22>/ParaStep' */
  DW_HoldOn_BCMR_DChrgParaCalc_T sf_HoldOn_i;/* '<S60>/HoldOn' */
  DW_ParaStep2_BCMR_DChrgParaCa_T sf_ParaStep2;/* '<S21>/ParaStep2' */
  DW_ParaStep_BCMR_DChrgParaCal_T sf_ParaStep;/* '<S21>/ParaStep' */
  DW_HoldOn_BCMR_DChrgParaCalc_T sf_HoldOn;/* '<S55>/HoldOn' */
} DW_BCMR_DChrgParaCalc_T;

/* Zero-crossing (trigger) state */
typedef struct {
  ZCSigState Chart_Trig_ZCE;           /* '<S2>/Chart' */
} PrevZCX_BCMR_DChrgParaCalc_T;

/* External outputs (root outports fed by signals with auto storage) */
typedef struct {
  real32_T BCMR_ahAccumDChrgAh_i;      /* '<Root>/BCMR_ahAccumDChrgAh' */
  boolean_T BCMR_bAccumAhDChrgFul_f;   /* '<Root>/BCMR_bAccumAhDChrgFul' */
} ExtY_BCMR_DChrgParaCalc_T;

/* Block signals (auto storage) */
extern B_BCMR_DChrgParaCalc_T BCMR_DChrgParaCalc_B;

/* Block states (auto storage) */
extern DW_BCMR_DChrgParaCalc_T BCMR_DChrgParaCalc_DW;

/* External outputs (root outports fed by signals with auto storage) */
extern ExtY_BCMR_DChrgParaCalc_T BCMR_DChrgParaCalc_Y;

/*
 * Exported Global Signals
 *
 * Note: Exported global signals are block signals with an exported global
 * storage class designation.  Code generation will declare the memory for
 * these signals and export their symbols.
 *
 */
extern uint8_T BCMR_numCellVoltFullCnt;/* '<S86>/Switch1' */
extern uint8_T CurrMethodMax;          /* '<S55>/HoldOn' */
extern boolean_T BCMR_bCellVoltFull;   /* '<S66>/Compare' */
extern boolean_T BCMR_bCellVoltFullTmrRaw;/* '<S88>/Logical Operator4' */
extern boolean_T BCMR_bCellVoltFullTmr;/* '<S70>/Relational Operator2' */
extern boolean_T BCMR_flgDChrgFulChkRaw;/* '<S11>/Logical Operator2' */
extern boolean_T BCMR_bCellVoltFullCnt;/* '<S82>/Compare' */
extern boolean_T BCMR_bCellVoltFullTriger;/* '<S83>/Compare' */
extern boolean_T equalFlg;             /* '<S38>/Relational Operator2' */

/* Model entry point functions */
extern void BCMR_DChrgParaCalc_initialize(void);
extern void BCMR_DChrgParaCalc_step(void);

/* Exported data declaration */
#define ASW1_OEM_START_SEC_DEFAULT_RAM1_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: OutputSignal */
extern volatile real32_T BCMR_ahAccumDChrgAh;
extern volatile boolean_T BCMR_bAccumAhDChrgFul;
extern volatile boolean_T BCMR_bDChrgCurrOutputEna;
extern volatile boolean_T BCMR_bDChrgCurrReqEna;
extern volatile boolean_T BCMR_bStakeParaOk;
extern volatile boolean_T BCMR_flgDChrgFulChk;
extern volatile boolean_T BCMR_flgDChrgPwrRdc;
extern volatile real32_T BCMR_iBattDCCurrReqFinal;
extern volatile real32_T BCMR_iDCCurrReqFil2;
extern volatile real32_T BCMR_iDCCurrReqRaw[2];
extern volatile real32_T BCMR_iDChrgBattCurrReqCalc;
extern volatile real32_T BCMR_iDChrgCalcMax;
extern volatile real32_T BCMR_iDChrgCalcMix2;
extern volatile real32_T BCMR_iDChrgCurrReqCalc;
extern volatile real32_T BCMR_iDChrgLoadCurrReqCalc;
extern volatile uint8_T BCMR_numDChrgTempStepMax;
extern volatile uint8_T BCMR_numDChrgTempStepMix2;
extern volatile uint8_T BCMR_numDChrgVoltStepMax;
extern volatile uint8_T BCMR_numDChrgVoltStepMix2;
extern volatile uint8_T BCMR_stDChrgCnnt;
extern volatile real32_T BCMR_tBattTempMaxFil[2];
extern volatile real32_T BCMR_uCellVoltMaxFil[2];
extern volatile real32_T BCMR_uDcChrgVoltReqCalc;

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM1_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'BCMR_DChrgParaCalc'
 * '<S1>'   : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc'
 * '<S2>'   : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc'
 * '<S3>'   : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/ModuleInputSigPro'
 * '<S4>'   : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/AccumAhCalc'
 * '<S5>'   : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/Chart'
 * '<S6>'   : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/Compare To Constant'
 * '<S7>'   : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/Compare To Constant1'
 * '<S8>'   : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/Compare To Constant2'
 * '<S9>'   : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/Compare To Constant4'
 * '<S10>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc'
 * '<S11>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk'
 * '<S12>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/ParaInfoMatch'
 * '<S13>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/Subsystem'
 * '<S14>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/TONV_TimeDebounce4'
 * '<S15>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/VoltReqCalc'
 * '<S16>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/AccumAhCalc/AccmAh'
 * '<S17>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/AccumAhCalc/AccmAhChgFulChk'
 * '<S18>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrCalc'
 * '<S19>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrMerge'
 * '<S20>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrSpTemp'
 * '<S21>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/MaxCurrCalc'
 * '<S22>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/MixCurrCalc2'
 * '<S23>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrCalc/BattCurrReq'
 * '<S24>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrCalc/BattCurrReq1'
 * '<S25>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrCalc/LoadCurrReq'
 * '<S26>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrCalc/BattCurrReq/CurrPro'
 * '<S27>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrCalc/BattCurrReq/CurrPro/Compare To Constant1'
 * '<S28>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrCalc/BattCurrReq/CurrPro/Compare To Constant4'
 * '<S29>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrCalc/BattCurrReq1/CurrPro'
 * '<S30>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrCalc/BattCurrReq1/CurrPro/Compare To Constant1'
 * '<S31>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrCalc/BattCurrReq1/CurrPro/Compare To Constant2'
 * '<S32>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrCalc/BattCurrReq1/CurrPro/TONV_VariableTimeDebounce'
 * '<S33>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrCalc/LoadCurrReq/Compare To Constant'
 * '<S34>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrCalc/LoadCurrReq/SIgFil1'
 * '<S35>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrCalc/LoadCurrReq/SIgFil1/Filter'
 * '<S36>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrCalc/LoadCurrReq/SIgFil1/Filter/Compare To Constant'
 * '<S37>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrCalc/LoadCurrReq/SIgFil1/Filter/TONV_VariableTimeDebounce'
 * '<S38>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrMerge/ShadeFall'
 * '<S39>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrSpTemp/CurrFilt'
 * '<S40>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrSpTemp/DCChrgFilter '
 * '<S41>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrSpTemp/K_Lowpass2'
 * '<S42>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrSpTemp/SIgFil'
 * '<S43>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrSpTemp/SIgFil1'
 * '<S44>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrSpTemp/TONV_VariableTimeDebounce'
 * '<S45>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrSpTemp/DCChrgFilter /Compare To Constant'
 * '<S46>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrSpTemp/SIgFil/Filter'
 * '<S47>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrSpTemp/SIgFil/Filter/Compare To Constant'
 * '<S48>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrSpTemp/SIgFil/Filter/TONV_VariableTimeDebounce'
 * '<S49>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrSpTemp/SIgFil1/Filter'
 * '<S50>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrSpTemp/SIgFil1/Filter/Compare To Constant'
 * '<S51>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrSpTemp/SIgFil1/Filter/Compare To Constant1'
 * '<S52>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrSpTemp/SIgFil1/Filter/TONV_VariableTimeDebounce'
 * '<S53>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/CurrSpTemp/SIgFil1/Filter/TONV_VariableTimeDebounce1'
 * '<S54>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/MaxCurrCalc/Compare To Zero1'
 * '<S55>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/MaxCurrCalc/CurrPro'
 * '<S56>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/MaxCurrCalc/ParaStep'
 * '<S57>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/MaxCurrCalc/ParaStep2'
 * '<S58>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/MaxCurrCalc/CurrPro/HoldOn'
 * '<S59>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/MixCurrCalc2/Compare To Zero1'
 * '<S60>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/MixCurrCalc2/CurrPro'
 * '<S61>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/MixCurrCalc2/ParaStep'
 * '<S62>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/MixCurrCalc2/ParaStep1'
 * '<S63>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/CurrReqCalc/MixCurrCalc2/CurrPro/HoldOn'
 * '<S64>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/BMSDCDebounceStartZero'
 * '<S65>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/CellVoltFulCnt'
 * '<S66>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/Compare To Constant1'
 * '<S67>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/Compare To Constant2'
 * '<S68>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/Compare To Constant3'
 * '<S69>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/Compare To Constant4'
 * '<S70>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/StateRetention1'
 * '<S71>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/StateRetention2'
 * '<S72>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/BMSDCDebounceStartZero/Compare To Zero'
 * '<S73>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/BMSDCDebounceStartZero/FaultProcess'
 * '<S74>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/BMSDCDebounceStartZero/HealProcess'
 * '<S75>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/BMSDCDebounceStartZero/FaultProcess/Decrease'
 * '<S76>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/BMSDCDebounceStartZero/FaultProcess/Increase'
 * '<S77>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/BMSDCDebounceStartZero/FaultProcess/Decrease/Nomal'
 * '<S78>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/BMSDCDebounceStartZero/HealProcess/Compare To Zero'
 * '<S79>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/BMSDCDebounceStartZero/HealProcess/Decrease'
 * '<S80>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/BMSDCDebounceStartZero/HealProcess/Increase'
 * '<S81>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/BMSDCDebounceStartZero/HealProcess/Decrease/Nomal'
 * '<S82>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/CellVoltFulCnt/Compare To Constant'
 * '<S83>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/CellVoltFulCnt/Compare To Constant1'
 * '<S84>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/CellVoltFulCnt/EdgeRising'
 * '<S85>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/CellVoltFulCnt/EdgeRising1'
 * '<S86>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/CellVoltFulCnt/Timer'
 * '<S87>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/StateRetention1/EdgeRising'
 * '<S88>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/StateRetention1/Subsystem3'
 * '<S89>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/StateRetention1/Timer'
 * '<S90>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/StateRetention2/EdgeRising'
 * '<S91>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/StateRetention2/Subsystem3'
 * '<S92>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/DChrgFulChk/StateRetention2/Timer'
 * '<S93>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/ParaInfoMatch/Compare To Constant1'
 * '<S94>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/ParaInfoMatch/TONV_VariableTimeDebounce'
 * '<S95>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/Subsystem/Compare To Constant1'
 * '<S96>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/Subsystem/Compare To Constant2'
 * '<S97>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/DcChgParaCalc/Subsystem/TONV_VariableTimeDebounce1'
 * '<S98>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/ModuleInputSigPro/BattTempPro'
 * '<S99>'  : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/ModuleInputSigPro/CellVolt'
 * '<S100>' : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/ModuleInputSigPro/Compare To Constant2'
 * '<S101>' : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/ModuleInputSigPro/CoolantPro'
 * '<S102>' : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/ModuleInputSigPro/BattTempPro/Compare To Constant2'
 * '<S103>' : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/ModuleInputSigPro/BattTempPro/Compare To Constant3'
 * '<S104>' : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/ModuleInputSigPro/BattTempPro/Compare To Constant4'
 * '<S105>' : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/ModuleInputSigPro/BattTempPro/TONV_VariableTimeDebounce'
 * '<S106>' : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/ModuleInputSigPro/BattTempPro/TONV_VariableTimeDebounce1'
 * '<S107>' : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/ModuleInputSigPro/CellVolt/Compare To Constant1'
 * '<S108>' : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/ModuleInputSigPro/CellVolt/Compare To Constant2'
 * '<S109>' : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/ModuleInputSigPro/CellVolt/Compare To Constant3'
 * '<S110>' : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/ModuleInputSigPro/CellVolt/Compare To Constant4'
 * '<S111>' : 'BCMR_DChrgParaCalc/BCMR_DChrg_ParaCalc/ModuleInputSigPro/CoolantPro/Compare To Constant2'
 */
#endif                                 /* RTW_HEADER_BCMR_DChrgParaCalc_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
