/*
 * File: BSER_CellBalcCtl.h
 *
 * Code generated for Simulink model 'BSER_CellBalcCtl'.
 *
 * Model version                  : D6_0
 * Simulink Coder version         : 8.11 (R2016b) 25-Aug-2016
 * C/C++ source code generated on : Tue Dec 15 10:14:15 2020
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#ifndef RTW_HEADER_BSER_CellBalcCtl_h_
#define RTW_HEADER_BSER_CellBalcCtl_h_
#include <math.h>
#include <string.h>
#include <stddef.h>
#ifndef BSER_CellBalcCtl_COMMON_INCLUDES_
# define BSER_CellBalcCtl_COMMON_INCLUDES_
#include "rtwtypes.h"
#endif                                 /* BSER_CellBalcCtl_COMMON_INCLUDES_ */

#include "BSER_CellBalcCtl_types.h"

/* Includes for objects with custom storage classes. */
#include "balctl_parameters.h"
#include "look1_iflf_binlcpw.h"
#include "mglflnohppppbiek_sort.h"

/* Macros for accessing real-time model data structure */

/* user code (top of header file) */
#include "ASW_Interface.h"

/* Block signals for system '<S7>/BSER_CellBalSortCal' */
typedef struct {
  boolean_T BSER_bCellBalEna_A[96];    /* '<S12>/BSER_CellBalSort' */
} B_BSER_CellBalSortCal_BSER_Ce_T;

/* Block states (auto storage) for system '<S7>/BSER_CellBalSortCal' */
typedef struct {
  boolean_T UnitDelay_DSTATE[8];       /* '<S16>/Unit Delay' */
  boolean_T UnitDelay_DSTATE_c[8];     /* '<S15>/Unit Delay' */
  uint8_T i;                           /* '<S12>/BSER_CellBalSort' */
} DW_BSER_CellBalSortCal_BSER_C_T;

/* Block signals for system '<S9>/CBCBMSDebounceStartZero1' */
typedef struct {
  boolean_T Switch;                    /* '<S35>/Switch' */
} B_CBCBMSDebounceStartZero1_BS_T;

/* Block states (auto storage) for system '<S9>/CBCBMSDebounceStartZero1' */
typedef struct {
  uint16_T StateName;                  /* '<S48>/Unit Delay' */
  uint16_T StateName_f;                /* '<S49>/Unit Delay1' */
  boolean_T StateName_k;               /* '<S35>/Unit Delay' */
  boolean_T StateName_h;               /* '<S48>/Unit Delay1' */
  boolean_T StateName_d;               /* '<S49>/Unit Delay2' */
} DW_CBCBMSDebounceStartZero1_B_T;

/* Block signals (auto storage) */
typedef struct {
  real32_T uDLookupTable[16];          /* '<S92>/1-D Lookup Table' */
  real32_T Gain1;                      /* '<S4>/Gain1' */
  boolean_T Merge[96];                 /* '<S7>/Merge' */
  boolean_T bBalDrvInteAct;            /* '<S19>/Chart' */
  boolean_T BSER_bCellBalFlg;          /* '<S7>/BSER_CellBalSeqChart' */
  enmBalRunSts BSER_bBalaVald_h;       /* '<S3>/BSER_CellBalCtrlRunTi' */
  enmBalDrvInteSts stBalDrvInteFlg;    /* '<S19>/Chart' */
  B_CBCBMSDebounceStartZero1_BS_T CBCBMSDebounceStartZero2;/* '<S9>/CBCBMSDebounceStartZero2' */
  B_CBCBMSDebounceStartZero1_BS_T CBCBMSDebounceStartZero1;/* '<S9>/CBCBMSDebounceStartZero1' */
  B_BSER_CellBalSortCal_BSER_Ce_T BSER_CellBalSortCal;/* '<S7>/BSER_CellBalSortCal' */
} B_BSER_CellBalcCtl_T;

/* Block states (auto storage) for system '<Root>' */
typedef struct {
  real32_T Delay_DSTATE;                 /* '<S93>/Delay' */
  real32_T UnitDelay_DSTATE[16];       /* '<S93>/Unit Delay' */
  real32_T Delay_DSTATE_f;             /* '<S25>/Delay' */
  real32_T Delay_DSTATE_g;             /* '<S34>/Delay' */
  real32_T Delay_DSTATE_i;             /* '<S33>/Delay' */
  real32_T Delay_DSTATE_j;             /* '<S32>/Delay' */
  real32_T Delay_DSTATE_h;             /* '<S31>/Delay' */
  real32_T Delay_DSTATE_je;            /* '<S30>/Delay' */
  real32_T Delay_DSTATE_hc;            /* '<S29>/Delay' */
  real32_T Cnt;                        /* '<S19>/Chart' */
  real32_T i;                          /* '<S7>/BSER_CellBalSeqChart' */
  real32_T cntBalOn;                   /* '<S7>/BSER_CellBalSeqChart' */
  real32_T i_j;                        /* '<S3>/BSER_CellBalCtrlRunTi' */
  boolean_T Delay_DSTATE_p;            /* '<S4>/Delay' */
  boolean_T Delay1_DSTATE;             /* '<S19>/Delay1' */
  boolean_T UnitDelay_DSTATE_g[8];     /* '<S46>/Unit Delay' */
  boolean_T UnitDelay_DSTATE_o[8];     /* '<S45>/Unit Delay' */
  boolean_T UnitDelay_DSTATE_p[8];     /* '<S44>/Unit Delay' */
  boolean_T UnitDelay_DSTATE_n[8];     /* '<S43>/Unit Delay' */
  boolean_T Delay2_DSTATE;             /* '<S42>/Delay2' */
  boolean_T Delay2_DSTATE_l;           /* '<S41>/Delay2' */
  boolean_T Delay2_DSTATE_e;           /* '<S40>/Delay2' */
  boolean_T Delay2_DSTATE_a;           /* '<S39>/Delay2' */
  boolean_T Delay1_DSTATE_c;           /* '<S28>/Delay1' */
  uint8_T is_active_c4_BSER_CellBalcCtl;/* '<S19>/Chart' */
  uint8_T is_c4_BSER_CellBalcCtl;      /* '<S19>/Chart' */
  uint8_T is_active_c2_BSER_CellBalcCtl;/* '<S7>/BSER_CellBalSeqChart' */
  uint8_T is_c2_BSER_CellBalcCtl;      /* '<S7>/BSER_CellBalSeqChart' */
  uint8_T is_BalCourse_Stt;            /* '<S7>/BSER_CellBalSeqChart' */
  uint8_T is_active_c3_BSER_CellBalcCtl;/* '<S3>/BSER_CellBalCtrlRunTi' */
  uint8_T is_c3_BSER_CellBalcCtl;      /* '<S3>/BSER_CellBalCtrlRunTi' */
  boolean_T Subsystem_MODE;            /* '<S2>/Subsystem' */
  boolean_T BSER_CellBalCtlCal_MODE;   /* '<S1>/BSER_CellBalCtlCal' */
  DW_CBCBMSDebounceStartZero1_B_T CBCBMSDebounceStartZero2;/* '<S9>/CBCBMSDebounceStartZero2' */
  DW_CBCBMSDebounceStartZero1_B_T CBCBMSDebounceStartZero1;/* '<S9>/CBCBMSDebounceStartZero1' */
  DW_BSER_CellBalSortCal_BSER_C_T BSER_CellBalSortCal;/* '<S7>/BSER_CellBalSortCal' */
} DW_BSER_CellBalcCtl_T;

/* Invariant block signals (auto storage) */
typedef struct {
  const uint8_T DataTypeConversion;    /* '<S6>/Data Type Conversion' */
  const uint8_T DataTypeConversion1;   /* '<S6>/Data Type Conversion1' */
  const uint8_T DataTypeConversion2;   /* '<S6>/Data Type Conversion2' */
  const uint8_T DataTypeConversion3;   /* '<S6>/Data Type Conversion3' */
  const uint8_T DataTypeConversion4;   /* '<S6>/Data Type Conversion4' */
  const uint8_T DataTypeConversion5;   /* '<S6>/Data Type Conversion5' */
  const uint8_T DataTypeConversion6;   /* '<S6>/Data Type Conversion6' */
  const uint8_T DataTypeConversion_o;  /* '<S26>/Data Type Conversion' */
  const uint8_T DataTypeConversion_n;  /* '<S17>/Data Type Conversion' */
  const uint8_T DataTypeConversion2_a; /* '<S18>/Data Type Conversion2' */
  const uint8_T DataTypeConversion_i;  /* '<S24>/Data Type Conversion' */
  const uint8_T DataTypeConversion1_l; /* '<S24>/Data Type Conversion1' */
} ConstB_BSER_CellBalcCtl_T;

/* Block signals (auto storage) */
extern B_BSER_CellBalcCtl_T BSER_CellBalcCtl_B;

/* Block states (auto storage) */
extern DW_BSER_CellBalcCtl_T BSER_CellBalcCtl_DW;
extern const ConstB_BSER_CellBalcCtl_T BSER_CellBalcCtl_ConstB;/* constant block i/o */

/* Model entry point functions */
extern void BSER_CellBalcCtl_initialize(void);
extern void BSER_CellBalcCtl_step(void);

/* Exported data declaration */

/* Volatile memory section */
#define ASW1_OEM_START_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: Volatile */
extern volatile uint8_T DFC_AFETempHighFlt_ASW;
extern volatile uint8_T DFC_BalCirOpenFlt_ASW;
extern volatile uint8_T DFC_BalCirShortFlt_ASW;
extern volatile uint8_T DFC_BalTempHighFlt_ASW;

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"
#define ASW1_OEM_START_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: OutputSignal */
extern volatile boolean_T BSER_bBalDrvInteAct;
extern volatile boolean_T BSER_bBalFltNrm;
extern volatile boolean_T BSER_bBalaVald;
extern volatile boolean_T BSER_bCellBalACMode;
extern volatile boolean_T BSER_bCellBalDCMode;
extern volatile boolean_T BSER_bCellBalNrmEna;
extern volatile boolean_T BSER_bCellBalOffDna;
extern volatile boolean_T BSER_bCellBalOnEna;
extern volatile boolean_T BSER_bCellBalTempDvtEna;
extern volatile boolean_T BSER_bCellBalTempNrmEna;
extern volatile boolean_T BSER_bCellBalVoltNrmEna;
extern volatile boolean_T BSER_bCmcAFETempVld[8];
extern volatile boolean_T BSER_bCmcBordTempVld[8];
extern volatile boolean_T BSER_bCmuBalEna_A[8];
extern volatile boolean_T BSER_bCmuTNormFlg;
extern volatile boolean_T BSER_bFaultLvlEna;
extern volatile boolean_T BSER_bWkBalEna;
extern volatile uint8_T BSER_stBal;
extern volatile uint8_T BSER_stBalErrorCode;
extern volatile uint8_T BSER_stBalInteChgFlg;
extern volatile uint8_T BSER_stCellBal[96];
extern volatile real32_T BSER_tCmcAFETemp_A[8];
extern volatile real32_T BSER_tCmcBordMaxTemp;
extern volatile real32_T BSER_tCmcBordTempAll_A[16];
extern volatile real32_T BSER_tCmcBordTemp_A[8];

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'BSER_CellBalcCtl'
 * '<S1>'   : 'BSER_CellBalcCtl/BSER_CellBalCtl'
 * '<S2>'   : 'BSER_CellBalcCtl/SigProc'
 * '<S3>'   : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_BalStartEnaCal'
 * '<S4>'   : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal'
 * '<S5>'   : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_BalStartEnaCal/BSER_CellBalCtrlRunTi'
 * '<S6>'   : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_BalErrCodeCal'
 * '<S7>'   : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalCal'
 * '<S8>'   : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalEnaCal'
 * '<S9>'   : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal'
 * '<S10>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalCal/BSER_CellBalInitCal'
 * '<S11>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalCal/BSER_CellBalSeqChart'
 * '<S12>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalCal/BSER_CellBalSortCal'
 * '<S13>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalCal/BSER_CellBalWaitCal'
 * '<S14>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalCal/BSER_CellBalSortCal/BSER_CellBalSort'
 * '<S15>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalCal/BSER_CellBalSortCal/Hysteresis'
 * '<S16>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalCal/BSER_CellBalSortCal/Hysteresis1'
 * '<S17>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalEnaCal/BSER_CellBalACModeCal'
 * '<S18>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalEnaCal/BSER_CellBalDCModeCal'
 * '<S19>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalEnaCal/BSER_CellBalDrvInteEnaCal'
 * '<S20>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalEnaCal/BSER_CellBalTempEnaCal'
 * '<S21>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalEnaCal/BSER_CellBalUDSEnaCal'
 * '<S22>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalEnaCal/BSER_CellBalVoltEnaCal'
 * '<S23>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalEnaCal/BSER_CellBalWkEnaCal'
 * '<S24>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalEnaCal/BSER_FaultLvlEnaCal'
 * '<S25>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalEnaCal/BSER_CellBalDrvInteEnaCal/BSER_BalInteChgTimeExsCal'
 * '<S26>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalEnaCal/BSER_CellBalDrvInteEnaCal/BSER_CellBalDrvInteEnaConCal'
 * '<S27>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalEnaCal/BSER_CellBalDrvInteEnaCal/Chart'
 * '<S28>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalEnaCal/BSER_CellBalDrvInteEnaCal/BSER_CellBalDrvInteEnaConCal/EdgeRising'
 * '<S29>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalEnaCal/BSER_CellBalDrvInteEnaCal/BSER_CellBalDrvInteEnaConCal/TONV_VariableTimeDebounce'
 * '<S30>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalEnaCal/BSER_CellBalTempEnaCal/TONV_VariableTimeDebounce'
 * '<S31>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalEnaCal/BSER_CellBalTempEnaCal/TONV_VariableTimeDebounce1'
 * '<S32>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalEnaCal/BSER_CellBalVoltEnaCal/TONV_VariableTimeDebounce'
 * '<S33>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalEnaCal/BSER_CellBalVoltEnaCal/TONV_VariableTimeDebounce1'
 * '<S34>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CellBalEnaCal/BSER_CellBalVoltEnaCal/TONV_VariableTimeDebounce2'
 * '<S35>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero1'
 * '<S36>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero2'
 * '<S37>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/Compare To Constant'
 * '<S38>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/Compare To Constant1'
 * '<S39>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck'
 * '<S40>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck1'
 * '<S41>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck2'
 * '<S42>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck3'
 * '<S43>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/Hysteresis'
 * '<S44>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/Hysteresis1'
 * '<S45>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/Hysteresis2'
 * '<S46>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/Hysteresis3'
 * '<S47>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero1/Compare To Zero'
 * '<S48>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero1/FaultProcess'
 * '<S49>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero1/HealProcess'
 * '<S50>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero1/FaultProcess/Decrease'
 * '<S51>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero1/FaultProcess/Increase'
 * '<S52>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero1/FaultProcess/Decrease/Nomal'
 * '<S53>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero1/HealProcess/Compare To Zero'
 * '<S54>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero1/HealProcess/Decrease'
 * '<S55>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero1/HealProcess/Increase'
 * '<S56>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero1/HealProcess/Decrease/Nomal'
 * '<S57>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero2/Compare To Zero'
 * '<S58>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero2/FaultProcess'
 * '<S59>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero2/HealProcess'
 * '<S60>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero2/FaultProcess/Decrease'
 * '<S61>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero2/FaultProcess/Increase'
 * '<S62>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero2/FaultProcess/Decrease/Nomal'
 * '<S63>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero2/HealProcess/Compare To Zero'
 * '<S64>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero2/HealProcess/Decrease'
 * '<S65>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero2/HealProcess/Increase'
 * '<S66>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/CBCBMSDebounceStartZero2/HealProcess/Decrease/Nomal'
 * '<S67>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck/Bit Clear1'
 * '<S68>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck/Bit Clear2'
 * '<S69>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck/Bit Set'
 * '<S70>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck/Bit Set1'
 * '<S71>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck/Bit Set2'
 * '<S72>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck/Bit Set4'
 * '<S73>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck1/Bit Clear1'
 * '<S74>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck1/Bit Clear2'
 * '<S75>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck1/Bit Set'
 * '<S76>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck1/Bit Set1'
 * '<S77>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck1/Bit Set2'
 * '<S78>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck1/Bit Set4'
 * '<S79>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck2/Bit Clear1'
 * '<S80>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck2/Bit Clear2'
 * '<S81>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck2/Bit Set'
 * '<S82>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck2/Bit Set1'
 * '<S83>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck2/Bit Set2'
 * '<S84>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck2/Bit Set4'
 * '<S85>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck3/Bit Clear1'
 * '<S86>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck3/Bit Clear2'
 * '<S87>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck3/Bit Set'
 * '<S88>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck3/Bit Set1'
 * '<S89>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck3/Bit Set2'
 * '<S90>'  : 'BSER_CellBalcCtl/BSER_CellBalCtl/BSER_CellBalCtlCal/BSER_CmuBalEnaCal/DSM_ReportCheck3/Bit Set4'
 * '<S91>'  : 'BSER_CellBalcCtl/SigProc/DimConvert'
 * '<S92>'  : 'BSER_CellBalcCtl/SigProc/Subsystem'
 * '<S93>'  : 'BSER_CellBalcCtl/SigProc/Subsystem/K_Lowpass1'
 */
#endif                                 /* RTW_HEADER_BSER_CellBalcCtl_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
