/*
 * File: BSPR_DChrgTempSnsrDiag.h
 *
 * Code generated for Simulink model 'BSPR_DChrgTempSnsrDiag'.
 *
 * Model version                  : 1.108F
 * Simulink Coder version         : 8.11F (R2016b) 25-Aug-2016
 * C/C++ source code generated on : Wed Dec 19 17:21:13 2018
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#ifndef RTW_HEADER_BSPR_DChrgTempSnsrDiag_h_
#define RTW_HEADER_BSPR_DChrgTempSnsrDiag_h_
#include <math.h>
#include <stddef.h>
#ifndef BSPR_DChrgTempSnsrDiag_COMMON_INCLUDES_
# define BSPR_DChrgTempSnsrDiag_COMMON_INCLUDES_
#include "rtwtypes.h"
#endif                                 /* BSPR_DChrgTempSnsrDiag_COMMON_INCLUDES_ */

#include "BSPR_DChrgTempSnsrDiag_types.h"

/* Includes for objects with custom storage classes. */
#include "BSPR_DChrgTempSnsrDiag_parameters.h"

/* Macros for accessing real-time model data structure */

/* user code (top of header file) */
#include "ASW_Interface.h"

/* Block states (auto storage) for system '<Root>' */
typedef struct {
  real32_T Delay_DSTATE;               /* '<S30>/Delay' */
  real32_T Delay_DSTATE_c;             /* '<S29>/Delay' */
  real32_T Delay_DSTATE_j;             /* '<S16>/Delay' */
  real32_T Delay_DSTATE_e;             /* '<S15>/Delay' */
  real32_T Delay_DSTATE_d;             /* '<S14>/Delay' */
  real32_T Delay_DSTATE_p;             /* '<S13>/Delay' */
  real32_T Delay_DSTATE_f;             /* '<S12>/Delay' */
  real32_T Delay_DSTATE_l;             /* '<S11>/Delay' */
  real32_T Delay_DSTATE_n;             /* '<S10>/Delay' */
  real32_T Delay_DSTATE_i;             /* '<S9>/Delay' */
  real32_T Delay_DSTATE_c4;            /* '<S8>/Delay' */
  real32_T Delay_DSTATE_o;             /* '<S7>/Delay' */
  real32_T Delay_DSTATE_m;             /* '<S6>/Delay' */
  real32_T Delay_DSTATE_l5;            /* '<S5>/Delay' */
  uint8_T Delay3_DSTATE;               /* '<S28>/Delay3' */
  uint8_T Delay3_DSTATE_n;             /* '<S27>/Delay3' */
  uint8_T Delay3_DSTATE_j;             /* '<S26>/Delay3' */
  uint8_T Delay3_DSTATE_k;             /* '<S25>/Delay3' */
  uint8_T Delay3_DSTATE_e;             /* '<S24>/Delay3' */
  uint8_T Delay3_DSTATE_l;             /* '<S23>/Delay3' */
  boolean_T Delay2_DSTATE;             /* '<S28>/Delay2' */
  boolean_T Delay2_DSTATE_c;           /* '<S27>/Delay2' */
  boolean_T Delay2_DSTATE_i;           /* '<S26>/Delay2' */
  boolean_T Delay2_DSTATE_h;           /* '<S25>/Delay2' */
  boolean_T Delay2_DSTATE_n;           /* '<S24>/Delay2' */
  boolean_T Delay2_DSTATE_e;           /* '<S23>/Delay2' */
} DW_BSPR_DChrgTempSnsrDiag_T;

/* Block states (auto storage) */
extern DW_BSPR_DChrgTempSnsrDiag_T BSPR_DChrgTempSnsrDiag_DW;

/* Model entry point functions */
extern void BSPR_DChrgTempSnsrDiag_initialize(void);
extern void BSPR_DChrgTempSnsrDiag_step(void);

/* Exported data declaration */

/* Volatile memory section */
 
 

/* Declaration for custom storage class: Volatile */
extern volatile uint8_T DFC_DChrgTNegElecMax_ASW;
extern volatile uint8_T DFC_DChrgTNegElecMin_ASW;
extern volatile uint8_T DFC_DChrgTNegElecSig_ASW;
extern volatile uint8_T DFC_DChrgTPosElecMax_ASW;
extern volatile uint8_T DFC_DChrgTPosElecMin_ASW;
extern volatile uint8_T DFC_DChrgTPosElecSig_ASW;

 
 

/* Declaration for custom storage class: OutputSignal */
extern volatile boolean_T BSPR_bDChrgNegTempVld;
extern volatile boolean_T BSPR_bDChrgPosTempVld;
extern volatile boolean_T BSPR_bDChrgTNegJitErrDet;
extern volatile boolean_T BSPR_bDChrgTNegJitErrHeal;
extern volatile boolean_T BSPR_bDChrgTNegJitErrStt;
extern volatile boolean_T BSPR_bDChrgTNegMaxErrDet;
extern volatile boolean_T BSPR_bDChrgTNegMaxErrHeal;
extern volatile boolean_T BSPR_bDChrgTNegMaxErrStt;
extern volatile boolean_T BSPR_bDChrgTNegMinErrDet;
extern volatile boolean_T BSPR_bDChrgTNegMinErrHeal;
extern volatile boolean_T BSPR_bDChrgTNegMinErrStt;
extern volatile boolean_T BSPR_bDChrgTPosJitErrDet;
extern volatile boolean_T BSPR_bDChrgTPosJitErrHeal;
extern volatile boolean_T BSPR_bDChrgTPosJitErrStt;
extern volatile boolean_T BSPR_bDChrgTPosMaxErrDet;
extern volatile boolean_T BSPR_bDChrgTPosMaxErrHeal;
extern volatile boolean_T BSPR_bDChrgTPosMaxErrStt;
extern volatile boolean_T BSPR_bDChrgTPosMinErrDet;
extern volatile boolean_T BSPR_bDChrgTPosMinErrHeal;
extern volatile boolean_T BSPR_bDChrgTPosMinErrStt;

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'BSPR_DChrgTempSnsrDiag'
 * '<S1>'   : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag'
 * '<S2>'   : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTNegErrChk'
 * '<S3>'   : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTPosErrChk'
 * '<S4>'   : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt'
 * '<S5>'   : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTNegErrChk/TONV_100msTimeDebounce'
 * '<S6>'   : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTNegErrChk/TONV_100msTimeDebounce1'
 * '<S7>'   : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTNegErrChk/TONV_100msTimeDebounce2'
 * '<S8>'   : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTNegErrChk/TONV_100msTimeDebounce3'
 * '<S9>'   : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTNegErrChk/TONV_100msTimeDebounce4'
 * '<S10>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTNegErrChk/TONV_100msTimeDebounce5'
 * '<S11>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTPosErrChk/TONV_100msTimeDebounce'
 * '<S12>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTPosErrChk/TONV_100msTimeDebounce1'
 * '<S13>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTPosErrChk/TONV_100msTimeDebounce2'
 * '<S14>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTPosErrChk/TONV_100msTimeDebounce3'
 * '<S15>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTPosErrChk/TONV_100msTimeDebounce4'
 * '<S16>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTPosErrChk/TONV_100msTimeDebounce5'
 * '<S17>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/Compare To Constant'
 * '<S18>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/Compare To Constant1'
 * '<S19>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/Compare To Constant2'
 * '<S20>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/Compare To Constant3'
 * '<S21>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/Compare To Constant4'
 * '<S22>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/Compare To Constant5'
 * '<S23>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck'
 * '<S24>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck1'
 * '<S25>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck2'
 * '<S26>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck3'
 * '<S27>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck4'
 * '<S28>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck5'
 * '<S29>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/TONV_100msTimeDebounce'
 * '<S30>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/TONV_100msTimeDebounce1'
 * '<S31>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck/Bit Clear1'
 * '<S32>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck/Bit Clear2'
 * '<S33>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck/Bit Set'
 * '<S34>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck/Bit Set1'
 * '<S35>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck/Bit Set2'
 * '<S36>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck/Bit Set4'
 * '<S37>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck1/Bit Clear1'
 * '<S38>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck1/Bit Clear2'
 * '<S39>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck1/Bit Set'
 * '<S40>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck1/Bit Set1'
 * '<S41>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck1/Bit Set2'
 * '<S42>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck1/Bit Set4'
 * '<S43>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck2/Bit Clear1'
 * '<S44>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck2/Bit Clear2'
 * '<S45>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck2/Bit Set'
 * '<S46>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck2/Bit Set1'
 * '<S47>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck2/Bit Set2'
 * '<S48>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck2/Bit Set4'
 * '<S49>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck3/Bit Clear1'
 * '<S50>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck3/Bit Clear2'
 * '<S51>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck3/Bit Set'
 * '<S52>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck3/Bit Set1'
 * '<S53>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck3/Bit Set2'
 * '<S54>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck3/Bit Set4'
 * '<S55>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck4/Bit Clear1'
 * '<S56>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck4/Bit Clear2'
 * '<S57>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck4/Bit Set'
 * '<S58>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck4/Bit Set1'
 * '<S59>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck4/Bit Set2'
 * '<S60>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck4/Bit Set4'
 * '<S61>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck5/Bit Clear1'
 * '<S62>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck5/Bit Clear2'
 * '<S63>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck5/Bit Set'
 * '<S64>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck5/Bit Set1'
 * '<S65>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck5/Bit Set2'
 * '<S66>'  : 'BSPR_DChrgTempSnsrDiag/BSPR_DChrgTempSnsrDiag/DChrgTempDsmRpt/DSM_ReportCheck5/Bit Set4'
 */
#endif                                 /* RTW_HEADER_BSPR_DChrgTempSnsrDiag_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
