/*
 * File: BSPR_ThmTempSnsrDiag.h
 *
 * Code generated for Simulink model 'BSPR_ThmTempSnsrDiag'.
 *
 * Model version                  : 1.200
 * Simulink Coder version         : 8.13 (R2017b) 24-Jul-2017
 * C/C++ source code generated on : Fri Oct  9 10:59:38 2020
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#ifndef RTW_HEADER_BSPR_ThmTempSnsrDiag_h_
#define RTW_HEADER_BSPR_ThmTempSnsrDiag_h_
#include <math.h>
#ifndef BSPR_ThmTempSnsrDiag_COMMON_INCLUDES_
# define BSPR_ThmTempSnsrDiag_COMMON_INCLUDES_
#include "rtwtypes.h"
#endif                                 /* BSPR_ThmTempSnsrDiag_COMMON_INCLUDES_ */

#include "BSPR_ThmTempSnsrDiag_types.h"

/* Includes for objects with custom storage classes. */
#include "BSPR_ThmTempSnsrDiag_parameters.h"

/* Macros for accessing real-time model data structure */

/* user code (top of header file) */
#include "ASW_Interface.h"

/* Block states (auto storage) for system '<Root>' */
typedef struct {
  real32_T Delay_DSTATE;               /* '<S86>/Delay' */
  real32_T Delay_DSTATE_l;             /* '<S85>/Delay' */
  real32_T Delay_DSTATE_j;             /* '<S84>/Delay' */
  real32_T Delay_DSTATE_e;             /* '<S83>/Delay' */
  real32_T Delay_DSTATE_d;             /* '<S82>/Delay' */
  real32_T Delay_DSTATE_p;             /* '<S81>/Delay' */
  real32_T Delay_DSTATE_f;             /* '<S80>/Delay' */
  real32_T Delay_DSTATE_l2;            /* '<S79>/Delay' */
  real32_T Delay_DSTATE_l2d;           /* '<S30>/Delay' */
  real32_T Delay_DSTATE_c;             /* '<S29>/Delay' */
  real32_T Delay_DSTATE_ds;            /* '<S12>/Delay' */
  real32_T Delay_DSTATE_dy;            /* '<S11>/Delay' */
  real32_T Delay_DSTATE_n;             /* '<S10>/Delay' */
  real32_T Delay_DSTATE_i;             /* '<S9>/Delay' */
  real32_T Delay_DSTATE_c4;            /* '<S8>/Delay' */
  real32_T Delay_DSTATE_o;             /* '<S7>/Delay' */
  real32_T Delay_DSTATE_m;             /* '<S6>/Delay' */
  real32_T Delay_DSTATE_l5;            /* '<S5>/Delay' */
  uint8_T Delay3_DSTATE;               /* '<S28>/Delay3' */
  uint8_T Delay3_DSTATE_n;             /* '<S27>/Delay3' */
  uint8_T Delay3_DSTATE_b;             /* '<S26>/Delay3' */
  uint8_T Delay3_DSTATE_nv;            /* '<S25>/Delay3' */
  uint8_T Delay3_DSTATE_j;             /* '<S24>/Delay3' */
  uint8_T Delay3_DSTATE_k;             /* '<S23>/Delay3' */
  uint8_T Delay3_DSTATE_e;             /* '<S22>/Delay3' */
  uint8_T Delay3_DSTATE_l;             /* '<S21>/Delay3' */
  boolean_T Delay2_DSTATE;             /* '<S28>/Delay2' */
  boolean_T Delay2_DSTATE_d;           /* '<S27>/Delay2' */
  boolean_T Delay2_DSTATE_g;           /* '<S26>/Delay2' */
  boolean_T Delay2_DSTATE_c;           /* '<S25>/Delay2' */
  boolean_T Delay2_DSTATE_i;           /* '<S24>/Delay2' */
  boolean_T Delay2_DSTATE_h;           /* '<S23>/Delay2' */
  boolean_T Delay2_DSTATE_n;           /* '<S22>/Delay2' */
  boolean_T Delay2_DSTATE_e;           /* '<S21>/Delay2' */
} DW_BSPR_ThmTempSnsrDiag_T;

/* Block states (auto storage) */
extern DW_BSPR_ThmTempSnsrDiag_T BSPR_ThmTempSnsrDiag_DW;

/* Model entry point functions */
extern void BSPR_ThmTempSnsrDiag_initialize(void);
extern void BSPR_ThmTempSnsrDiag_step(void);

/* Exported data declaration */

/* Volatile memory section */
#define ASW1_OEM_START_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: Volatile */
extern volatile uint8_T DFC_ClntDsTElecMax_ASW;/* Max fault of coolant inlet temperature sensor */
extern volatile uint8_T DFC_ClntDsTElecMin_ASW;/* Min fault of coolant inlet temperature sensor */
extern volatile uint8_T DFC_ClntDsTElecSig_ASW;/* Sig fault of coolant inlet temperature sensor */
extern volatile uint8_T DFC_ClntUsTElecMax_ASW;/* Max fault of coolant outlet temperature sensor */
extern volatile uint8_T DFC_ClntUsTElecMin_ASW;/* Min fault of coolant outlet temperature sensor */
extern volatile uint8_T DFC_ClntUsTElecSig_ASW;/* Sig fault of coolant outlet temperature sensor */
extern volatile uint8_T DFC_InClntOverTmp_ASW;/* Inlet coolant temperature high */
extern volatile uint8_T DFC_OutClntOverTmp_ASW;/* Outlet coolant temperature high */

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"
#define ASW1_OEM_START_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: OutputSignal */
extern volatile boolean_T BSPR_bClntDsTJitErrDet;
extern volatile boolean_T BSPR_bClntDsTJitErrHeal;
extern volatile boolean_T BSPR_bClntDsTJitErrStt;
extern volatile boolean_T BSPR_bClntDsTMaxErrDet;
extern volatile boolean_T BSPR_bClntDsTMaxErrHeal;
extern volatile boolean_T BSPR_bClntDsTMaxErrStt;
extern volatile boolean_T BSPR_bClntDsTMinErrDet;
extern volatile boolean_T BSPR_bClntDsTMinErrHeal;
extern volatile boolean_T BSPR_bClntDsTMinErrStt;
extern volatile boolean_T BSPR_bClntDsTOTErrDet;
extern volatile boolean_T BSPR_bClntDsTOTErrHeal;
extern volatile boolean_T BSPR_bClntDsTVld;
extern volatile boolean_T BSPR_bClntUsTJitErrDet;
extern volatile boolean_T BSPR_bClntUsTJitErrHeal;
extern volatile boolean_T BSPR_bClntUsTJitErrStt;
extern volatile boolean_T BSPR_bClntUsTMaxErrDet;
extern volatile boolean_T BSPR_bClntUsTMaxErrHeal;
extern volatile boolean_T BSPR_bClntUsTMaxErrStt;
extern volatile boolean_T BSPR_bClntUsTMinErrDet;
extern volatile boolean_T BSPR_bClntUsTMinErrHeal;
extern volatile boolean_T BSPR_bClntUsTMinErrStt;
extern volatile boolean_T BSPR_bClntUsTOTErrDet;
extern volatile boolean_T BSPR_bClntUsTOTErrHeal;
extern volatile boolean_T BSPR_bClntUsTVld;

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'BSPR_ThmTempSnsrDiag'
 * '<S1>'   : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag'
 * '<S2>'   : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntDsTErrChk'
 * '<S3>'   : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt'
 * '<S4>'   : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntUsTErrChk'
 * '<S5>'   : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntDsTErrChk/TONV_100msTimeDebounce'
 * '<S6>'   : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntDsTErrChk/TONV_100msTimeDebounce1'
 * '<S7>'   : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntDsTErrChk/TONV_100msTimeDebounce2'
 * '<S8>'   : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntDsTErrChk/TONV_100msTimeDebounce3'
 * '<S9>'   : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntDsTErrChk/TONV_100msTimeDebounce4'
 * '<S10>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntDsTErrChk/TONV_100msTimeDebounce5'
 * '<S11>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntDsTErrChk/TONV_100msTimeDebounce6'
 * '<S12>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntDsTErrChk/TONV_100msTimeDebounce7'
 * '<S13>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/Compare To Constant'
 * '<S14>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/Compare To Constant1'
 * '<S15>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/Compare To Constant2'
 * '<S16>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/Compare To Constant3'
 * '<S17>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/Compare To Constant4'
 * '<S18>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/Compare To Constant5'
 * '<S19>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/Compare To Constant6'
 * '<S20>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/Compare To Constant7'
 * '<S21>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck'
 * '<S22>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck1'
 * '<S23>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck2'
 * '<S24>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck3'
 * '<S25>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck4'
 * '<S26>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck5'
 * '<S27>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck6'
 * '<S28>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck7'
 * '<S29>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/TONV_100msTimeDebounce'
 * '<S30>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/TONV_100msTimeDebounce1'
 * '<S31>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck/Bit Clear1'
 * '<S32>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck/Bit Clear2'
 * '<S33>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck/Bit Set'
 * '<S34>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck/Bit Set1'
 * '<S35>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck/Bit Set2'
 * '<S36>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck/Bit Set4'
 * '<S37>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck1/Bit Clear1'
 * '<S38>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck1/Bit Clear2'
 * '<S39>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck1/Bit Set'
 * '<S40>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck1/Bit Set1'
 * '<S41>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck1/Bit Set2'
 * '<S42>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck1/Bit Set4'
 * '<S43>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck2/Bit Clear1'
 * '<S44>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck2/Bit Clear2'
 * '<S45>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck2/Bit Set'
 * '<S46>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck2/Bit Set1'
 * '<S47>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck2/Bit Set2'
 * '<S48>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck2/Bit Set4'
 * '<S49>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck3/Bit Clear1'
 * '<S50>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck3/Bit Clear2'
 * '<S51>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck3/Bit Set'
 * '<S52>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck3/Bit Set1'
 * '<S53>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck3/Bit Set2'
 * '<S54>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck3/Bit Set4'
 * '<S55>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck4/Bit Clear1'
 * '<S56>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck4/Bit Clear2'
 * '<S57>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck4/Bit Set'
 * '<S58>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck4/Bit Set1'
 * '<S59>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck4/Bit Set2'
 * '<S60>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck4/Bit Set4'
 * '<S61>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck5/Bit Clear1'
 * '<S62>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck5/Bit Clear2'
 * '<S63>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck5/Bit Set'
 * '<S64>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck5/Bit Set1'
 * '<S65>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck5/Bit Set2'
 * '<S66>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck5/Bit Set4'
 * '<S67>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck6/Bit Clear1'
 * '<S68>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck6/Bit Clear2'
 * '<S69>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck6/Bit Set'
 * '<S70>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck6/Bit Set1'
 * '<S71>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck6/Bit Set2'
 * '<S72>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck6/Bit Set4'
 * '<S73>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck7/Bit Clear1'
 * '<S74>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck7/Bit Clear2'
 * '<S75>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck7/Bit Set'
 * '<S76>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck7/Bit Set1'
 * '<S77>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck7/Bit Set2'
 * '<S78>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntTempDsmRpt/DSM_ReportCheck7/Bit Set4'
 * '<S79>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntUsTErrChk/TONV_100msTimeDebounce'
 * '<S80>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntUsTErrChk/TONV_100msTimeDebounce1'
 * '<S81>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntUsTErrChk/TONV_100msTimeDebounce2'
 * '<S82>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntUsTErrChk/TONV_100msTimeDebounce3'
 * '<S83>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntUsTErrChk/TONV_100msTimeDebounce4'
 * '<S84>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntUsTErrChk/TONV_100msTimeDebounce5'
 * '<S85>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntUsTErrChk/TONV_100msTimeDebounce6'
 * '<S86>'  : 'BSPR_ThmTempSnsrDiag/BSPR_ThmTempSnsrDiag/CIntUsTErrChk/TONV_100msTimeDebounce7'
 */
#endif                                 /* RTW_HEADER_BSPR_ThmTempSnsrDiag_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
