/*
 * File: BSPR_RTE_parameters.c
 *
 * Code generated for Simulink model 'BSPR_RTE'.
 *
 * Model version                  : A1.0_0
 * Simulink Coder version         : 8.11 (R2016b) 25-Aug-2016
 * C/C++ source code generated on : Tue Nov 10 16:47:36 2020
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#include "rtwtypes.h"
#include "BSPR_RTE_types.h"

/* Exported data definition */
#define ASW1_OEM_START_SEC_DEFAULT_CALIB_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Definition for custom storage class: Const */
const volatile boolean_T RTE_bDchrgDiagStdSel_C = 0U;
const volatile real32_T RTE_tiBase_C = 0.01F;
const volatile real32_T RTE_tiDebs_C = 0.1F;
const volatile real32_T RTE_uDCWkUpLow_C = 4000.0F;
const volatile real32_T RTE_uDCWkUpUp_C = 6000.0F;

#define ASW1_OEM_STOP_SEC_DEFAULT_CALIB_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
