/*
 * File: BCMR_DChrgTiRem.h
 *
 * Code generated for Simulink model 'BCMR_DChrgTiRem'.
 *
 * Model version                  : 1.645
 * Simulink Coder version         : 8.11 (R2016b) 25-Aug-2016
 * C/C++ source code generated on : Sun Feb 28 20:48:46 2021
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#ifndef RTW_HEADER_BCMR_DChrgTiRem_h_
#define RTW_HEADER_BCMR_DChrgTiRem_h_
#include <math.h>
#include <stddef.h>
#ifndef BCMR_DChrgTiRem_COMMON_INCLUDES_
# define BCMR_DChrgTiRem_COMMON_INCLUDES_
#include "rtwtypes.h"
#endif                                 /* BCMR_DChrgTiRem_COMMON_INCLUDES_ */

#include "BCMR_DChrgTiRem_types.h"

/* Includes for objects with custom storage classes. */
#include "dchrg_remt_parameters.h"
#include "intrp2d_fu32fla_pw.h"
#include "look1_iflf_binlcapw.h"
#include "plook_u32ff_binca.h"

/* Macros for accessing real-time model data structure */

/* user code (top of header file) */
#include "ASW_Interface.h"

/* Block signals for system '<S14>/ParaStep' */
typedef struct {
  uint8_T ParaStep;                    /* '<S14>/ParaStep' */
} B_ParaStep_BCMR_DChrgTiRem_T;

/* Block states (auto storage) for system '<S14>/ParaStep' */
typedef struct {
  uint8_T is_active_c3_BCMR_DChrgTiRem;/* '<S14>/ParaStep' */
  uint8_T is_c3_BCMR_DChrgTiRem;       /* '<S14>/ParaStep' */
} DW_ParaStep_BCMR_DChrgTiRem_T;

/* Block signals for system '<S15>/ParaStep2' */
typedef struct {
  uint8_T ParaStep;                    /* '<S15>/ParaStep2' */
} B_ParaStep2_BCMR_DChrgTiRem_T;

/* Block states (auto storage) for system '<S15>/ParaStep2' */
typedef struct {
  uint8_T is_active_c2_BCMR_DChrgTiRem;/* '<S15>/ParaStep2' */
  uint8_T is_c2_BCMR_DChrgTiRem;       /* '<S15>/ParaStep2' */
} DW_ParaStep2_BCMR_DChrgTiRem_T;

/* Block signals (auto storage) */
typedef struct {
  real32_T Switch2;                    /* '<S11>/Switch2' */
  B_ParaStep2_BCMR_DChrgTiRem_T sf_ParaStep2;/* '<S15>/ParaStep2' */
  B_ParaStep_BCMR_DChrgTiRem_T sf_ParaStep;/* '<S14>/ParaStep' */
} B_BCMR_DChrgTiRem_T;

/* Block states (auto storage) for system '<Root>' */
typedef struct {
  real32_T Delay_DSTATE;                 /* '<S31>/Delay' */
  real32_T Delay_DSTATE_e;               /* '<S30>/Delay' */
  real32_T UnitDelay_DSTATE;           /* '<S11>/Unit Delay' */
  real32_T Delay2_DSTATE;              /* '<S36>/Delay2' */
  real32_T Delay1_DSTATE;              /* '<S32>/Delay1' */
  real32_T UnitDelay2_DSTATE;          /* '<S11>/Unit Delay2' */
  real32_T UnitDelay1_DSTATE;          /* '<S11>/Unit Delay1' */
  real32_T Delay2_DSTATE_l;            /* '<S34>/Delay2' */
  real32_T Delay_DSTATE_c;             /* '<S33>/Delay' */
  real32_T UnitDelay3_DSTATE;          /* '<S11>/Unit Delay3' */
  real32_T Delay2_DSTATE_n;            /* '<S35>/Delay2' */
  real32_T Delay_DSTATE_ec;            /* '<S37>/Delay' */
  real32_T Delay_DSTATE_et;            /* '<S43>/Delay' */
  real32_T Delay_DSTATE_f;             /* '<S42>/Delay' */
  real32_T UnitDelay_DSTATE_e;         /* '<S31>/Unit Delay' */
  real32_T UnitDelay_DSTATE_n;         /* '<S30>/Unit Delay' */
  real32_T Delay1_DSTATE_d[2];         /* '<S16>/Delay1' */
  real32_T Delay_DSTATE_cx[2];         /* '<S22>/Delay' */
  real32_T PackCurNow;                 /* '<S13>/TiRvsCalc' */
  uint16_T Time;                       /* '<S13>/TiRvsCalc' */
  boolean_T UnitDelay1_DSTATE_l;       /* '<S32>/Unit Delay1' */
  boolean_T Delay1_DSTATE_p;           /* '<S33>/Delay1' */
  boolean_T UnitDelay1_DSTATE_j;       /* '<S16>/Unit Delay1' */
  uint8_T is_active_c1_BCMR_DChrgTiRem;/* '<S13>/TiRvsCalc' */
  uint8_T is_c1_BCMR_DChrgTiRem;       /* '<S13>/TiRvsCalc' */
  uint8_T is_end;                      /* '<S13>/TiRvsCalc' */
  uint8_T Rx;                          /* '<S13>/TiRvsCalc' */
  uint8_T temporalCounter_i1;          /* '<S13>/TiRvsCalc' */
  boolean_T DcRemTime_MODE;            /* '<S1>/DcRemTime' */
  boolean_T RemChgTimeCalc_MODE;       /* '<S5>/RemChgTimeCalc' */
  DW_ParaStep2_BCMR_DChrgTiRem_T sf_ParaStep2;/* '<S15>/ParaStep2' */
  DW_ParaStep_BCMR_DChrgTiRem_T sf_ParaStep;/* '<S14>/ParaStep' */
} DW_BCMR_DChrgTiRem_T;

/* Block signals (auto storage) */
extern B_BCMR_DChrgTiRem_T BCMR_DChrgTiRem_B;

/* Block states (auto storage) */
extern DW_BCMR_DChrgTiRem_T BCMR_DChrgTiRem_DW;

/* Model entry point functions */
extern void BCMR_DChrgTiRem_initialize(void);
extern void BCMR_DChrgTiRem_step(void);

/* Exported data declaration */
#define ASW1_OEM_START_SEC_DEFAULT_RAM1_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: OutputSignal */
extern volatile uint8_T BCMR_RemTimeState;
extern volatile uint16_T BCMR_cntCountNum;
extern volatile uint16_T BCMR_cntCounterNum;
extern volatile real32_T BCMR_iCurDChrgOldVal;
extern volatile uint8_T BCMR_rColNum;
extern volatile uint8_T BCMR_rRowNum;
extern volatile real32_T BCMR_rSocStepDiff;
extern volatile real32_T BCMR_rSocStepLong;
extern volatile real32_T BCMR_tiDChrgRemRvs;
extern volatile real32_T BCMR_tiDChrgRemTbl;
extern volatile real32_T BCMR_tiDChrgTiRemCalc;
extern volatile real32_T BCMR_tiRemDChrgTime;
extern volatile real32_T BCMR_tiUnitTimeSub;
extern volatile real32_T BCMR_tiUnitTimeTot;

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM1_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'BCMR_DChrgTiRem'
 * '<S1>'   : 'BCMR_DChrgTiRem/DChrgTiRem'
 * '<S2>'   : 'BCMR_DChrgTiRem/DChrgTiRem/Compare To Constant'
 * '<S3>'   : 'BCMR_DChrgTiRem/DChrgTiRem/Compare To Constant2'
 * '<S4>'   : 'BCMR_DChrgTiRem/DChrgTiRem/Compare To Constant4'
 * '<S5>'   : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime'
 * '<S6>'   : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/Compare To Constant'
 * '<S7>'   : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/Compare To Constant2'
 * '<S8>'   : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/Compare To Constant4'
 * '<S9>'   : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/CurrReqCalc'
 * '<S10>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/CurrTimeRvs'
 * '<S11>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc'
 * '<S12>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/CurrReqCalc/ArrayIndex'
 * '<S13>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/CurrReqCalc/TiRvsCalc'
 * '<S14>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/CurrReqCalc/ArrayIndex/ColNumCalc'
 * '<S15>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/CurrReqCalc/ArrayIndex/RowNumCalc'
 * '<S16>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/CurrReqCalc/ArrayIndex/SIgFil'
 * '<S17>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/CurrReqCalc/ArrayIndex/TiLutVal'
 * '<S18>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/CurrReqCalc/ArrayIndex/ColNumCalc/ParaStep'
 * '<S19>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/CurrReqCalc/ArrayIndex/RowNumCalc/ParaStep2'
 * '<S20>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/CurrReqCalc/ArrayIndex/SIgFil/Filter'
 * '<S21>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/CurrReqCalc/ArrayIndex/SIgFil/Filter/Compare To Constant'
 * '<S22>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/CurrReqCalc/ArrayIndex/SIgFil/Filter/TONV_VariableTimeDebounce'
 * '<S23>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/CurrReqCalc/TiRvsCalc/TiRvsCalc'
 * '<S24>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/Compare To Constant'
 * '<S25>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/Compare To Constant1'
 * '<S26>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/Compare To Constant2'
 * '<S27>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/Compare To Constant3'
 * '<S28>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/Compare To Constant4'
 * '<S29>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/Compare To Constant6'
 * '<S30>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/K_Lowpass1'
 * '<S31>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/K_Lowpass3'
 * '<S32>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/SIgFil1'
 * '<S33>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/Subsystem1'
 * '<S34>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/Subsystem2'
 * '<S35>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/Subsystem3'
 * '<S36>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/Subsystem4'
 * '<S37>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/TONV_VariableTimeDebounce'
 * '<S38>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/zeroGuardDivide'
 * '<S39>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/SIgFil1/Filter'
 * '<S40>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/SIgFil1/Filter/Compare To Constant'
 * '<S41>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/SIgFil1/Filter/Compare To Constant1'
 * '<S42>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/SIgFil1/Filter/TONV_VariableTimeDebounce'
 * '<S43>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/SIgFil1/Filter/TONV_VariableTimeDebounce1'
 * '<S44>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/Subsystem2/Compare To Constant1'
 * '<S45>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/Subsystem3/Compare To Constant1'
 * '<S46>'  : 'BCMR_DChrgTiRem/DChrgTiRem/DcRemTime/RemChgTimeCalc/Subsystem4/Compare To Constant1'
 */
#endif                                 /* RTW_HEADER_BCMR_DChrgTiRem_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
