/*
 * File: BCMR_DChrgTiRem_types.h
 *
 * Code generated for Simulink model 'BCMR_DChrgTiRem'.
 *
 * Model version                  : 1.645
 * Simulink Coder version         : 8.11 (R2016b) 25-Aug-2016
 * C/C++ source code generated on : Sun Feb 28 20:48:46 2021
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#ifndef RTW_HEADER_BCMR_DChrgTiRem_types_h_
#define RTW_HEADER_BCMR_DChrgTiRem_types_h_
#endif                                 /* RTW_HEADER_BCMR_DChrgTiRem_types_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
