/*
 * File: COMR_BusOff.h
 *
 * Code generated for Simulink model 'COMR_BusOff'.
 *
 * Model version                  : A1.0_0
 * Simulink Coder version         : 8.11 (R2016b) 25-Aug-2016
 * C/C++ source code generated on : Mon Dec 07 10:53:38 2020
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#ifndef RTW_HEADER_COMR_BusOff_h_
#define RTW_HEADER_COMR_BusOff_h_
#include <math.h>
#include <stddef.h>
#ifndef COMR_BusOff_COMMON_INCLUDES_
# define COMR_BusOff_COMMON_INCLUDES_
#include "rtwtypes.h"
#endif                                 /* COMR_BusOff_COMMON_INCLUDES_ */

#include "COMR_BusOff_types.h"

/* Includes for objects with custom storage classes. */
#include "COMR_BusOff_parameters.h"

/* Macros for accessing real-time model data structure */

/* user code (top of header file) */
#include "ASW_Interface.h"

/* Block states (auto storage) for system '<Root>' */
typedef struct {
  real32_T Delay_DSTATE;               /* '<S30>/Delay' */
  real32_T Delay_DSTATE_f;             /* '<S29>/Delay' */
  real32_T Delay_DSTATE_h;             /* '<S21>/Delay' */
  real32_T Delay_DSTATE_j;             /* '<S20>/Delay' */
  real32_T Delay_DSTATE_fk;            /* '<S18>/Delay' */
  real32_T Delay_DSTATE_l;             /* '<S11>/Delay' */
  real32_T Delay_DSTATE_jx;            /* '<S10>/Delay' */
  uint8_T Delay3_DSTATE;               /* '<S28>/Delay3' */
  uint8_T Delay3_DSTATE_o;             /* '<S19>/Delay3' */
  uint8_T Delay3_DSTATE_n;             /* '<S9>/Delay3' */
  boolean_T Delay2_DSTATE;             /* '<S28>/Delay2' */
  boolean_T Delay2_DSTATE_e;           /* '<S19>/Delay2' */
  boolean_T Delay2_DSTATE_d;           /* '<S9>/Delay2' */
  boolean_T InCan_MODE;                /* '<S1>/InCan' */
  boolean_T VeCan_MODE;                /* '<S1>/VeCan' */
  boolean_T DcCan_MODE;                /* '<S1>/DcCan' */
} DW_COMR_BusOff_T;

/* Block states (auto storage) */
extern DW_COMR_BusOff_T COMR_BusOff_DW;

/* Model entry point functions */
extern void COMR_BusOff_initialize(void);
extern void COMR_BusOff_step(void);

/* Exported data declaration */

/* Volatile memory section */
#define ASW1_OEM_START_SEC_DEFAULT_RAM1_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: Volatile */
extern volatile uint8_T DFC_DcCanBusOff_ASW;
extern volatile uint8_T DFC_InCanBusOff_ASW;
extern volatile uint8_T DFC_VeCanBusOff_ASW;

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM1_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"
#define ASW1_OEM_START_SEC_DEFAULT_RAM1_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: OutputSignal */
extern volatile boolean_T COMR_bDChrgCanBusoffDet;
extern volatile boolean_T COMR_bDChrgCanBusoffHeal;
extern volatile boolean_T COMR_bEvCanBusoffDet;
extern volatile boolean_T COMR_bEvCanBusoffHeal;
extern volatile boolean_T COMR_bInCanBusoffDet;
extern volatile boolean_T COMR_bInCanBusoffHeal;

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM1_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'COMR_BusOff'
 * '<S1>'   : 'COMR_BusOff/COMR_BusOff'
 * '<S2>'   : 'COMR_BusOff/COMR_BusOff/DcCan'
 * '<S3>'   : 'COMR_BusOff/COMR_BusOff/EnCond'
 * '<S4>'   : 'COMR_BusOff/COMR_BusOff/InCan'
 * '<S5>'   : 'COMR_BusOff/COMR_BusOff/VeCan'
 * '<S6>'   : 'COMR_BusOff/COMR_BusOff/DcCan/CanOffEn'
 * '<S7>'   : 'COMR_BusOff/COMR_BusOff/DcCan/DcCan'
 * '<S8>'   : 'COMR_BusOff/COMR_BusOff/DcCan/CanOffEn/Compare To Constant'
 * '<S9>'   : 'COMR_BusOff/COMR_BusOff/DcCan/DcCan/DSM_ReportCheck'
 * '<S10>'  : 'COMR_BusOff/COMR_BusOff/DcCan/DcCan/TONV_VariableTimeDebounce'
 * '<S11>'  : 'COMR_BusOff/COMR_BusOff/DcCan/DcCan/TONV_VariableTimeDebounce1'
 * '<S12>'  : 'COMR_BusOff/COMR_BusOff/DcCan/DcCan/DSM_ReportCheck/Bit Clear1'
 * '<S13>'  : 'COMR_BusOff/COMR_BusOff/DcCan/DcCan/DSM_ReportCheck/Bit Clear2'
 * '<S14>'  : 'COMR_BusOff/COMR_BusOff/DcCan/DcCan/DSM_ReportCheck/Bit Set'
 * '<S15>'  : 'COMR_BusOff/COMR_BusOff/DcCan/DcCan/DSM_ReportCheck/Bit Set1'
 * '<S16>'  : 'COMR_BusOff/COMR_BusOff/DcCan/DcCan/DSM_ReportCheck/Bit Set2'
 * '<S17>'  : 'COMR_BusOff/COMR_BusOff/DcCan/DcCan/DSM_ReportCheck/Bit Set4'
 * '<S18>'  : 'COMR_BusOff/COMR_BusOff/EnCond/TONV_VariableTimeDebounce2'
 * '<S19>'  : 'COMR_BusOff/COMR_BusOff/InCan/DSM_ReportCheck1'
 * '<S20>'  : 'COMR_BusOff/COMR_BusOff/InCan/TONV_VariableTimeDebounce1'
 * '<S21>'  : 'COMR_BusOff/COMR_BusOff/InCan/TONV_VariableTimeDebounce2'
 * '<S22>'  : 'COMR_BusOff/COMR_BusOff/InCan/DSM_ReportCheck1/Bit Clear1'
 * '<S23>'  : 'COMR_BusOff/COMR_BusOff/InCan/DSM_ReportCheck1/Bit Clear2'
 * '<S24>'  : 'COMR_BusOff/COMR_BusOff/InCan/DSM_ReportCheck1/Bit Set'
 * '<S25>'  : 'COMR_BusOff/COMR_BusOff/InCan/DSM_ReportCheck1/Bit Set1'
 * '<S26>'  : 'COMR_BusOff/COMR_BusOff/InCan/DSM_ReportCheck1/Bit Set2'
 * '<S27>'  : 'COMR_BusOff/COMR_BusOff/InCan/DSM_ReportCheck1/Bit Set4'
 * '<S28>'  : 'COMR_BusOff/COMR_BusOff/VeCan/DSM_ReportCheck1'
 * '<S29>'  : 'COMR_BusOff/COMR_BusOff/VeCan/TONV_VariableTimeDebounce2'
 * '<S30>'  : 'COMR_BusOff/COMR_BusOff/VeCan/TONV_VariableTimeDebounce3'
 * '<S31>'  : 'COMR_BusOff/COMR_BusOff/VeCan/DSM_ReportCheck1/Bit Clear1'
 * '<S32>'  : 'COMR_BusOff/COMR_BusOff/VeCan/DSM_ReportCheck1/Bit Clear2'
 * '<S33>'  : 'COMR_BusOff/COMR_BusOff/VeCan/DSM_ReportCheck1/Bit Set'
 * '<S34>'  : 'COMR_BusOff/COMR_BusOff/VeCan/DSM_ReportCheck1/Bit Set1'
 * '<S35>'  : 'COMR_BusOff/COMR_BusOff/VeCan/DSM_ReportCheck1/Bit Set2'
 * '<S36>'  : 'COMR_BusOff/COMR_BusOff/VeCan/DSM_ReportCheck1/Bit Set4'
 */
#endif                                 /* RTW_HEADER_COMR_BusOff_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
