/*
 * File: HVSR_CrashChk.h
 *
 * Code generated for Simulink model 'HVSR_CrashChk'.
 *
 * Model version                  : 1.129
 * Simulink Coder version         : 8.13 (R2017b) 24-Jul-2017
 * C/C++ source code generated on : Mon Feb 22 11:19:42 2021
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#ifndef RTW_HEADER_HVSR_CrashChk_h_
#define RTW_HEADER_HVSR_CrashChk_h_
#ifndef HVSR_CrashChk_COMMON_INCLUDES_
# define HVSR_CrashChk_COMMON_INCLUDES_
#include "rtwtypes.h"
#endif                                 /* HVSR_CrashChk_COMMON_INCLUDES_ */

#include "HVSR_CrashChk_types.h"

/* Includes for objects with custom storage classes. */
#include "HVSR_CrahChk_parameter.h"

/* Macros for accessing real-time model data structure */

/* user code (top of header file) */
#include "ASW_Interface.h"

/* Block states (auto storage) for system '<Root>' */
typedef struct {
  real32_T Delay_DSTATE;               /* '<S80>/Delay' */
  real32_T Delay_DSTATE_p;             /* '<S52>/Delay' */
  real32_T Delay_DSTATE_g;             /* '<S17>/Delay' */
  real32_T Delay_DSTATE_b;             /* '<S16>/Delay' */
  real32_T Delay_DSTATE_j;             /* '<S15>/Delay' */
  real32_T Delay_DSTATE_d;             /* '<S14>/Delay' */
  real32_T Delay_DSTATE_pl;            /* '<S13>/Delay' */
  real32_T Delay_DSTATE_f;             /* '<S12>/Delay' */
  real32_T Delay_DSTATE_i;             /* '<S11>/Delay' */
  uint8_T Delay3_DSTATE;               /* '<S10>/Delay3' */
  uint8_T Delay3_DSTATE_b;             /* '<S9>/Delay3' */
  uint8_T Delay3_DSTATE_d;             /* '<S8>/Delay3' */
  uint8_T Delay3_DSTATE_a;             /* '<S7>/Delay3' */
  uint8_T Delay3_DSTATE_m;             /* '<S6>/Delay3' */
  boolean_T Delay2_DSTATE;             /* '<S10>/Delay2' */
  boolean_T Delay2_DSTATE_p;           /* '<S9>/Delay2' */
  boolean_T Delay2_DSTATE_d;           /* '<S8>/Delay2' */
  boolean_T Delay2_DSTATE_i;           /* '<S7>/Delay2' */
  boolean_T Delay2_DSTATE_c;           /* '<S6>/Delay2' */
} DW_HVSR_CrashChk_T;

/* Block states (auto storage) */
extern DW_HVSR_CrashChk_T HVSR_CrashChk_DW;

/* Model entry point functions */
extern void HVSR_CrashChk_initialize(void);
extern void HVSR_CrashChk_step(void);

/* Exported data declaration */

/* Volatile memory section */
#define ASW1_OEM_START_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: Volatile */
extern volatile uint8_T DFC_CrashCANNpl_ASW;
extern volatile uint8_T DFC_CrashChkHwDutyAbnorm_ASW;
extern volatile uint8_T DFC_CrashChkHwFrqAbnorm_ASW;
extern volatile uint8_T DFC_CrashHwNpl_ASW;
extern volatile uint8_T DFC_CrashNpl_ASW;

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"
#define ASW1_OEM_START_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: OutputSignal */
extern volatile boolean_T HVSR_bCrashChkCan;/* Flag for crash state calculated according to CAN bus */
extern volatile boolean_T HVSR_bCrashChkHw;/* Flag for crash state calculated according to hardwire */
extern volatile boolean_T HVSR_bCrashChkHwDutyAbnorm;
extern volatile boolean_T HVSR_bCrashChkHwDutyNorm;
extern volatile boolean_T HVSR_bCrashChkHwFrqAbnorm;
extern volatile boolean_T HVSR_bCrashChkHwFrqNorm;
extern volatile boolean_T HVSR_bCrashDet;/* Flag for crash fault detected */
extern volatile boolean_T HVSR_bCrashHeal;/* Flag for crash fault healed */
extern volatile boolean_T HVSR_bCrashPwmFrqAvl;/* Valid flag for frequency check of crash state received from hardwire */

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'HVSR_CrashChk'
 * '<S1>'   : 'HVSR_CrashChk/HVSR_CrashChk'
 * '<S2>'   : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc'
 * '<S3>'   : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk'
 * '<S4>'   : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/Compare To Constant1'
 * '<S5>'   : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/Compare To Constant3'
 * '<S6>'   : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck'
 * '<S7>'   : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck1'
 * '<S8>'   : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck2'
 * '<S9>'   : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck3'
 * '<S10>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck4'
 * '<S11>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/TONV_10msTimeDebounce1'
 * '<S12>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/TONV_10msTimeDebounce2'
 * '<S13>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/TONV_10msTimeDebounce3'
 * '<S14>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/TONV_10msTimeDebounce4'
 * '<S15>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/TONV_10msTimeDebounce5'
 * '<S16>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/TONV_10msTimeDebounce6'
 * '<S17>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/TONV_10msTimeDebounce7'
 * '<S18>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck/Bit Clear1'
 * '<S19>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck/Bit Clear2'
 * '<S20>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck/Bit Set'
 * '<S21>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck/Bit Set1'
 * '<S22>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck/Bit Set2'
 * '<S23>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck/Bit Set4'
 * '<S24>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck1/Bit Clear1'
 * '<S25>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck1/Bit Clear2'
 * '<S26>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck1/Bit Set'
 * '<S27>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck1/Bit Set1'
 * '<S28>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck1/Bit Set2'
 * '<S29>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck1/Bit Set4'
 * '<S30>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck2/Bit Clear1'
 * '<S31>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck2/Bit Clear2'
 * '<S32>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck2/Bit Set'
 * '<S33>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck2/Bit Set1'
 * '<S34>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck2/Bit Set2'
 * '<S35>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck2/Bit Set4'
 * '<S36>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck3/Bit Clear1'
 * '<S37>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck3/Bit Clear2'
 * '<S38>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck3/Bit Set'
 * '<S39>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck3/Bit Set1'
 * '<S40>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck3/Bit Set2'
 * '<S41>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck3/Bit Set4'
 * '<S42>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck4/Bit Clear1'
 * '<S43>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck4/Bit Clear2'
 * '<S44>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck4/Bit Set'
 * '<S45>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck4/Bit Set1'
 * '<S46>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck4/Bit Set2'
 * '<S47>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashCalc/DSM_ReportCheck4/Bit Set4'
 * '<S48>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN'
 * '<S49>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashHw'
 * '<S50>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN'
 * '<S51>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/Compare To Constant'
 * '<S52>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/TONV_10msTimeDebounce2'
 * '<S53>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant'
 * '<S54>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant1'
 * '<S55>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant10'
 * '<S56>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant11'
 * '<S57>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant12'
 * '<S58>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant13'
 * '<S59>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant14'
 * '<S60>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant15'
 * '<S61>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant16'
 * '<S62>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant17'
 * '<S63>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant18'
 * '<S64>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant19'
 * '<S65>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant2'
 * '<S66>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant20'
 * '<S67>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant21'
 * '<S68>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant22'
 * '<S69>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant3'
 * '<S70>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant4'
 * '<S71>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant5'
 * '<S72>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant6'
 * '<S73>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant7'
 * '<S74>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant8'
 * '<S75>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashCAN/ChkByCAN/Compare To Constant9'
 * '<S76>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashHw/Compare To Constant'
 * '<S77>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashHw/Compare To Constant1'
 * '<S78>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashHw/Compare To Constant2'
 * '<S79>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashHw/Compare To Constant3'
 * '<S80>'  : 'HVSR_CrashChk/HVSR_CrashChk/CrashChk/CrashHw/TONV_10msTimeDebounce2'
 */
#endif                                 /* RTW_HEADER_HVSR_CrashChk_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
