/*
 * File: HVSR_HvilChk.h
 *
 * Code generated for Simulink model 'HVSR_HvilChk'.
 *
 * Model version                  : 1.168
 * Simulink Coder version         : 8.13 (R2017b) 24-Jul-2017
 * C/C++ source code generated on : Thu Jul 29 11:20:56 2021
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#ifndef RTW_HEADER_HVSR_HvilChk_h_
#define RTW_HEADER_HVSR_HvilChk_h_
#include <math.h>
#ifndef HVSR_HvilChk_COMMON_INCLUDES_
# define HVSR_HvilChk_COMMON_INCLUDES_
#include "rtwtypes.h"
#endif                                 /* HVSR_HvilChk_COMMON_INCLUDES_ */

#include "HVSR_HvilChk_types.h"

/* Includes for objects with custom storage classes. */
#include "HVSR_HvilChk_parameter.h"

/* Macros for accessing real-time model data structure */

/* user code (top of header file) */
#include "ASW_Interface.h"

/* Block signals (auto storage) */
typedef struct {
  boolean_T Q;                         /* '<S34>/RS' */
} B_HVSR_HvilChk_T;

/* Block states (auto storage) for system '<Root>' */
typedef struct {
  real32_T Delay_DSTATE;               /* '<S4>/Delay' */
  real32_T Delay_DSTATE_i;             /* '<S45>/Delay' */
  real32_T Delay_DSTATE_j;             /* '<S44>/Delay' */
  real32_T Delay_DSTATE_p;             /* '<S41>/Delay' */
  real32_T Delay_DSTATE_l;             /* '<S40>/Delay' */
  real32_T Delay_DSTATE_k;             /* '<S35>/Delay' */
  uint8_T Delay3_DSTATE;               /* '<S14>/Delay3' */
  uint8_T Delay3_DSTATE_i;             /* '<S13>/Delay3' */
  uint8_T Delay3_DSTATE_j;             /* '<S12>/Delay3' */
  boolean_T Delay2_DSTATE;             /* '<S14>/Delay2' */
  boolean_T Delay2_DSTATE_p;           /* '<S13>/Delay2' */
  boolean_T Delay2_DSTATE_o;           /* '<S12>/Delay2' */
  uint8_T is_active_c3_HVSR_HvilChk;   /* '<S34>/RS' */
} DW_HVSR_HvilChk_T;

/* Block signals (auto storage) */
extern B_HVSR_HvilChk_T HVSR_HvilChk_B;

/* Block states (auto storage) */
extern DW_HVSR_HvilChk_T HVSR_HvilChk_DW;

/* Model entry point functions */
extern void HVSR_HvilChk_initialize(void);
extern void HVSR_HvilChk_step(void);

/* Exported data declaration */

/* Volatile memory section */
#define ASW1_OEM_START_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: Volatile */
extern volatile uint8_T DFC_HvilMax_ASW;   /* Max fault for HVIL Scb diagnosis */
extern volatile uint8_T DFC_HvilMin_ASW;   /* Min fault for HVIL Scg diagnosis */
extern volatile uint8_T DFC_HvilSig_ASW;   /* Sig fault for HVIL Opl diagnosis */

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"
#define ASW1_OEM_START_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: OutputSignal */
extern volatile boolean_T BSPR_bHvilDiagCond;/* Condition for HVIL  diagnosis */
extern volatile boolean_T BSPR_bKl30HvilDiagCond;/* kl30 condition for HVIL diagnosis */
extern volatile real32_T BSPR_dcHvilPwmDuty;/* 高压互锁PWM占空比设定 */
extern volatile boolean_T HVSR_bHvilOplErrDet;/* Error flag for HVIL open load diagnosis */
extern volatile boolean_T HVSR_bHvilOplErrHeal;/* Healing flag for HVIL open load  diagnosis */
extern volatile boolean_T HVSR_bHvilScbErrDet;/* Error flag for HVIL short circuit to battery diagnosis */
extern volatile boolean_T HVSR_bHvilScbErrHeal;/* Healing flag for HVIL short circuit to battery diagnosis */
extern volatile boolean_T HVSR_bHvilScgErrDet;/* Error flag for HVIL short circuit to ground diagnosis */
extern volatile boolean_T HVSR_bHvilScgErrHeal;/* Healing flag for HVIL short circuit to ground diagnosis */
extern volatile boolean_T HVSR_flgHvilFault;/* Fault flag for HVIL detect */

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'HVSR_HvilChk'
 * '<S1>'   : 'HVSR_HvilChk/HVSR_HvilChk'
 * '<S2>'   : 'HVSR_HvilChk/HVSR_HvilChk/ChkCond'
 * '<S3>'   : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag'
 * '<S4>'   : 'HVSR_HvilChk/HVSR_HvilChk/OplCalc'
 * '<S5>'   : 'HVSR_HvilChk/HVSR_HvilChk/ScbCalc'
 * '<S6>'   : 'HVSR_HvilChk/HVSR_HvilChk/ScgCalc'
 * '<S7>'   : 'HVSR_HvilChk/HVSR_HvilChk/ChkCond/Compare To Constant'
 * '<S8>'   : 'HVSR_HvilChk/HVSR_HvilChk/ChkCond/Compare To Constant1'
 * '<S9>'   : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/Compare To Constant'
 * '<S10>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/Compare To Constant1'
 * '<S11>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/Compare To Constant2'
 * '<S12>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck'
 * '<S13>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck1'
 * '<S14>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck2'
 * '<S15>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck/Bit Clear1'
 * '<S16>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck/Bit Clear2'
 * '<S17>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck/Bit Set'
 * '<S18>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck/Bit Set1'
 * '<S19>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck/Bit Set2'
 * '<S20>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck/Bit Set4'
 * '<S21>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck1/Bit Clear1'
 * '<S22>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck1/Bit Clear2'
 * '<S23>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck1/Bit Set'
 * '<S24>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck1/Bit Set1'
 * '<S25>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck1/Bit Set2'
 * '<S26>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck1/Bit Set4'
 * '<S27>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck2/Bit Clear1'
 * '<S28>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck2/Bit Clear2'
 * '<S29>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck2/Bit Set'
 * '<S30>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck2/Bit Set1'
 * '<S31>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck2/Bit Set2'
 * '<S32>'  : 'HVSR_HvilChk/HVSR_HvilChk/DsmDiag/DSM_ReportCheck2/Bit Set4'
 * '<S33>'  : 'HVSR_HvilChk/HVSR_HvilChk/OplCalc/Compare To Constant1'
 * '<S34>'  : 'HVSR_HvilChk/HVSR_HvilChk/OplCalc/RS_FlipFlop'
 * '<S35>'  : 'HVSR_HvilChk/HVSR_HvilChk/OplCalc/TONV_10msTimeDebounce1'
 * '<S36>'  : 'HVSR_HvilChk/HVSR_HvilChk/OplCalc/RS_FlipFlop/RS'
 * '<S37>'  : 'HVSR_HvilChk/HVSR_HvilChk/ScbCalc/Compare To Constant'
 * '<S38>'  : 'HVSR_HvilChk/HVSR_HvilChk/ScbCalc/Compare To Constant2'
 * '<S39>'  : 'HVSR_HvilChk/HVSR_HvilChk/ScbCalc/Compare To Constant3'
 * '<S40>'  : 'HVSR_HvilChk/HVSR_HvilChk/ScbCalc/TONV_10msTimeDebounce'
 * '<S41>'  : 'HVSR_HvilChk/HVSR_HvilChk/ScbCalc/TONV_10msTimeDebounce1'
 * '<S42>'  : 'HVSR_HvilChk/HVSR_HvilChk/ScgCalc/Compare To Constant'
 * '<S43>'  : 'HVSR_HvilChk/HVSR_HvilChk/ScgCalc/Compare To Constant1'
 * '<S44>'  : 'HVSR_HvilChk/HVSR_HvilChk/ScgCalc/TONV_10msTimeDebounce'
 * '<S45>'  : 'HVSR_HvilChk/HVSR_HvilChk/ScgCalc/TONV_10msTimeDebounce1'
 */
#endif                                 /* RTW_HEADER_HVSR_HvilChk_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
