/*
 * File: BCMR_DChrgComProc.h
 *
 * Code generated for Simulink model 'BCMR_DChrgComProc'.
 *
 * Model version                  : 1.100
 * Simulink Coder version         : 8.11 (R2016b) 25-Aug-2016
 * C/C++ source code generated on : Sun Feb 28 20:36:49 2021
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#ifndef RTW_HEADER_BCMR_DChrgComProc_h_
#define RTW_HEADER_BCMR_DChrgComProc_h_
#include <math.h>
#include <stddef.h>
#ifndef BCMR_DChrgComProc_COMMON_INCLUDES_
# define BCMR_DChrgComProc_COMMON_INCLUDES_
#include "rtwtypes.h"
#endif                                 /* BCMR_DChrgComProc_COMMON_INCLUDES_ */

#include "BCMR_DChrgComProc_types.h"

/* Includes for objects with custom storage classes. */
#include "dchrg_comproc_parameters.h"

/* Macros for accessing real-time model data structure */

/* user code (top of header file) */
#include "ASW_Interface.h"

/* Block states (auto storage) for system '<Root>' */
typedef struct {
  real32_T Delay1_DSTATE;              /* '<S43>/Delay1' */
  real32_T Delay_DSTATE;               /* '<S34>/Delay' */
  real32_T Delay_DSTATE_j;             /* '<S31>/Delay' */
  boolean_T Delay2_DSTATE;             /* '<S46>/Delay2' */
  boolean_T Delay1_DSTATE_f;           /* '<S45>/Delay1' */
} DW_BCMR_DChrgComProc_T;

/* Invariant block signals (auto storage) */
typedef struct {
  const uint32_T DataTypeConversion14; /* '<S42>/Data Type Conversion14' */
  const uint32_T DataTypeConversion6;  /* '<S42>/Data Type Conversion6' */
  const uint32_T DataTypeConversion7;  /* '<S42>/Data Type Conversion7' */
  const uint32_T DataTypeConversion9;  /* '<S42>/Data Type Conversion9' */
  const uint32_T DataTypeConversion8;  /* '<S42>/Data Type Conversion8' */
  const uint32_T DataTypeConversion12; /* '<S42>/Data Type Conversion12' */
  const uint32_T DataTypeConversion13; /* '<S42>/Data Type Conversion13' */
  const uint16_T DataTypeConversion15; /* '<S42>/Data Type Conversion15' */
  const uint16_T DataTypeConversion16; /* '<S42>/Data Type Conversion16' */
  const uint16_T DataTypeConversion17; /* '<S42>/Data Type Conversion17' */
  const uint16_T DataTypeConversion2;  /* '<S42>/Data Type Conversion2' */
  const uint16_T DataTypeConversion10; /* '<S42>/Data Type Conversion10' */
  const uint8_T DataTypeConversion;    /* '<S42>/Data Type Conversion' */
  const uint8_T DataTypeConversion1;   /* '<S42>/Data Type Conversion1' */
  const uint8_T DataTypeConversion3;   /* '<S42>/Data Type Conversion3' */
  const uint8_T DataTypeConversion4;   /* '<S42>/Data Type Conversion4' */
  const uint8_T DataTypeConversion5;   /* '<S42>/Data Type Conversion5' */
  const uint8_T DataTypeConversion11;  /* '<S42>/Data Type Conversion11' */
} ConstB_BCMR_DChrgComProc_T;

/* External inputs (root inport signals with auto storage) */
typedef struct {
  real32_T BCMR_flgTxBMV;              /* '<Root>/BCMR_flgTxBMV' */
  real32_T BCMR_flgTxBMT;              /* '<Root>/BCMR_flgTxBMT' */
  real32_T BCMR_flgTxBSP;              /* '<Root>/BCMR_flgTxBSP' */
} ExtU_BCMR_DChrgComProc_T;

/* Block states (auto storage) */
extern DW_BCMR_DChrgComProc_T BCMR_DChrgComProc_DW;

/* External inputs (root inport signals with auto storage) */
extern ExtU_BCMR_DChrgComProc_T BCMR_DChrgComProc_U;
extern const ConstB_BCMR_DChrgComProc_T BCMR_DChrgComProc_ConstB;/* constant block i/o */

/*
 * Exported Global Signals
 *
 * Note: Exported global signals are block signals with an exported global
 * storage class designation.  Code generation will declare the memory for
 * these signals and export their symbols.
 *
 */
extern MSG_BRM_P1 BCMR_strMsgBRM_P1;   /* '<S42>/Bus Creator1' */
extern MSG_BCP_P2 BCMR_strMsgBCP_P2;   /* '<S43>/Bus Creator' */
extern MSG_BSD_P4 BCMR_strMsgBSD_P4;   /* '<S40>/Bus Creator' */
extern MSG_BSM_P3 BCMR_strMsgBSM_P3;   /* '<S56>/Bus Creator2' */
extern MSG_BCL_P3 BCMR_strMsgBCL_P3;   /* '<S54>/Bus Creator' */
extern MSG_BCS_P3 BCMR_strMsgBCS_P3;   /* '<S55>/Bus Creator1' */
extern MSG_BST_P3 BCMR_strMsgBST_P3;   /* '<S57>/Bus Creator3' */
extern MSG_BHM_P1 BCMR_strMsgBHM_P1;   /* '<S41>/Bus Creator' */
extern MSG_BRO_P2 BCMR_strMsgBRO_P2;   /* '<S44>/Bus Creator1' */
extern MSG_BEM_ERR BCMR_strMsgBEM_ERR; /* '<S47>/Bus Creator' */

/* Model entry point functions */
extern void BCMR_DChrgComProc_initialize(void);
extern void BCMR_DChrgComProc_step(void);

/* Exported data declaration */
#define ASW1_OEM_START_SEC_DEFAULT_RAM1_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: OutputSignal */
extern volatile boolean_T BCMR_bRxCrmIdtfRstNg;
extern volatile boolean_T BCMR_bRxCrmIdtfRstOk;
extern volatile boolean_T BCMR_bRxCroRdyNg;
extern volatile boolean_T BCMR_bRxCroRdyOk;
extern volatile uint8_T BCMR_stDChrgerActStop;/* BST */
extern volatile boolean_T BCMR_verDChrgCom2015;
extern volatile real32_T COMR_iDcChrgMaxCurrOutputPmtdCml;
extern volatile real32_T COMR_iDcChrgMinCurrOutputPmtdCml;
extern volatile real32_T COMR_iDcChrgOutputCurrCcs;
extern volatile real32_T COMR_tiDcChrgTimeActualCcs;
extern volatile real32_T COMR_uDcChrgMaxVoltOutputPmtdCml;
extern volatile real32_T COMR_uDcChrgMinVoltOutputPmtdCml;
extern volatile real32_T COMR_vDcChrgOutputVoltCcs;
extern volatile uint8_T DFC_DChrgMsgTimeout_ASW;

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM1_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'BCMR_DChrgComProc'
 * '<S1>'   : 'BCMR_DChrgComProc/BCMR_DcChrgComProc'
 * '<S2>'   : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANInputSigIntegration'
 * '<S3>'   : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro'
 * '<S4>'   : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro'
 * '<S5>'   : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/CRM'
 * '<S6>'   : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/CRO'
 * '<S7>'   : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant'
 * '<S8>'   : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant1'
 * '<S9>'   : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant12'
 * '<S10>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant13'
 * '<S11>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant14'
 * '<S12>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant15'
 * '<S13>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant16'
 * '<S14>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant17'
 * '<S15>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant18'
 * '<S16>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant19'
 * '<S17>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant2'
 * '<S18>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant20'
 * '<S19>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant21'
 * '<S20>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant22'
 * '<S21>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant23'
 * '<S22>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant24'
 * '<S23>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant25'
 * '<S24>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant3'
 * '<S25>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant4'
 * '<S26>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant5'
 * '<S27>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant6'
 * '<S28>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/Compare To Constant7'
 * '<S29>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/CRM/Compare To Constant8'
 * '<S30>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/CRM/Compare To Constant9'
 * '<S31>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/CRM/TONV_VariableTimeDebounce2'
 * '<S32>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/CRO/Compare To Constant8'
 * '<S33>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/CRO/Compare To Constant9'
 * '<S34>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANRxSigPro/CRO/TONV_VariableTimeDebounce2'
 * '<S35>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgEndOutput'
 * '<S36>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgHandOvrOutput'
 * '<S37>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgParaConfigOutput'
 * '<S38>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgTimeOutOutput'
 * '<S39>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgingOutput'
 * '<S40>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgEndOutput/TxBSD'
 * '<S41>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgHandOvrOutput/TxBHM'
 * '<S42>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgHandOvrOutput/TxBRM'
 * '<S43>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgParaConfigOutput/TxBCP'
 * '<S44>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgParaConfigOutput/TxBRO'
 * '<S45>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgParaConfigOutput/TxBCP/EdgeRising2'
 * '<S46>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgTimeOutOutput/DSM_ReportCheck'
 * '<S47>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgTimeOutOutput/TxBEM'
 * '<S48>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgTimeOutOutput/DSM_ReportCheck/Bit Clear1'
 * '<S49>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgTimeOutOutput/DSM_ReportCheck/Bit Clear2'
 * '<S50>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgTimeOutOutput/DSM_ReportCheck/Bit Set'
 * '<S51>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgTimeOutOutput/DSM_ReportCheck/Bit Set1'
 * '<S52>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgTimeOutOutput/DSM_ReportCheck/Bit Set2'
 * '<S53>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgTimeOutOutput/DSM_ReportCheck/Bit Set4'
 * '<S54>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgingOutput/TxBCL'
 * '<S55>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgingOutput/TxBCS'
 * '<S56>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgingOutput/TxBSM'
 * '<S57>'  : 'BCMR_DChrgComProc/BCMR_DcChrgComProc/DCANTxSigPro/DcChrgingOutput/TxBST'
 */
#endif                                 /* RTW_HEADER_BCMR_DChrgComProc_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
