/*
 * File: BTMR_ThmRnwyChk.h
 *
 * Code generated for Simulink model 'BTMR_ThmRnwyChk'.
 *
 * Model version                  : sd
 * Simulink Coder version         : 8.13 (R2017b) 24-Jul-2017
 * C/C++ source code generated on : Wed Aug 25 11:28:21 2021
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#ifndef RTW_HEADER_BTMR_ThmRnwyChk_h_
#define RTW_HEADER_BTMR_ThmRnwyChk_h_
#include <math.h>
#ifndef BTMR_ThmRnwyChk_COMMON_INCLUDES_
# define BTMR_ThmRnwyChk_COMMON_INCLUDES_
#include "rtwtypes.h"
#include "zero_crossing_types.h"
#endif                                 /* BTMR_ThmRnwyChk_COMMON_INCLUDES_ */

#include "BTMR_ThmRnwyChk_types.h"

/* Includes for objects with custom storage classes. */
#include "BTMR_ThmRnwyChk_parameters.h"

/* Macros for accessing real-time model data structure */

/* user code (top of header file) */
#include "ASW_Interface.h"

/* Block signals (auto storage) */
typedef struct {
  real32_T Add;                        /* '<S210>/Add' */
  real32_T DataTypeConversion3;        /* '<S208>/Data Type Conversion3' */
  real32_T BSPR_uCellVoltAvrg_d;       /* '<S208>/BSPR_uCellVoltAvrg' */
  real32_T DataTypeConversion3_n;      /* '<S113>/Data Type Conversion3' */
  real32_T uDMinimum_o1;               /* '<S112>/2-D Minimum' */
  real32_T DataTypeConversion3_m;      /* '<S110>/Data Type Conversion3' */
  real32_T DataTypeConversion3_d;      /* '<S103>/Data Type Conversion3' */
  real32_T uDMaximum_o1;               /* '<S99>/2-D Maximum' */
  real32_T uDMaximum_o1_h;             /* '<S80>/2-D Maximum' */
  real32_T uDMaximum_o1_j;             /* '<S79>/2-D Maximum' */
  real32_T uDMaximum_o1_f;             /* '<S73>/2-D Maximum' */
  uint8_T DataTypeConversion1;         /* '<S210>/Data Type Conversion1' */
  uint8_T DataTypeConversion;          /* '<S173>/Data Type Conversion' */
  uint8_T DataTypeConversion_f;        /* '<S169>/Data Type Conversion' */
  uint8_T DataTypeConversion_fs;       /* '<S187>/Data Type Conversion' */
  uint8_T DataTypeConversion_g;        /* '<S85>/Data Type Conversion' */
  uint8_T SumofElements4;              /* '<S45>/Sum of Elements4' */
  uint8_T DataTypeConversion_b;        /* '<S120>/Data Type Conversion' */
  uint8_T DataTypeConversion_e;        /* '<S113>/Data Type Conversion' */
  uint8_T DataTypeConversion_j;        /* '<S110>/Data Type Conversion' */
  uint8_T DataTypeConversion_h;        /* '<S103>/Data Type Conversion' */
  uint8_T DataTypeConversion_d;        /* '<S99>/Data Type Conversion' */
  uint8_T DataTypeConversion_l;        /* '<S80>/Data Type Conversion' */
  uint8_T DataTypeConversion_c;        /* '<S79>/Data Type Conversion' */
  uint8_T DataTypeConversion_dk;       /* '<S73>/Data Type Conversion' */
  boolean_T LogicalOperator4;          /* '<S231>/Logical Operator4' */
  boolean_T LogicalOperator2;          /* '<S24>/Logical Operator2' */
  boolean_T Switch;                    /* '<S11>/Switch' */
  boolean_T RelationalOperator;        /* '<S165>/Relational Operator' */
  boolean_T RelationalOperator_j;      /* '<S164>/Relational Operator' */
  boolean_T BTMR_bRnwyMaxTGDet_i;      /* '<S43>/Logical Operator2' */
  boolean_T LogicalOperator4_m;        /* '<S97>/Logical Operator4' */
  boolean_T LogicalOperator1;          /* '<S44>/Logical Operator1' */
  boolean_T LogicalOperator4_o;        /* '<S45>/Logical Operator4' */
  boolean_T LogicalOperator4_f;        /* '<S125>/Logical Operator4' */
  boolean_T LogicalOperator4_d;        /* '<S128>/Logical Operator4' */
  boolean_T LogicalOperator2_j;        /* '<S45>/Logical Operator2' */
  boolean_T RelationalOperator5;       /* '<S45>/Relational Operator5' */
  boolean_T LogicalOperator5;          /* '<S10>/Logical Operator5' */
  boolean_T Switch4;                   /* '<S10>/Switch4' */
  boolean_T Switch3;                   /* '<S10>/Switch3' */
  boolean_T Switch5;                   /* '<S10>/Switch5' */
  boolean_T RelationalOperator_d;      /* '<S74>/Relational Operator' */
} B_BTMR_ThmRnwyChk_T;

/* Block states (auto storage) for system '<Root>' */
typedef struct {
  real32_T StateName[48];              /* '<S12>/Unit Delay' */
  real32_T StateName_l[48];            /* '<S14>/Unit Delay' */
  real32_T StateName_p[48];            /* '<S15>/Unit Delay' */
  real32_T StateName_k[48];            /* '<S16>/Unit Delay' */
  real32_T StateName_b[48];            /* '<S17>/Unit Delay' */
  real32_T StateName_be[48];           /* '<S18>/Unit Delay' */
  real32_T StateName_g[48];            /* '<S19>/Unit Delay' */
  real32_T StateName_e[48];            /* '<S20>/Unit Delay' */
  real32_T StateName_bl[48];           /* '<S21>/Unit Delay' */
  real32_T StateName_h[48];            /* '<S13>/Unit Delay' */
  real32_T UnitDelay_DSTATE;           /* '<S216>/Unit Delay' */
  real32_T Delay2_DSTATE;              /* '<S209>/Delay2' */
  real32_T Delay_DSTATE;               /* '<S28>/Delay' */
  real32_T Delay_DSTATE_n;             /* '<S27>/Delay' */
  real32_T Delay_DSTATE_e;             /* '<S26>/Delay' */
  real32_T Delay_DSTATE_i;             /* '<S25>/Delay' */
  real32_T UnitDelay_DSTATE_l;         /* '<S232>/Unit Delay' */
  real32_T Delay_DSTATE_p;             /* '<S213>/Delay' */
  real32_T Delay_DSTATE_ey;            /* '<S212>/Delay' */
  real32_T Delay_DSTATE_e3;            /* '<S211>/Delay' */
  real32_T Delay_DSTATE_d[240];        /* '<S11>/Delay' */
  real32_T Delay1_DSTATE[240];         /* '<S11>/Delay1' */
  real32_T UnitDelay_DSTATE_h;         /* '<S196>/Unit Delay' */
  real32_T UnitDelay_DSTATE_b;         /* '<S178>/Unit Delay' */
  real32_T UnitDelay_DSTATE_g;         /* '<S187>/Unit Delay' */
  real32_T UnitDelay_DSTATE_j;         /* '<S200>/Unit Delay' */
  real32_T UnitDelay_DSTATE_i;         /* '<S182>/Unit Delay' */
  real32_T UnitDelay_DSTATE_c;         /* '<S192>/Unit Delay' */
  real32_T UnitDelay_DSTATE_p;         /* '<S177>/Unit Delay' */
  real32_T UnitDelay_DSTATE_k;         /* '<S181>/Unit Delay' */
  real32_T UnitDelay_DSTATE_i0;        /* '<S186>/Unit Delay' */
  real32_T UnitDelay_DSTATE_f;         /* '<S191>/Unit Delay' */
  real32_T UnitDelay_DSTATE_m;         /* '<S195>/Unit Delay' */
  real32_T UnitDelay_DSTATE_ks;        /* '<S199>/Unit Delay' */
  real32_T Delay_DSTATE_nl;            /* '<S168>/Delay' */
  real32_T Delay_DSTATE_h;             /* '<S167>/Delay' */
  real32_T Delay_DSTATE_ig;            /* '<S166>/Delay' */
  real32_T Delay_DSTATE_a;             /* '<S165>/Delay' */
  real32_T Delay_DSTATE_hd;            /* '<S164>/Delay' */
  real32_T Delay_DSTATE_k;             /* '<S163>/Delay' */
  real32_T Delay_DSTATE_h4;            /* '<S162>/Delay' */
  real32_T Delay_DSTATE_ax;            /* '<S161>/Delay' */
  real32_T Delay_DSTATE_pn;            /* '<S160>/Delay' */
  real32_T UnitDelay_DSTATE_fk;        /* '<S66>/Unit Delay' */
  real32_T UnitDelay_DSTATE_d;         /* '<S65>/Unit Delay' */
  real32_T UnitDelay_DSTATE_k4;        /* '<S69>/Unit Delay' */
  real32_T UnitDelay_DSTATE_hj;        /* '<S92>/Unit Delay' */
  real32_T UnitDelay_DSTATE_a;         /* '<S91>/Unit Delay' */
  real32_T UnitDelay_DSTATE_f1;        /* '<S95>/Unit Delay' */
  real32_T UnitDelay_DSTATE_at;        /* '<S98>/Unit Delay' */
  real32_T Delay4_DSTATE[150];         /* '<S45>/Delay4' */
  real32_T UnitDelay_DSTATE_n;         /* '<S123>/Unit Delay' */
  real32_T UnitDelay_DSTATE_dt;        /* '<S126>/Unit Delay' */
  real32_T Delay2_DSTATE_e[150];       /* '<S45>/Delay2' */
  real32_T Delay3_DSTATE[150];         /* '<S45>/Delay3' */
  real32_T UnitDelay_DSTATE_d2;        /* '<S129>/Unit Delay' */
  real32_T UnitDelay_DSTATE_cr;        /* '<S133>/Unit Delay' */
  real32_T UnitDelay_DSTATE_ar;        /* '<S132>/Unit Delay' */
  real32_T Delay_DSTATE_hx;            /* '<S137>/Delay' */
  real32_T Delay_DSTATE_f[150];        /* '<S119>/Delay' */
  real32_T Delay_DSTATE_m;             /* '<S118>/Delay' */
  real32_T Delay_DSTATE_md;            /* '<S117>/Delay' */
  real32_T Delay_DSTATE_mr;            /* '<S116>/Delay' */
  real32_T Delay_DSTATE_iz;            /* '<S115>/Delay' */
  real32_T Delay_DSTATE_c;             /* '<S100>/Delay' */
  real32_T Delay_DSTATE_l[48];         /* '<S84>/Delay' */
  real32_T Delay_DSTATE_c3[48];        /* '<S83>/Delay' */
  real32_T Delay_DSTATE_lc;            /* '<S82>/Delay' */
  real32_T Delay_DSTATE_g[48];         /* '<S81>/Delay' */
  real32_T Delay_DSTATE_ez;            /* '<S74>/Delay' */
  real32_T Delay_DSTATE_fk;            /* '<S71>/Delay' */
  real32_T Delay_DSTATE_hn[48];        /* '<S59>/Delay' */
  real32_T Delay_DSTATE_j;             /* '<S58>/Delay' */
  real32_T Delay_DSTATE_h4x[48];       /* '<S57>/Delay' */
  real32_T Delay_DSTATE_jf;            /* '<S52>/Delay' */
  uint8_T StateName_ki;                /* '<S12>/Unit Delay1' */
  uint8_T StateName_j;                 /* '<S14>/Unit Delay1' */
  uint8_T StateName_o;                 /* '<S15>/Unit Delay1' */
  uint8_T StateName_ef;                /* '<S16>/Unit Delay1' */
  uint8_T StateName_d;                 /* '<S17>/Unit Delay1' */
  uint8_T StateName_bx;                /* '<S18>/Unit Delay1' */
  uint8_T StateName_jx;                /* '<S19>/Unit Delay1' */
  uint8_T StateName_k1;                /* '<S20>/Unit Delay1' */
  uint8_T StateName_ey;                /* '<S21>/Unit Delay1' */
  uint8_T StateName_i;                 /* '<S13>/Unit Delay1' */
  uint8_T Delay_DSTATE_o;              /* '<S22>/Delay' */
  boolean_T Delay_DSTATE_o5;           /* '<S215>/Delay' */
  boolean_T Delay2_DSTATE_o;           /* '<S201>/Delay2' */
  boolean_T Delay1_DSTATE_k;           /* '<S202>/Delay1' */
  boolean_T Delay1_DSTATE_h;           /* '<S22>/Delay1' */
  boolean_T Delay_DSTATE_axs;          /* '<S231>/Delay' */
  boolean_T Delay2_DSTATE_b;           /* '<S229>/Delay2' */
  boolean_T Delay1_DSTATE_d;           /* '<S230>/Delay1' */
  boolean_T Delay2_DSTATE_bb;          /* '<S221>/Delay2' */
  boolean_T Delay1_DSTATE_a;           /* '<S214>/Delay1' */
  boolean_T Delay_DSTATE_nz;           /* '<S194>/Delay' */
  boolean_T Delay2_DSTATE_h;           /* '<S173>/Delay2' */
  boolean_T Delay_DSTATE_mf;           /* '<S176>/Delay' */
  boolean_T Delay2_DSTATE_m;           /* '<S169>/Delay2' */
  boolean_T Delay_DSTATE_pm;           /* '<S185>/Delay' */
  boolean_T Delay2_DSTATE_hj;          /* '<S171>/Delay2' */
  boolean_T Delay_DSTATE_c5;           /* '<S198>/Delay' */
  boolean_T Delay2_DSTATE_l;           /* '<S174>/Delay2' */
  boolean_T Delay_DSTATE_cw;           /* '<S180>/Delay' */
  boolean_T Delay2_DSTATE_k;           /* '<S170>/Delay2' */
  boolean_T Delay_DSTATE_c1;           /* '<S190>/Delay' */
  boolean_T Delay2_DSTATE_kh;          /* '<S172>/Delay2' */
  boolean_T Delay1_DSTATE_g;           /* '<S197>/Delay1' */
  boolean_T Delay1_DSTATE_du;          /* '<S193>/Delay1' */
  boolean_T Delay1_DSTATE_m;           /* '<S189>/Delay1' */
  boolean_T Delay1_DSTATE_i;           /* '<S188>/Delay1' */
  boolean_T Delay1_DSTATE_o;           /* '<S184>/Delay1' */
  boolean_T Delay1_DSTATE_oe;          /* '<S183>/Delay1' */
  boolean_T Delay1_DSTATE_hb;          /* '<S179>/Delay1' */
  boolean_T Delay1_DSTATE_my;          /* '<S175>/Delay1' */
  boolean_T Delay1_DSTATE_gb;          /* '<S159>/Delay1' */
  boolean_T Delay1_DSTATE_op;          /* '<S158>/Delay1' */
  boolean_T Delay1_DSTATE_j;           /* '<S157>/Delay1' */
  boolean_T Delay1_DSTATE_i3;          /* '<S156>/Delay1' */
  boolean_T Delay1_DSTATE_n;           /* '<S155>/Delay1' */
  boolean_T Delay1_DSTATE_c;           /* '<S154>/Delay1' */
  boolean_T Delay_DSTATE_hs;           /* '<S68>/Delay' */
  boolean_T Delay2_DSTATE_h2;          /* '<S61>/Delay2' */
  boolean_T Delay_DSTATE_gr;           /* '<S64>/Delay' */
  boolean_T Delay2_DSTATE_n;           /* '<S60>/Delay2' */
  boolean_T Delay_DSTATE_dr;           /* '<S94>/Delay' */
  boolean_T Delay2_DSTATE_p;           /* '<S86>/Delay2' */
  boolean_T Delay_DSTATE_p5;           /* '<S90>/Delay' */
  boolean_T Delay2_DSTATE_hs;          /* '<S85>/Delay2' */
  boolean_T Delay2_DSTATE_f;           /* '<S87>/Delay2' */
  boolean_T Delay_DSTATE_cf;           /* '<S97>/Delay' */
  boolean_T Delay2_DSTATE_i;           /* '<S102>/Delay2' */
  boolean_T Delay_DSTATE_jn;           /* '<S122>/Delay' */
  boolean_T Delay2_DSTATE_er;          /* '<S104>/Delay2' */
  boolean_T Delay_DSTATE_j3;           /* '<S125>/Delay' */
  boolean_T Delay_DSTATE_lq;           /* '<S128>/Delay' */
  boolean_T Delay2_DSTATE_ka;          /* '<S111>/Delay2' */
  boolean_T Delay_DSTATE_ib;           /* '<S131>/Delay' */
  boolean_T Delay2_DSTATE_e3;          /* '<S120>/Delay2' */
  boolean_T Delay_DSTATE_ka;           /* '<S10>/Delay' */
  boolean_T Delay1_DSTATE_ha;          /* '<S130>/Delay1' */
  boolean_T Delay1_DSTATE_ka;          /* '<S127>/Delay1' */
  boolean_T Delay1_DSTATE_ky;          /* '<S124>/Delay1' */
  boolean_T Delay1_DSTATE_p;           /* '<S121>/Delay1' */
  boolean_T Delay1_DSTATE_e;           /* '<S96>/Delay1' */
  boolean_T Delay1_DSTATE_d1;          /* '<S93>/Delay1' */
  boolean_T Delay1_DSTATE_m0;          /* '<S89>/Delay1' */
  boolean_T Delay1_DSTATE_e1;          /* '<S88>/Delay1' */
  boolean_T Delay1_DSTATE_cj;          /* '<S67>/Delay1' */
  boolean_T Delay1_DSTATE_ez;          /* '<S63>/Delay1' */
  boolean_T Delay1_DSTATE_dl;          /* '<S62>/Delay1' */
  boolean_T Subsystem_MODE;            /* '<S1>/Subsystem' */
  boolean_T Rnwy_Chk_TPLTmt_MODE;      /* '<S1>/Rnwy_Chk_TPLTmt' */
  boolean_T Rnwy_Chk_MODE;             /* '<S1>/Rnwy_Chk' */
} DW_BTMR_ThmRnwyChk_T;

/* Zero-crossing (trigger) state */
typedef struct {
  ZCSigState ShortCellVoltCal_Trig_ZCE;/* '<S22>/ShortCellVoltCal' */
  ZCSigState LongCellVoltInit_Trig_ZCE;/* '<S22>/LongCellVoltInit' */
  ZCSigState MinVoltIdCal_Trig_ZCE;    /* '<S45>/MinVoltIdCal' */
  ZCSigState MinMdulVoltIdCal_Trig_ZCE;/* '<S45>/MinMdulVoltIdCal' */
  ZCSigState MaxVoltIdCal_Trig_ZCE;    /* '<S45>/MaxVoltIdCal' */
  ZCSigState AbnrVoltGradIdCal_Trig_ZCE;/* '<S45>/AbnrVoltGradIdCal' */
  ZCSigState MaxTempIDCal_Trig_ZCE;    /* '<S44>/MaxTempIDCal' */
  ZCSigState MaxTempGradIDCal1_Trig_ZCE;/* '<S43>/MaxTempGradIDCal1' */
  ZCSigState MaxTempGradIDCal_Trig_ZCE;/* '<S43>/MaxTempGradIDCal' */
  ZCSigState MaxTempIDCal_Trig_ZCE_f;  /* '<S42>/MaxTempIDCal' */
  ZCSigState MaxTempIDCal_Trig_ZCE_l;  /* '<S41>/MaxTempIDCal' */
  ZCSigState MaxTempGradIDCal_Trig_ZCE_l;/* '<S40>/MaxTempGradIDCal' */
  ZCSigState MaxTempIDCal_Trig_ZCE_lt; /* '<S39>/MaxTempIDCal' */
} PrevZCX_BTMR_ThmRnwyChk_T;



/* Model entry point functions */
extern void BTMR_ThmRnwyChk_initialize(void);
extern void BTMR_ThmRnwyChk_step(void);

/* Exported data declaration */

/* Volatile memory section */
#define ASW1_OEM_START_SEC_DEFAULT_RAM0_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: Volatile */
extern volatile uint8_T DFC_ThmRnwy_ASW;

/* Block signals (auto storage) */
extern B_BTMR_ThmRnwyChk_T BTMR_ThmRnwyChk_B;

/* Block states (auto storage) */
extern DW_BTMR_ThmRnwyChk_T BTMR_ThmRnwyChk_DW;

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM0_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"
#define ASW1_OEM_START_SEC_DEFAULT_RAM0_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: OutputSignal */
extern volatile boolean_T BTMR_bBusbarRnwyHighTempDet;
extern volatile boolean_T BTMR_bBusbarRnwyMaxTGDet;
extern volatile boolean_T BTMR_bBusbarRnwyTempDiffDet;
extern volatile boolean_T BTMR_bCellVoltGradAbnrDet;
extern volatile boolean_T BTMR_bLowVoltAlrm;
extern volatile boolean_T BTMR_bMaxVoltDiff;
extern volatile boolean_T BTMR_bMinVoltMdulFit;
extern volatile boolean_T BTMR_bModuleFit;
extern volatile boolean_T BTMR_bNewShrtVoltVld;
extern volatile boolean_T BTMR_bRnwyCellMdulVoltDet;
extern volatile boolean_T BTMR_bRnwyChkSleepPmt;
extern volatile boolean_T BTMR_bRnwyHighTempDet;
extern volatile boolean_T BTMR_bRnwyLowMdulVoltDet;
extern volatile boolean_T BTMR_bRnwyLowVoltDet;
extern volatile boolean_T BTMR_bRnwyMaxTGDet;
extern volatile boolean_T BTMR_bRnwyTempDiffDet;
extern volatile boolean_T BTMR_bRnwyVoltAbnrDet;
extern volatile boolean_T BTMR_bRnwyVoltDiagTGDet;
extern volatile boolean_T BTMR_bShrtLowVoltIDFitWrt;
extern volatile boolean_T BTMR_bStopTimeInvld;
extern volatile boolean_T BTMR_bTPLTmtThmRunAway;
extern volatile boolean_T BTMR_bTPLWkupRnwyDiagEna;
extern volatile boolean_T BTMR_bTSnsrTmt;
extern volatile boolean_T BTMR_bThmRnwyAlrm;
extern volatile boolean_T BTMR_bThmRnwyWarn;
extern volatile boolean_T BTMR_bThmRunAway;
extern volatile boolean_T BTMR_bThmRunAwayCond1;
extern volatile boolean_T BTMR_bThmRunAwayCond2;
extern volatile boolean_T BTMR_bThmRunAwayCond3;
extern volatile boolean_T BTMR_bThmRunAwayCond4;
extern volatile boolean_T BTMR_bVSnsrTmt;
extern volatile boolean_T BTMR_bVoltDiffAlrm;
extern volatile uint8_T BTMR_cntBattTGRnwy;
extern volatile uint8_T BTMR_cntBusbarTGRnwy;
extern volatile uint8_T BTMR_cntCellVoltGradAbnr;
extern volatile uint8_T BTMR_cntRnwyCellVoltAbnr;
extern volatile uint8_T BTMR_cntTPLTmtBattTDiffRnwy;
extern volatile uint8_T BTMR_cntTPLTmtBattTGRnwy;
extern volatile uint8_T BTMR_cntTPLTmtBattTRnwy;
extern volatile boolean_T BTMR_flgBusbarTGRunAwayLv2;
extern volatile boolean_T BTMR_flgBusbarTRunAwayLv3;
extern volatile boolean_T BTMR_flgDSMBattRunAway;
extern volatile boolean_T BTMR_flgNewCellVoltVld;
extern volatile boolean_T BTMR_flgTGRunAwayLv2;
extern volatile boolean_T BTMR_flgTPLWkupRnwyDiag;
extern volatile boolean_T BTMR_flgTRunAwayLv3;
extern volatile uint8_T BTMR_idxAbnrVoltGradID;
extern volatile uint8_T BTMR_idxBusbarMaxTempGradID;
extern volatile uint8_T BTMR_idxBusbarMaxTempID;
extern volatile uint8_T BTMR_idxBusbarTempDiffMaxID;
extern volatile uint8_T BTMR_idxMaxTempGradID;
extern volatile uint8_T BTMR_idxMaxTempGradVoltDiagID;
extern volatile uint8_T BTMR_idxMaxTempID;
extern volatile uint8_T BTMR_idxMaxVoltID;
extern volatile uint8_T BTMR_idxMinMdulVoltID;
extern volatile uint8_T BTMR_idxMinVoltID;
extern volatile uint8_T BTMR_idxShrtLowVoltIDWrt;
extern volatile uint8_T BTMR_idxTempDiffMaxID;
extern volatile real32_T BTMR_tBusbarMaxTemp;
extern volatile real32_T BTMR_tBusbarMaxTempGrad;
extern volatile real32_T BTMR_tBusbarTempDiffMax;
extern volatile real32_T BTMR_tBusbarTempGrad[48];
extern volatile real32_T BTMR_tBusbarTempMax;
extern volatile real32_T BTMR_tBusbarTempMin;
extern volatile real32_T BTMR_tBusbarTemp_A[48];
extern volatile real32_T BTMR_tCellTempGrad[48];
extern volatile real32_T BTMR_tCellTempMax;
extern volatile real32_T BTMR_tCellTempMin;
extern volatile real32_T BTMR_tCellTemp_A[48];
extern volatile real32_T BTMR_tMaxTemp;
extern volatile real32_T BTMR_tMaxTempGrad;
extern volatile real32_T BTMR_tMaxTempGradVoltDiag;
extern volatile real32_T BTMR_tTempDiffMax;
extern volatile uint16_T BTMR_tiRuntimeCalWrt;
extern volatile uint32_T BTMR_tiShortRuntimeSumWrt;
extern volatile real32_T BTMR_uAbnrVoltGrad;
extern volatile real32_T BTMR_uMaxVolt;
extern volatile real32_T BTMR_uMinMdulVolt;
extern volatile real32_T BTMR_uMinStrtVolt;
extern volatile real32_T BTMR_uMinVolt;
extern volatile real32_T BTMR_uShrtCellVoltDiffWrt;
extern volatile real32_T BTMR_uStrtCellVoltAvrg;
extern volatile real32_T Local_uShrtLowVoltDiff;

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM0_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'BTMR_ThmRnwyChk'
 * '<S1>'   : 'BTMR_ThmRnwyChk/RunAway'
 * '<S2>'   : 'BTMR_ThmRnwyChk/RunAway/BusbarTempSig'
 * '<S3>'   : 'BTMR_ThmRnwyChk/RunAway/CellTempSig'
 * '<S4>'   : 'BTMR_ThmRnwyChk/RunAway/Compare To Zero1'
 * '<S5>'   : 'BTMR_ThmRnwyChk/RunAway/Compare To Zero2'
 * '<S6>'   : 'BTMR_ThmRnwyChk/RunAway/Compare To Zero3'
 * '<S7>'   : 'BTMR_ThmRnwyChk/RunAway/Compare To Zero4'
 * '<S8>'   : 'BTMR_ThmRnwyChk/RunAway/DSM_GetSFCErD1'
 * '<S9>'   : 'BTMR_ThmRnwyChk/RunAway/DSM_GetSFCErD2'
 * '<S10>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk'
 * '<S11>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt'
 * '<S12>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Delay1'
 * '<S13>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Delay10'
 * '<S14>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Delay2'
 * '<S15>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Delay3'
 * '<S16>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Delay4'
 * '<S17>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Delay5'
 * '<S18>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Delay6'
 * '<S19>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Delay7'
 * '<S20>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Delay8'
 * '<S21>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Delay9'
 * '<S22>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk'
 * '<S23>'  : 'BTMR_ThmRnwyChk/RunAway/RunA_DSM'
 * '<S24>'  : 'BTMR_ThmRnwyChk/RunAway/Subsystem'
 * '<S25>'  : 'BTMR_ThmRnwyChk/RunAway/TONV_100msTimeDebounce'
 * '<S26>'  : 'BTMR_ThmRnwyChk/RunAway/TONV_100msTimeDebounce1'
 * '<S27>'  : 'BTMR_ThmRnwyChk/RunAway/TONV_100msTimeDebounce2'
 * '<S28>'  : 'BTMR_ThmRnwyChk/RunAway/TONV_100msTimeDebounce3'
 * '<S29>'  : 'BTMR_ThmRnwyChk/RunAway/BusbarTempSig/BusbarTempProc'
 * '<S30>'  : 'BTMR_ThmRnwyChk/RunAway/BusbarTempSig/Subsystem'
 * '<S31>'  : 'BTMR_ThmRnwyChk/RunAway/BusbarTempSig/BusbarTempProc/BusbarTempFilter'
 * '<S32>'  : 'BTMR_ThmRnwyChk/RunAway/BusbarTempSig/BusbarTempProc/TONV_VariableTimeDebounce'
 * '<S33>'  : 'BTMR_ThmRnwyChk/RunAway/CellTempSig/CellTempProc'
 * '<S34>'  : 'BTMR_ThmRnwyChk/RunAway/CellTempSig/Subsystem'
 * '<S35>'  : 'BTMR_ThmRnwyChk/RunAway/CellTempSig/CellTempProc/CellTempFilter'
 * '<S36>'  : 'BTMR_ThmRnwyChk/RunAway/CellTempSig/CellTempProc/TONV_VariableTimeDebounce'
 * '<S37>'  : 'BTMR_ThmRnwyChk/RunAway/DSM_GetSFCErD1/DFC_IsoChkLv1_1_compare'
 * '<S38>'  : 'BTMR_ThmRnwyChk/RunAway/DSM_GetSFCErD2/DFC_IsoChkLv1_1_compare'
 * '<S39>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempDiffDiag'
 * '<S40>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempGradDiag'
 * '<S41>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempMaxDiag'
 * '<S42>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempDiffDiag'
 * '<S43>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag'
 * '<S44>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempMaxDiag'
 * '<S45>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag'
 * '<S46>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/Compare To Constant'
 * '<S47>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/ModuleCompare'
 * '<S48>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/RnwyCond2Diag'
 * '<S49>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/RnwyCond3Diag'
 * '<S50>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/RnwyCond4Diag'
 * '<S51>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempDiffDiag/MaxTempIDCal'
 * '<S52>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempDiffDiag/TONV_100msTimeDebounce4'
 * '<S53>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempGradDiag/Compare To Zero'
 * '<S54>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempGradDiag/Compare To Zero1'
 * '<S55>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempGradDiag/Compare To Zero2'
 * '<S56>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempGradDiag/MaxTempGradIDCal'
 * '<S57>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempGradDiag/TONV_100msTimeDebounce1'
 * '<S58>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempGradDiag/TONV_100msTimeDebounce2'
 * '<S59>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempGradDiag/TONV_100msTimeDebounce4'
 * '<S60>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempGradDiag/TempGradConditionCnt'
 * '<S61>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempGradDiag/TempGradConditionLv2'
 * '<S62>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempGradDiag/TempGradConditionCnt/EdgeRising'
 * '<S63>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempGradDiag/TempGradConditionCnt/EdgeRising1'
 * '<S64>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempGradDiag/TempGradConditionCnt/Subsystem3'
 * '<S65>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempGradDiag/TempGradConditionCnt/Timer'
 * '<S66>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempGradDiag/TempGradConditionCnt/Timser1'
 * '<S67>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempGradDiag/TempGradConditionLv2/EdgeRising'
 * '<S68>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempGradDiag/TempGradConditionLv2/Subsystem3'
 * '<S69>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempGradDiag/TempGradConditionLv2/Timer'
 * '<S70>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempMaxDiag/MaxTempIDCal'
 * '<S71>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempMaxDiag/TONV_100msTimeDebounce1'
 * '<S72>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/BusbarTempMaxDiag/TONV_100msTimeDebounce2'
 * '<S73>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempDiffDiag/MaxTempIDCal'
 * '<S74>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempDiffDiag/TONV_100msTimeDebounce4'
 * '<S75>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/Compare To Zero'
 * '<S76>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/Compare To Zero1'
 * '<S77>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/Compare To Zero2'
 * '<S78>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/Compare To Zero3'
 * '<S79>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/MaxTempGradIDCal'
 * '<S80>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/MaxTempGradIDCal1'
 * '<S81>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/TONV_100msTimeDebounce1'
 * '<S82>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/TONV_100msTimeDebounce2'
 * '<S83>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/TONV_100msTimeDebounce3'
 * '<S84>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/TONV_100msTimeDebounce4'
 * '<S85>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/TempGradConditionCnt'
 * '<S86>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/TempGradConditionLv2'
 * '<S87>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/VoltGTempGradCondition'
 * '<S88>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/TempGradConditionCnt/EdgeRising'
 * '<S89>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/TempGradConditionCnt/EdgeRising1'
 * '<S90>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/TempGradConditionCnt/Subsystem3'
 * '<S91>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/TempGradConditionCnt/Timer'
 * '<S92>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/TempGradConditionCnt/Timser1'
 * '<S93>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/TempGradConditionLv2/EdgeRising'
 * '<S94>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/TempGradConditionLv2/Subsystem3'
 * '<S95>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/TempGradConditionLv2/Timer'
 * '<S96>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/VoltGTempGradCondition/EdgeRising'
 * '<S97>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/VoltGTempGradCondition/Subsystem3'
 * '<S98>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempGradDiag/VoltGTempGradCondition/Timer'
 * '<S99>'  : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempMaxDiag/MaxTempIDCal'
 * '<S100>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempMaxDiag/TONV_100msTimeDebounce1'
 * '<S101>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellTempMaxDiag/TONV_100msTimeDebounce2'
 * '<S102>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/AbnrVoltFlgHld'
 * '<S103>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/AbnrVoltGradIdCal'
 * '<S104>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/CellVoltConditon'
 * '<S105>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/Compare To Zero1'
 * '<S106>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/Compare To Zero2'
 * '<S107>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/Compare To Zero3'
 * '<S108>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/Compare To Zero4'
 * '<S109>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/Compare To Zero5'
 * '<S110>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/MaxVoltIdCal'
 * '<S111>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/MdulVoltConditon'
 * '<S112>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/MinMdulVoltIdCal'
 * '<S113>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/MinVoltIdCal'
 * '<S114>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/MinVoltMdulCompare'
 * '<S115>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/TONV_100msTimeDebounce1'
 * '<S116>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/TONV_100msTimeDebounce2'
 * '<S117>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/TONV_100msTimeDebounce3'
 * '<S118>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/TONV_100msTimeDebounce4'
 * '<S119>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/TONV_100msTimeDebounce5'
 * '<S120>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/VoltConditionCnt'
 * '<S121>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/AbnrVoltFlgHld/EdgeRising'
 * '<S122>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/AbnrVoltFlgHld/Subsystem3'
 * '<S123>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/AbnrVoltFlgHld/Timer'
 * '<S124>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/CellVoltConditon/EdgeRising'
 * '<S125>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/CellVoltConditon/Subsystem3'
 * '<S126>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/CellVoltConditon/Timer'
 * '<S127>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/MdulVoltConditon/EdgeRising'
 * '<S128>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/MdulVoltConditon/Subsystem3'
 * '<S129>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/MdulVoltConditon/Timer'
 * '<S130>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/VoltConditionCnt/EdgeRising'
 * '<S131>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/VoltConditionCnt/Subsystem3'
 * '<S132>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/VoltConditionCnt/Timer'
 * '<S133>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/CellVoltDiag/VoltConditionCnt/Timser1'
 * '<S134>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/ModuleCompare/Compare To Zero1'
 * '<S135>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/ModuleCompare/Compare To Zero2'
 * '<S136>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/ModuleCompare/Compare To Zero3'
 * '<S137>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/ModuleCompare/TONV_100msTimeDebounce2'
 * '<S138>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/RnwyCond2Diag/VoltTempCompare'
 * '<S139>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/RnwyCond2Diag/VoltTempDiffCompare'
 * '<S140>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/RnwyCond2Diag/VoltTempGradCompare'
 * '<S141>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/RnwyCond2Diag/VoltTempCompare/Compare To Zero1'
 * '<S142>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/RnwyCond2Diag/VoltTempCompare/Compare To Zero3'
 * '<S143>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/RnwyCond2Diag/VoltTempDiffCompare/Compare To Zero1'
 * '<S144>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/RnwyCond2Diag/VoltTempDiffCompare/Compare To Zero3'
 * '<S145>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/RnwyCond2Diag/VoltTempGradCompare/Compare To Zero1'
 * '<S146>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/RnwyCond2Diag/VoltTempGradCompare/Compare To Zero3'
 * '<S147>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk/RnwyCond3Diag/Compare To Zero3'
 * '<S148>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/Compare To Constant'
 * '<S149>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/Compare To Zero'
 * '<S150>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/Compare To Zero1'
 * '<S151>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/Compare To Zero2'
 * '<S152>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/Compare To Zero3'
 * '<S153>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/Compare To Zero4'
 * '<S154>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/EdgeRising1'
 * '<S155>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/EdgeRising2'
 * '<S156>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/EdgeRising3'
 * '<S157>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/EdgeRising4'
 * '<S158>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/EdgeRising5'
 * '<S159>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/EdgeRising6'
 * '<S160>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TONV_100msTimeDebounce1'
 * '<S161>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TONV_100msTimeDebounce2'
 * '<S162>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TONV_100msTimeDebounce3'
 * '<S163>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TONV_100msTimeDebounce4'
 * '<S164>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TONV_100msTimeDebounce5'
 * '<S165>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TONV_100msTimeDebounce6'
 * '<S166>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TONV_100msTimeDebounce7'
 * '<S167>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TONV_100msTimeDebounce8'
 * '<S168>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TONV_100msTimeDebounce9'
 * '<S169>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempConditionCnt'
 * '<S170>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempConditionCnt1'
 * '<S171>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempDiffConditionCnt'
 * '<S172>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempDiffConditionCnt1'
 * '<S173>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempGradConditionCnt'
 * '<S174>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempGradConditionCnt1'
 * '<S175>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempConditionCnt/EdgeRising'
 * '<S176>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempConditionCnt/Subsystem3'
 * '<S177>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempConditionCnt/Timer'
 * '<S178>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempConditionCnt/Timser1'
 * '<S179>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempConditionCnt1/EdgeRising'
 * '<S180>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempConditionCnt1/Subsystem3'
 * '<S181>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempConditionCnt1/Timer'
 * '<S182>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempConditionCnt1/Timser1'
 * '<S183>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempDiffConditionCnt/EdgeRising'
 * '<S184>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempDiffConditionCnt/EdgeRising1'
 * '<S185>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempDiffConditionCnt/Subsystem3'
 * '<S186>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempDiffConditionCnt/Timser'
 * '<S187>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempDiffConditionCnt/Timser1'
 * '<S188>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempDiffConditionCnt1/EdgeRising'
 * '<S189>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempDiffConditionCnt1/EdgeRising1'
 * '<S190>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempDiffConditionCnt1/Subsystem3'
 * '<S191>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempDiffConditionCnt1/Timser'
 * '<S192>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempDiffConditionCnt1/Timser1'
 * '<S193>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempGradConditionCnt/EdgeRising'
 * '<S194>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempGradConditionCnt/Subsystem3'
 * '<S195>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempGradConditionCnt/Timer'
 * '<S196>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempGradConditionCnt/Timser1'
 * '<S197>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempGradConditionCnt1/EdgeRising'
 * '<S198>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempGradConditionCnt1/Subsystem3'
 * '<S199>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempGradConditionCnt1/Timer'
 * '<S200>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_Chk_TPLTmt/TPLTmtTempGradConditionCnt1/Timser1'
 * '<S201>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk/BMSModeEna'
 * '<S202>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk/CellIDInherit'
 * '<S203>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk/CellVoltCompare'
 * '<S204>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk/Compare To Constant1'
 * '<S205>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk/Compare To Constant2'
 * '<S206>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk/Compare To Zero1'
 * '<S207>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk/Compare To Zero3'
 * '<S208>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk/LongCellVoltInit'
 * '<S209>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk/RunTimeCal'
 * '<S210>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk/ShortCellVoltCal'
 * '<S211>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk/TONV_100msTimeDebounce1'
 * '<S212>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk/TONV_100msTimeDebounce2'
 * '<S213>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk/TONV_100msTimeDebounce3'
 * '<S214>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk/BMSModeEna/EdgeRising'
 * '<S215>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk/BMSModeEna/Subsystem3'
 * '<S216>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk/BMSModeEna/Timer'
 * '<S217>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk/CellIDInherit/Compare To Zero2'
 * '<S218>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk/CellIDInherit/Compare To Zero4'
 * '<S219>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk/CellVoltCompare/Compare To Zero1'
 * '<S220>' : 'BTMR_ThmRnwyChk/RunAway/Rnwy_PreChk/CellVoltCompare/Compare To Zero3'
 * '<S221>' : 'BTMR_ThmRnwyChk/RunAway/RunA_DSM/DSM_ReportCheck'
 * '<S222>' : 'BTMR_ThmRnwyChk/RunAway/RunA_DSM/DSM_ReportCheck/Bit Clear1'
 * '<S223>' : 'BTMR_ThmRnwyChk/RunAway/RunA_DSM/DSM_ReportCheck/Bit Clear2'
 * '<S224>' : 'BTMR_ThmRnwyChk/RunAway/RunA_DSM/DSM_ReportCheck/Bit Set'
 * '<S225>' : 'BTMR_ThmRnwyChk/RunAway/RunA_DSM/DSM_ReportCheck/Bit Set1'
 * '<S226>' : 'BTMR_ThmRnwyChk/RunAway/RunA_DSM/DSM_ReportCheck/Bit Set2'
 * '<S227>' : 'BTMR_ThmRnwyChk/RunAway/RunA_DSM/DSM_ReportCheck/Bit Set4'
 * '<S228>' : 'BTMR_ThmRnwyChk/RunAway/Subsystem/Compare To Zero4'
 * '<S229>' : 'BTMR_ThmRnwyChk/RunAway/Subsystem/TPLWkupDiagDeb'
 * '<S230>' : 'BTMR_ThmRnwyChk/RunAway/Subsystem/TPLWkupDiagDeb/EdgeRising'
 * '<S231>' : 'BTMR_ThmRnwyChk/RunAway/Subsystem/TPLWkupDiagDeb/Subsystem3'
 * '<S232>' : 'BTMR_ThmRnwyChk/RunAway/Subsystem/TPLWkupDiagDeb/Timer'
 */
#endif                                 /* RTW_HEADER_BTMR_ThmRnwyChk_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
