/*
 * File: BSPR_BattTempDsmDiag.h
 *
 * Code generated for Simulink model 'BSPR_BattTempDsmDiag'.
 *
 * Model version                  : 1.1322
 * Simulink Coder version         : 8.13 (R2017b) 24-Jul-2017
 * C/C++ source code generated on : Thu Nov 19 11:36:27 2020
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#ifndef RTW_HEADER_BSPR_BattTempDsmDiag_h_
#define RTW_HEADER_BSPR_BattTempDsmDiag_h_
#ifndef BSPR_BattTempDsmDiag_COMMON_INCLUDES_
# define BSPR_BattTempDsmDiag_COMMON_INCLUDES_
#include "rtwtypes.h"
#endif                                 /* BSPR_BattTempDsmDiag_COMMON_INCLUDES_ */

#include "BSPR_BattTempDsmDiag_types.h"

/* Macros for accessing real-time model data structure */

/* user code (top of header file) */
#include "ASW_Interface.h"

/* Block states (auto storage) for system '<Root>' */
typedef struct {
  uint8_T Delay3_DSTATE;               /* '<S100>/Delay3' */
  uint8_T Delay3_DSTATE_b;             /* '<S99>/Delay3' */
  uint8_T Delay3_DSTATE_a;             /* '<S98>/Delay3' */
  uint8_T Delay3_DSTATE_e;             /* '<S97>/Delay3' */
  uint8_T Delay3_DSTATE_j;             /* '<S96>/Delay3' */
  uint8_T Delay3_DSTATE_n;             /* '<S95>/Delay3' */
  uint8_T Delay3_DSTATE_l;             /* '<S76>/Delay3' */
  uint8_T Delay3_DSTATE_d;             /* '<S75>/Delay3' */
  uint8_T Delay3_DSTATE_c;             /* '<S74>/Delay3' */
  uint8_T Delay3_DSTATE_i;             /* '<S33>/Delay3' */
  uint8_T Delay3_DSTATE_p;             /* '<S32>/Delay3' */
  uint8_T Delay3_DSTATE_nu;            /* '<S31>/Delay3' */
  uint8_T Delay3_DSTATE_jf;            /* '<S30>/Delay3' */
  uint8_T Delay3_DSTATE_d5;            /* '<S29>/Delay3' */
  uint8_T Delay3_DSTATE_h;             /* '<S28>/Delay3' */
  uint8_T Delay3_DSTATE_hn;            /* '<S9>/Delay3' */
  uint8_T Delay3_DSTATE_bf;            /* '<S8>/Delay3' */
  uint8_T Delay3_DSTATE_bj;            /* '<S7>/Delay3' */
  boolean_T Delay2_DSTATE;             /* '<S100>/Delay2' */
  boolean_T Delay2_DSTATE_p;           /* '<S99>/Delay2' */
  boolean_T Delay2_DSTATE_b;           /* '<S98>/Delay2' */
  boolean_T Delay2_DSTATE_h;           /* '<S97>/Delay2' */
  boolean_T Delay2_DSTATE_a;           /* '<S96>/Delay2' */
  boolean_T Delay2_DSTATE_f;           /* '<S95>/Delay2' */
  boolean_T Delay2_DSTATE_e;           /* '<S76>/Delay2' */
  boolean_T Delay2_DSTATE_i;           /* '<S75>/Delay2' */
  boolean_T Delay2_DSTATE_b3;          /* '<S74>/Delay2' */
  boolean_T Delay2_DSTATE_o;           /* '<S33>/Delay2' */
  boolean_T Delay2_DSTATE_g;           /* '<S32>/Delay2' */
  boolean_T Delay2_DSTATE_j;           /* '<S31>/Delay2' */
  boolean_T Delay2_DSTATE_ey;          /* '<S30>/Delay2' */
  boolean_T Delay2_DSTATE_ec;          /* '<S29>/Delay2' */
  boolean_T Delay2_DSTATE_hi;          /* '<S28>/Delay2' */
  boolean_T Delay2_DSTATE_is;          /* '<S9>/Delay2' */
  boolean_T Delay2_DSTATE_o2;          /* '<S8>/Delay2' */
  boolean_T Delay2_DSTATE_d;           /* '<S7>/Delay2' */
} DW_BSPR_BattTempDsmDiag_T;

/* Block states (auto storage) */
extern DW_BSPR_BattTempDsmDiag_T BSPR_BattTempDsmDiag_DW;

/* Model entry point functions */
extern void BSPR_BattTempDsmDiag_initialize(void);
extern void BSPR_BattTempDsmDiag_step(void);

/* Exported data declaration */

/* Volatile memory section */
#define ASW1_OEM_START_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: Volatile */
extern volatile uint8_T DFC_BattTAlrmMax_ASW;/* Out of range high alarm  level error of battery temperature sensor */
extern volatile uint8_T DFC_BattTAlrmMin_ASW;/* Out of range low alarm  level error of battery temperature sensor */
extern volatile uint8_T DFC_BattTCnstMax_ASW;/* Consistent error  of battery temperature sensor */
extern volatile uint8_T DFC_BattTFaultMax_ASW;/* Out of range high serious level error of battery temperature sensor */
extern volatile uint8_T DFC_BattTFaultMin_ASW;/* Out of range low serious level error of battery temperature sensor */
extern volatile uint8_T DFC_BattTGradtMax_ASW;/* Gradt error  of battery temperature sensor */
extern volatile uint8_T DFC_BattTHopMax_ASW;/* Jitter error of battery temperature sensor */
extern volatile uint8_T DFC_BattTWarnMax_ASW;/* Out of range high alarm level error of battery temperature sensor */
extern volatile uint8_T DFC_BattTWarnMin_ASW;/* Out of range low alarm  level error of battery temperature sensor */
extern volatile uint8_T DFC_CellTAlrmMax_ASW;/* Out of range high alarm  level error of battery temperature sensor */
extern volatile uint8_T DFC_CellTAlrmMin_ASW;/* Out of range low alarm  level error of battery temperature sensor */
extern volatile uint8_T DFC_CellTCnstMax_ASW;/* Consistent error  of battery temperature sensor */
extern volatile uint8_T DFC_CellTFaultMax_ASW;/* Out of range high serious level error of battery temperature sensor */
extern volatile uint8_T DFC_CellTFaultMin_ASW;/* Out of range low serious level error of battery temperature sensor */
extern volatile uint8_T DFC_CellTGradtMax_ASW;/* Gradt error  of battery temperature sensor */
extern volatile uint8_T DFC_CellTHopMax_ASW;/* Jitter error of battery temperature sensor */
extern volatile uint8_T DFC_CellTWarnMax_ASW;/* Out of range high alarm level error of battery temperature sensor */
extern volatile uint8_T DFC_CellTWarnMin_ASW;/* Out of range low alarm  level error of battery temperature sensor */

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'BSPR_BattTempDsmDiag'
 * '<S1>'   : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag'
 * '<S2>'   : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag'
 * '<S3>'   : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag'
 * '<S4>'   : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag'
 * '<S5>'   : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/Compare To Constant'
 * '<S6>'   : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/Compare To Constant2'
 * '<S7>'   : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck'
 * '<S8>'   : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck1'
 * '<S9>'   : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck2'
 * '<S10>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck/Bit Clear1'
 * '<S11>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck/Bit Clear2'
 * '<S12>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck/Bit Set'
 * '<S13>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck/Bit Set1'
 * '<S14>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck/Bit Set2'
 * '<S15>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck/Bit Set4'
 * '<S16>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck1/Bit Clear1'
 * '<S17>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck1/Bit Clear2'
 * '<S18>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck1/Bit Set'
 * '<S19>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck1/Bit Set1'
 * '<S20>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck1/Bit Set2'
 * '<S21>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck1/Bit Set4'
 * '<S22>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck2/Bit Clear1'
 * '<S23>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck2/Bit Clear2'
 * '<S24>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck2/Bit Set'
 * '<S25>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck2/Bit Set1'
 * '<S26>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck2/Bit Set2'
 * '<S27>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/PlausDsmDiag/DSM_ReportCheck2/Bit Set4'
 * '<S28>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck'
 * '<S29>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck1'
 * '<S30>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck2'
 * '<S31>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck3'
 * '<S32>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck4'
 * '<S33>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck5'
 * '<S34>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck/Bit Clear1'
 * '<S35>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck/Bit Clear2'
 * '<S36>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck/Bit Set'
 * '<S37>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck/Bit Set1'
 * '<S38>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck/Bit Set2'
 * '<S39>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck/Bit Set4'
 * '<S40>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck1/Bit Clear1'
 * '<S41>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck1/Bit Clear2'
 * '<S42>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck1/Bit Set'
 * '<S43>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck1/Bit Set1'
 * '<S44>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck1/Bit Set2'
 * '<S45>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck1/Bit Set4'
 * '<S46>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck2/Bit Clear1'
 * '<S47>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck2/Bit Clear2'
 * '<S48>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck2/Bit Set'
 * '<S49>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck2/Bit Set1'
 * '<S50>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck2/Bit Set2'
 * '<S51>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck2/Bit Set4'
 * '<S52>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck3/Bit Clear1'
 * '<S53>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck3/Bit Clear2'
 * '<S54>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck3/Bit Set'
 * '<S55>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck3/Bit Set1'
 * '<S56>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck3/Bit Set2'
 * '<S57>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck3/Bit Set4'
 * '<S58>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck4/Bit Clear1'
 * '<S59>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck4/Bit Clear2'
 * '<S60>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck4/Bit Set'
 * '<S61>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck4/Bit Set1'
 * '<S62>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck4/Bit Set2'
 * '<S63>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck4/Bit Set4'
 * '<S64>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck5/Bit Clear1'
 * '<S65>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck5/Bit Clear2'
 * '<S66>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck5/Bit Set'
 * '<S67>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck5/Bit Set1'
 * '<S68>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck5/Bit Set2'
 * '<S69>'  : 'BSPR_BattTempDsmDiag/BSPR_BattTempDsmDiag/RngDsmDiag/DSM_ReportCheck5/Bit Set4'
 * '<S70>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag'
 * '<S71>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag'
 * '<S72>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/Compare To Constant'
 * '<S73>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/Compare To Constant2'
 * '<S74>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck'
 * '<S75>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck1'
 * '<S76>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck2'
 * '<S77>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck/Bit Clear1'
 * '<S78>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck/Bit Clear2'
 * '<S79>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck/Bit Set'
 * '<S80>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck/Bit Set1'
 * '<S81>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck/Bit Set2'
 * '<S82>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck/Bit Set4'
 * '<S83>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck1/Bit Clear1'
 * '<S84>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck1/Bit Clear2'
 * '<S85>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck1/Bit Set'
 * '<S86>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck1/Bit Set1'
 * '<S87>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck1/Bit Set2'
 * '<S88>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck1/Bit Set4'
 * '<S89>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck2/Bit Clear1'
 * '<S90>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck2/Bit Clear2'
 * '<S91>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck2/Bit Set'
 * '<S92>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck2/Bit Set1'
 * '<S93>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck2/Bit Set2'
 * '<S94>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_PlausDsmDiag/DSM_ReportCheck2/Bit Set4'
 * '<S95>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck'
 * '<S96>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck1'
 * '<S97>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck2'
 * '<S98>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck3'
 * '<S99>'  : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck4'
 * '<S100>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck5'
 * '<S101>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck/Bit Clear1'
 * '<S102>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck/Bit Clear2'
 * '<S103>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck/Bit Set'
 * '<S104>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck/Bit Set1'
 * '<S105>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck/Bit Set2'
 * '<S106>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck/Bit Set4'
 * '<S107>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck1/Bit Clear1'
 * '<S108>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck1/Bit Clear2'
 * '<S109>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck1/Bit Set'
 * '<S110>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck1/Bit Set1'
 * '<S111>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck1/Bit Set2'
 * '<S112>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck1/Bit Set4'
 * '<S113>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck2/Bit Clear1'
 * '<S114>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck2/Bit Clear2'
 * '<S115>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck2/Bit Set'
 * '<S116>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck2/Bit Set1'
 * '<S117>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck2/Bit Set2'
 * '<S118>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck2/Bit Set4'
 * '<S119>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck3/Bit Clear1'
 * '<S120>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck3/Bit Clear2'
 * '<S121>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck3/Bit Set'
 * '<S122>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck3/Bit Set1'
 * '<S123>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck3/Bit Set2'
 * '<S124>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck3/Bit Set4'
 * '<S125>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck4/Bit Clear1'
 * '<S126>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck4/Bit Clear2'
 * '<S127>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck4/Bit Set'
 * '<S128>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck4/Bit Set1'
 * '<S129>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck4/Bit Set2'
 * '<S130>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck4/Bit Set4'
 * '<S131>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck5/Bit Clear1'
 * '<S132>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck5/Bit Clear2'
 * '<S133>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck5/Bit Set'
 * '<S134>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck5/Bit Set1'
 * '<S135>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck5/Bit Set2'
 * '<S136>' : 'BSPR_BattTempDsmDiag/BSPR_CellTempDsmDiag/Cell_RngDsmDiag/DSM_ReportCheck5/Bit Set4'
 */
#endif                                 /* RTW_HEADER_BSPR_BattTempDsmDiag_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
