/*
 * File: CFM.h
 *
 * Code generated for Simulink model 'CFM'.
 *
 * Company                        : AIWAYS
 * Author                         : zhangzy
 * Model version                  : 'M111C110'
 * Simulink Coder version         : 8.13 (R2017b) 24-Jul-2017
 * C/C++ source code generated on : Wed Jul 14 16:29:42 2021
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Safety precaution
 * Validation result: Not run
 */

#ifndef RTW_HEADER_CFM_h_
#define RTW_HEADER_CFM_h_
#ifndef CFM_COMMON_INCLUDES_
# define CFM_COMMON_INCLUDES_
#include "rtwtypes.h"
#endif                                 /* CFM_COMMON_INCLUDES_ */

#include "CFM_types.h"

/* Includes for objects with custom storage classes. */
#include "CFM_Var.h"
#include "CFM_Cal.h"
#include "CFM_Const.h"

/* Macros for accessing real-time model data structure */

/* user code (top of header file) */
#include "ASW_Interface.h"

/* Block signals for system '<S4>/BMSDelay' */
typedef struct {
  boolean_T RelationalOperator[8];     /* '<S9>/Relational Operator' */
} B_BMSDelay_CFM_T;

/* Block states (auto storage) for system '<S4>/BMSDelay' */
typedef struct {
  uint16_T FixPtUnitDelay1_DSTATE[8];  /* '<S11>/FixPt Unit Delay1' */
  uint8_T FixPtUnitDelay2_DSTATE;      /* '<S11>/FixPt Unit Delay2' */
} DW_BMSDelay_CFM_T;

/* Block signals (auto storage) */
typedef struct {
  B_BMSDelay_CFM_T BMSDelay_cq;        /* '<S8>/BMSDelay' */
  B_BMSDelay_CFM_T BMSDelay_h;         /* '<S7>/BMSDelay' */
  B_BMSDelay_CFM_T BMSDelay_f;         /* '<S20>/BMSDelay' */
  B_BMSDelay_CFM_T BMSDelay_b;         /* '<S18>/BMSDelay' */
  B_BMSDelay_CFM_T BMSDelay_c;         /* '<S17>/BMSDelay' */
  B_BMSDelay_CFM_T BMSDelay_n;         /* '<S16>/BMSDelay' */
  B_BMSDelay_CFM_T BMSDelay_d;         /* '<S15>/BMSDelay' */
  B_BMSDelay_CFM_T BMSDelay_a;         /* '<S5>/BMSDelay' */
  B_BMSDelay_CFM_T BMSDelay;           /* '<S4>/BMSDelay' */
} B_CFM_T;

/* Block states (auto storage) for system '<Root>' */
typedef struct {
  boolean_T StateName;                 /* '<S42>/Unit Delay21' */
  boolean_T StateName_c;               /* '<S41>/Unit Delay21' */
  boolean_T StateName_o;               /* '<S40>/Unit Delay21' */
  boolean_T StateName_l;               /* '<S39>/Unit Delay21' */
  boolean_T StateName_h;               /* '<S38>/Unit Delay21' */
  uint8_T MinCellTempNumbIterator_Iterati;/* '<S42>/MinCellTempNumbIterator' */
  uint8_T MinCellTempNumbIterator_Itera_i;/* '<S41>/MinCellTempNumbIterator' */
  uint8_T MinCellTempNumbIterator_Itera_k;/* '<S40>/MinCellTempNumbIterator' */
  uint8_T MinCellTempNumbIterator_Itera_j;/* '<S39>/MinCellTempNumbIterator' */
  uint8_T MinCellTempNumbIterator_Itera_b;/* '<S38>/MinCellTempNumbIterator' */
  DW_BMSDelay_CFM_T BMSDelay_cq;       /* '<S8>/BMSDelay' */
  DW_BMSDelay_CFM_T BMSDelay_h;        /* '<S7>/BMSDelay' */
  DW_BMSDelay_CFM_T BMSDelay_f;        /* '<S20>/BMSDelay' */
  DW_BMSDelay_CFM_T BMSDelay_b;        /* '<S18>/BMSDelay' */
  DW_BMSDelay_CFM_T BMSDelay_c;        /* '<S17>/BMSDelay' */
  DW_BMSDelay_CFM_T BMSDelay_n;        /* '<S16>/BMSDelay' */
  DW_BMSDelay_CFM_T BMSDelay_d;        /* '<S15>/BMSDelay' */
  DW_BMSDelay_CFM_T BMSDelay_a;        /* '<S5>/BMSDelay' */
  DW_BMSDelay_CFM_T BMSDelay;          /* '<S4>/BMSDelay' */
} DW_CFM_T;

/* External outputs (root outports fed by signals with auto storage) */
typedef struct {
  boolean_T GaCFM_AFEComLost_flg_l[8]; /* '<Root>/GaCFM_AFEComLost_flg' */
  boolean_T GaCFM_AFECellVoltUpdErr_flg_e[8];/* '<Root>/GaCFM_AFECellVoltUpdErr_flg' */
  boolean_T GaCFM_AFECellTempUpdErr_flg_k[8];/* '<Root>/GaCFM_AFECellTempUpdErr_flg' */
  boolean_T GaCFM_AFECellVoltLineOpen_flg_h[8];/* '<Root>/GaCFM_AFECellVoltLineOpen_flg' */
  boolean_T GaCFM_AFEGpioLineOpen_flg_k[8];/* '<Root>/GaCFM_AFEGpioLineOpen_flg' */
  boolean_T GaCFM_AFEAdcRelatedErr_flg_j[8];/* '<Root>/GaCFM_AFEAdcRelatedErr_flg' */
  boolean_T GaCFM_AFEDiagModeExitErr_flg_d[8];/* '<Root>/GaCFM_AFEDiagModeExitErr_flg' */
  boolean_T GaCFM_AFEOtherErr_flg_e[8];/* '<Root>/GaCFM_AFEOtherErr_flg' */
  boolean_T GaCFM_AFESampleErr_flg_c[8];/* '<Root>/GaCFM_AFESampleErr_flg' */
} ExtY_CFM_T;

/* Block signals (auto storage) */
extern B_CFM_T CFM_B;

/* Block states (auto storage) */
extern DW_CFM_T CFM_DW;

/* External outputs (root outports fed by signals with auto storage) */
extern ExtY_CFM_T CFM_Y;

/* Model entry point functions */
extern void CFM_initialize(void);

/* Exported entry point functions */
extern void CFM_CMCFltMag_20ms(void);

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'CFM'
 * '<S1>'   : 'CFM/CFM'
 * '<S2>'   : 'CFM/CFM/CMCFltMag_20ms'
 * '<S3>'   : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys'
 * '<S4>'   : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEComLost_Err'
 * '<S5>'   : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEDiagExit_Err'
 * '<S6>'   : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration'
 * '<S7>'   : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEOther_Err'
 * '<S8>'   : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFESample_Err'
 * '<S9>'   : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEComLost_Err/BMSDelay'
 * '<S10>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEComLost_Err/CFM_GaCFM_AFEComLost_flg'
 * '<S11>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEComLost_Err/BMSDelay/Unit Delay Resettable'
 * '<S12>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEDiagExit_Err/BMSDelay'
 * '<S13>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEDiagExit_Err/CFM_GaCFM_AFEDiagModeExitErr_flg'
 * '<S14>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEDiagExit_Err/BMSDelay/Unit Delay Resettable'
 * '<S15>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFEAdcRelatedErr_Debounce'
 * '<S16>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFECellTempUpd_Debounce'
 * '<S17>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFECellVoltLineOpen_Debounce'
 * '<S18>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFECellVoltUpd_Debounce'
 * '<S19>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFEErr_Iteration_sys'
 * '<S20>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFEGpioLineOpen_Debounce'
 * '<S21>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFEAdcRelatedErr_Debounce/BMSDelay'
 * '<S22>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFEAdcRelatedErr_Debounce/CFM_GaCFM_AFEAdcRelatedErr_flg'
 * '<S23>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFEAdcRelatedErr_Debounce/BMSDelay/Unit Delay Resettable'
 * '<S24>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFECellTempUpd_Debounce/BMSDelay'
 * '<S25>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFECellTempUpd_Debounce/CFM_GaCFM_AFECellTempUpdErr_flg'
 * '<S26>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFECellTempUpd_Debounce/BMSDelay/Unit Delay Resettable'
 * '<S27>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFECellVoltLineOpen_Debounce/BMSDelay'
 * '<S28>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFECellVoltLineOpen_Debounce/CFM_GaCFM_AFECellVoltLineOpen_flg'
 * '<S29>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFECellVoltLineOpen_Debounce/BMSDelay/Unit Delay Resettable'
 * '<S30>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFECellVoltUpd_Debounce/BMSDelay'
 * '<S31>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFECellVoltUpd_Debounce/CFM_GaCFM_AFECellVoltUpdErr_flg'
 * '<S32>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFECellVoltUpd_Debounce/BMSDelay/Unit Delay Resettable'
 * '<S33>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFEErr_Iteration_sys/AFEAdcRelatedErr'
 * '<S34>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFEErr_Iteration_sys/AFECellTempUpdErr'
 * '<S35>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFEErr_Iteration_sys/AFECellVoltLineOpenErr'
 * '<S36>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFEErr_Iteration_sys/AFECellVoltUpdErr'
 * '<S37>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFEErr_Iteration_sys/AFEGpioLineOpenErr'
 * '<S38>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFEErr_Iteration_sys/AFEAdcRelatedErr/AFEAdcRelatedErr_sys'
 * '<S39>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFEErr_Iteration_sys/AFECellTempUpdErr/AFECellTempUpdErr_sys'
 * '<S40>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFEErr_Iteration_sys/AFECellVoltLineOpenErr/AFECellVoltLineOpenErr_sys'
 * '<S41>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFEErr_Iteration_sys/AFECellVoltUpdErr/AFECellVoltUpdErr_sys'
 * '<S42>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFEErr_Iteration_sys/AFEGpioLineOpenErr/AFEGpioLineOpenErr_sys'
 * '<S43>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFEGpioLineOpen_Debounce/BMSDelay'
 * '<S44>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFEGpioLineOpen_Debounce/CFM_GaCFM_AFEGpioLineOpen_flg'
 * '<S45>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEErr_Iteration/AFEGpioLineOpen_Debounce/BMSDelay/Unit Delay Resettable'
 * '<S46>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEOther_Err/BMSDelay'
 * '<S47>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEOther_Err/CFM_GaCFM_AFEOtherErr_flg'
 * '<S48>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFEOther_Err/BMSDelay/Unit Delay Resettable'
 * '<S49>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFESample_Err/BMSDelay'
 * '<S50>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFESample_Err/CFM_GaCFM_AFESampleErr_flg'
 * '<S51>'  : 'CFM/CFM/CMCFltMag_20ms/CMCFltMag_20ms_sys/AFESample_Err/BMSDelay/Unit Delay Resettable'
 */

/*-
 * Requirements for '<Root>': CFM
 */
#endif                                 /* RTW_HEADER_CFM_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
