/*
 * File: HVSR_CrashChk_private.h
 *
 * Code generated for Simulink model 'HVSR_CrashChk'.
 *
 * Model version                  : 1.129
 * Simulink Coder version         : 8.13 (R2017b) 24-Jul-2017
 * C/C++ source code generated on : Mon Feb 22 11:19:42 2021
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#ifndef RTW_HEADER_HVSR_CrashChk_private_h_
#define RTW_HEADER_HVSR_CrashChk_private_h_
#include "rtwtypes.h"

/* Exported data declaration */

/* Declaration for custom storage class: InputSignal */
extern volatile boolean_T BSPR_bKl15WkUp;
extern volatile real32_T BSPR_dcCrashPwmDuty;/* Duty cycle of crash signal input */
extern volatile real32_T BSPR_dcCrashPwmDutyOutDet;/* Duty cycle of crash signal output feedback */
extern volatile real32_T BSPR_fCrashPwmFrq;/* Frequency cycle of crash signal input */
extern volatile real32_T BSPR_fCrashPwmFrqOutDet;/* State of crash signal output feedback */
extern volatile boolean_T BSPR_flgGwAbmVld;/* State of crash signal input */
extern volatile uint8_T BSPR_stCrashOutpFdbk;/* Frequency cycle of crash signal output feedback */
extern volatile uint16_T COMR_YearSet;
extern volatile uint8_T COMR_stCrashSgl;
extern volatile boolean_T GcISP_ChkSumMsg050_numb;
extern volatile boolean_T GcISP_RcMsg050_numb;
extern volatile uint8_T GeRTE_PrjEdition_enum;

#endif                                 /* RTW_HEADER_HVSR_CrashChk_private_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
