/*
 * File: BSPR_BattCurrCoord.h
 *
 * Code generated for Simulink model 'BSPR_BattCurrCoord'.
 *
 * Model version                  : 1.1181
 * Simulink Coder version         : 8.13 (R2017b) 24-Jul-2017
 * C/C++ source code generated on : Mon Aug  2 17:32:11 2021
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#ifndef RTW_HEADER_BSPR_BattCurrCoord_h_
#define RTW_HEADER_BSPR_BattCurrCoord_h_
#include <math.h>
#ifndef BSPR_BattCurrCoord_COMMON_INCLUDES_
# define BSPR_BattCurrCoord_COMMON_INCLUDES_
#include "rtwtypes.h"
#endif                                 /* BSPR_BattCurrCoord_COMMON_INCLUDES_ */

#include "BSPR_BattCurrCoord_types.h"

/* Includes for objects with custom storage classes. */
#include "BSPR_BattCurrCoordParameter.h"

/* Macros for accessing real-time model data structure */

/* user code (top of header file) */
#include "ASW_Interface.h"

/* Block signals (auto storage) */
typedef struct {
  boolean_T LogicalOperator1;          /* '<S6>/Logical Operator1' */
} B_BSPR_BattCurrCoord_T;

/* Block states (auto storage) for system '<Root>' */
typedef struct {
  real32_T Delay_DSTATE;               /* '<S126>/Delay' */
  real32_T Delay_DSTATE_c;             /* '<S118>/Delay' */
  real32_T Delay_DSTATE_e;             /* '<S117>/Delay' */
  real32_T Delay_DSTATE_k;             /* '<S109>/Delay' */
  real32_T Delay_DSTATE_b;             /* '<S108>/Delay' */
  real32_T Delay_DSTATE_ex;            /* '<S94>/Delay' */
  real32_T Delay_DSTATE_i;             /* '<S93>/Delay' */
  real32_T Delay_DSTATE_g;             /* '<S92>/Delay' */
  real32_T Delay_DSTATE_g5;            /* '<S91>/Delay' */
  real32_T Delay_DSTATE_cl;            /* '<S80>/Delay' */
  real32_T Delay_DSTATE_o;             /* '<S79>/Delay' */
  real32_T Delay_DSTATE_id;            /* '<S70>/Delay' */
  real32_T Delay_DSTATE_h;             /* '<S69>/Delay' */
  real32_T Delay_DSTATE_j;             /* '<S48>/Delay' */
  real32_T Delay_DSTATE_ja;            /* '<S47>/Delay' */
  real32_T Delay_DSTATE_d;             /* '<S46>/Delay' */
  real32_T Delay_DSTATE_a;             /* '<S45>/Delay' */
  real32_T Delay_DSTATE_bu;            /* '<S44>/Delay' */
  real32_T Delay_DSTATE_ke;            /* '<S43>/Delay' */
  real32_T Delay_DSTATE_av;            /* '<S33>/Delay' */
  real32_T Delay_DSTATE_o3;            /* '<S32>/Delay' */
  real32_T Delay_DSTATE_o1;            /* '<S14>/Delay' */
  real32_T Delay_DSTATE_f;             /* '<S13>/Delay' */
  real32_T UnitDelay3_DSTATE;          /* '<S4>/Unit Delay3' */
  real32_T UnitDelay7_DSTATE;          /* '<S4>/Unit Delay7' */
  real32_T UnitDelay10_DSTATE;         /* '<S4>/Unit Delay10' */
  real32_T UnitDelay1_DSTATE;          /* '<S4>/Unit Delay1' */
  real32_T UnitDelay9_DSTATE;          /* '<S4>/Unit Delay9' */
  real32_T UnitDelay16_DSTATE;         /* '<S4>/Unit Delay16' */
  real32_T UnitDelay13_DSTATE;         /* '<S4>/Unit Delay13' */
  real32_T UnitDelay14_DSTATE;         /* '<S4>/Unit Delay14' */
  real32_T UnitDelay15_DSTATE;         /* '<S4>/Unit Delay15' */
  uint32_T UnitDelay5_DSTATE;          /* '<S4>/Unit Delay5' */
  uint32_T UnitDelay6_DSTATE;          /* '<S4>/Unit Delay6' */
  uint32_T UnitDelay8_DSTATE;          /* '<S4>/Unit Delay8' */
  uint32_T UnitDelay11_DSTATE;         /* '<S4>/Unit Delay11' */
  uint32_T UnitDelay12_DSTATE;         /* '<S4>/Unit Delay12' */
  real32_T buffer[5];                  /* '<S125>/Chart' */
  real32_T sum;                        /* '<S125>/Chart' */
  real32_T BSPR_tiCurrAdapAllw;        /* '<S5>/AdapOs' */
  uint16_T count;                      /* '<S125>/Chart' */
  uint16_T index;                      /* '<S125>/Chart' */
  uint8_T Delay3_DSTATE;               /* '<S116>/Delay3' */
  uint8_T Delay3_DSTATE_j;             /* '<S107>/Delay3' */
  uint8_T Delay3_DSTATE_h;             /* '<S90>/Delay3' */
  uint8_T Delay3_DSTATE_a;             /* '<S89>/Delay3' */
  uint8_T Delay3_DSTATE_e;             /* '<S78>/Delay3' */
  uint8_T Delay3_DSTATE_k;             /* '<S68>/Delay3' */
  uint8_T Delay3_DSTATE_n;             /* '<S42>/Delay3' */
  uint8_T Delay3_DSTATE_c;             /* '<S41>/Delay3' */
  uint8_T Delay3_DSTATE_kw;            /* '<S40>/Delay3' */
  uint8_T Delay3_DSTATE_f;             /* '<S31>/Delay3' */
  uint8_T Delay3_DSTATE_p;             /* '<S12>/Delay3' */
  uint8_T UnitDelay4_DSTATE;           /* '<S4>/Unit Delay4' */
  uint8_T Delay1_DSTATE;               /* '<S9>/Delay1' */
  boolean_T UnitDelay12_DSTATE_e;      /* '<S7>/Unit Delay12' */
  boolean_T Delay1_DSTATE_d;           /* '<S11>/Delay1' */
  boolean_T UnitDelay_DSTATE;          /* '<S22>/Unit Delay' */
  boolean_T Delay2_DSTATE;             /* '<S116>/Delay2' */
  boolean_T Delay2_DSTATE_f;           /* '<S107>/Delay2' */
  boolean_T Delay2_DSTATE_h;           /* '<S90>/Delay2' */
  boolean_T Delay2_DSTATE_ha;          /* '<S89>/Delay2' */
  boolean_T Delay2_DSTATE_d;           /* '<S78>/Delay2' */
  boolean_T Delay2_DSTATE_a;           /* '<S68>/Delay2' */
  boolean_T Delay2_DSTATE_c;           /* '<S42>/Delay2' */
  boolean_T Delay2_DSTATE_n;           /* '<S41>/Delay2' */
  boolean_T Delay2_DSTATE_l;           /* '<S40>/Delay2' */
  boolean_T Delay2_DSTATE_m;           /* '<S31>/Delay2' */
  boolean_T Delay2_DSTATE_k;           /* '<S12>/Delay2' */
  uint8_T is_active_c3_BSPR_BattCurrCoord;/* '<S5>/AdapOs' */
  uint8_T is_c3_BSPR_BattCurrCoord;    /* '<S5>/AdapOs' */
  uint8_T ini_counter;                 /* '<S5>/AdapOs' */
} DW_BSPR_BattCurrCoord_T;

/* Block signals (auto storage) */
extern B_BSPR_BattCurrCoord_T BSPR_BattCurrCoord_B;

/* Block states (auto storage) */
extern DW_BSPR_BattCurrCoord_T BSPR_BattCurrCoord_DW;

/* Model entry point functions */
extern void BSPR_BattCurrCoord_initialize(void);
extern void BSPR_BattCurrCoord_step(void);

/* Exported data declaration */

/* Volatile memory section */
#define ASW1_OEM_START_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: Volatile */
extern volatile real32_T BSPR_iCurrOfsAdap;/* Self-adaption current for battery current sensor */
extern volatile uint8_T DFC_BMSSplyPwrAbnToCAB_ASW;
extern volatile uint8_T DFC_BMSSplyPwrAbnToLem_ASW;
extern volatile uint8_T DFC_BattCurrMismatchErr_ASW;
extern volatile uint8_T DFC_CABDevFlt_ASW;
extern volatile uint8_T DFC_CABErr_ASW;
extern volatile uint8_T DFC_CABVoltOutOfRng_ASW;
extern volatile uint8_T DFC_CurrRngErr_ASW;/* Currrent out of range fault */
extern volatile uint8_T DFC_HwCurrElecSCG_ASW;
extern volatile uint8_T DFC_HwCurrElecSCP_ASW;
extern volatile uint8_T DFC_PackCrntSaf_ASW;
extern volatile uint8_T DFC_TwoCurrSnsrFlt_ASW;

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"
#define ASW1_OEM_START_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: OutputSignal */
extern volatile boolean_T BSPR_TwoCurrSnsrFlt_flg;
extern volatile boolean_T BSPR_bBattMismatchErrDet;
extern volatile boolean_T BSPR_bBattMismatchErrHeal;
extern volatile boolean_T BSPR_bCABCurrVld;
extern volatile boolean_T BSPR_bCabErrDet;
extern volatile boolean_T BSPR_bCabErrHeal;
extern volatile boolean_T BSPR_bCurrAdapCalcEn;/* Condition for battery current self-adaption */
extern volatile boolean_T BSPR_bCurrAdapCoordEn;/* Condition for battery current self-adaption */
extern volatile boolean_T BSPR_bCurrAdapEn;/* Condition for battery current self-adaption */
extern volatile boolean_T BSPR_bCurrRngChkErr;/* Error flag for current sensor out of range check */
extern volatile boolean_T BSPR_bCurrRngChkOk;/* Ok flag for current sensor out of range check */
extern volatile boolean_T BSPR_bHwCurrElecSCPErrDet;
extern volatile boolean_T BSPR_bHwCurrElecSCPErrHeal;
extern volatile boolean_T BSPR_bHwCurrVld;
extern volatile uint32_T BSPR_cntCurrStbCalc;/*  Stable period statistics for battery current sensor self-adaption */
extern volatile uint32_T BSPR_cntCurrStbPerCalc;/* Total period  statistics for battery current sensor self-adaption */
extern volatile real32_T BSPR_iBattCurr;/* Battery current after coordinating */
extern volatile real32_T BSPR_iBattCurrCalc;
extern volatile real32_T BSPR_iBattCurrFil;
extern volatile real32_T BSPR_iBattCurrRaw;
extern volatile real32_T BSPR_iCurrStbAvrgCalc;/* Average current during battery current sensor self-adaption */
extern volatile real32_T BSPR_iCurrStbMaxCalc;/* Max current during battery current sensor self-adaption */
extern volatile real32_T BSPR_iCurrStbMinCalc;/* Min current during battery current sensor self-adaption */
extern volatile uint8_T BSPR_stBattCurrMismatchErr;
extern volatile uint8_T BSPR_stCABErr;

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'BSPR_BattCurrCoord'
 * '<S1>'   : 'BSPR_BattCurrCoord/BattCurrCoord'
 * '<S2>'   : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrAdap'
 * '<S3>'   : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc'
 * '<S4>'   : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrAdap/AdapCalc'
 * '<S5>'   : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrAdap/AdapOs'
 * '<S6>'   : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrAdap/AdptCoord'
 * '<S7>'   : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrAdap/AdptProc'
 * '<S8>'   : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrAdap/RngChk'
 * '<S9>'   : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrAdap/AdapCalc/EdgeFalling'
 * '<S10>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrAdap/AdapOs/AdapOs'
 * '<S11>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrAdap/AdptProc/EdgeRising'
 * '<S12>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrAdap/RngChk/DSM_ReportCheck'
 * '<S13>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrAdap/RngChk/TONV_10msTimeDebounce'
 * '<S14>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrAdap/RngChk/TONV_10msTimeDebounce1'
 * '<S15>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrAdap/RngChk/DSM_ReportCheck/Bit Clear1'
 * '<S16>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrAdap/RngChk/DSM_ReportCheck/Bit Clear2'
 * '<S17>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrAdap/RngChk/DSM_ReportCheck/Bit Set'
 * '<S18>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrAdap/RngChk/DSM_ReportCheck/Bit Set1'
 * '<S19>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrAdap/RngChk/DSM_ReportCheck/Bit Set2'
 * '<S20>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrAdap/RngChk/DSM_ReportCheck/Bit Set4'
 * '<S21>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck'
 * '<S22>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/CABLEM_SW'
 * '<S23>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/BattCurrMismatchErr'
 * '<S24>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC'
 * '<S25>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrStatus'
 * '<S26>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CurrSnsrFlt'
 * '<S27>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk'
 * '<S28>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/SupplyDTC'
 * '<S29>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/SysOverCurrDet'
 * '<S30>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/BattCurrMismatchErr/Compare To Constant3'
 * '<S31>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/BattCurrMismatchErr/DSM_ReportCheck'
 * '<S32>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/BattCurrMismatchErr/TONV_10msTimeDebounce'
 * '<S33>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/BattCurrMismatchErr/TONV_10msTimeDebounce1'
 * '<S34>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/BattCurrMismatchErr/DSM_ReportCheck/Bit Clear1'
 * '<S35>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/BattCurrMismatchErr/DSM_ReportCheck/Bit Clear2'
 * '<S36>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/BattCurrMismatchErr/DSM_ReportCheck/Bit Set'
 * '<S37>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/BattCurrMismatchErr/DSM_ReportCheck/Bit Set1'
 * '<S38>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/BattCurrMismatchErr/DSM_ReportCheck/Bit Set2'
 * '<S39>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/BattCurrMismatchErr/DSM_ReportCheck/Bit Set4'
 * '<S40>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck'
 * '<S41>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck1'
 * '<S42>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck2'
 * '<S43>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/TONV_10msTimeDebounce'
 * '<S44>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/TONV_10msTimeDebounce1'
 * '<S45>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/TONV_10msTimeDebounce2'
 * '<S46>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/TONV_10msTimeDebounce3'
 * '<S47>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/TONV_10msTimeDebounce4'
 * '<S48>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/TONV_10msTimeDebounce5'
 * '<S49>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck/Bit Clear1'
 * '<S50>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck/Bit Clear2'
 * '<S51>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck/Bit Set'
 * '<S52>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck/Bit Set1'
 * '<S53>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck/Bit Set2'
 * '<S54>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck/Bit Set4'
 * '<S55>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck1/Bit Clear1'
 * '<S56>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck1/Bit Clear2'
 * '<S57>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck1/Bit Set'
 * '<S58>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck1/Bit Set1'
 * '<S59>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck1/Bit Set2'
 * '<S60>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck1/Bit Set4'
 * '<S61>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck2/Bit Clear1'
 * '<S62>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck2/Bit Clear2'
 * '<S63>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck2/Bit Set'
 * '<S64>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck2/Bit Set1'
 * '<S65>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck2/Bit Set2'
 * '<S66>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrDTC/DSM_ReportCheck2/Bit Set4'
 * '<S67>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrStatus/Compare To Constant3'
 * '<S68>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrStatus/DSM_ReportCheck'
 * '<S69>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrStatus/TONV_10msTimeDebounce'
 * '<S70>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrStatus/TONV_10msTimeDebounce1'
 * '<S71>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrStatus/DSM_ReportCheck/Bit Clear1'
 * '<S72>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrStatus/DSM_ReportCheck/Bit Clear2'
 * '<S73>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrStatus/DSM_ReportCheck/Bit Set'
 * '<S74>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrStatus/DSM_ReportCheck/Bit Set1'
 * '<S75>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrStatus/DSM_ReportCheck/Bit Set2'
 * '<S76>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CabErrStatus/DSM_ReportCheck/Bit Set4'
 * '<S77>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CurrSnsrFlt/Compare To Constant1'
 * '<S78>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CurrSnsrFlt/DSM_ReportCheck'
 * '<S79>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CurrSnsrFlt/TONV_10msTimeDebounce1'
 * '<S80>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CurrSnsrFlt/TONV_10msTimeDebounce2'
 * '<S81>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CurrSnsrFlt/DSM_ReportCheck/Bit Clear1'
 * '<S82>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CurrSnsrFlt/DSM_ReportCheck/Bit Clear2'
 * '<S83>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CurrSnsrFlt/DSM_ReportCheck/Bit Set'
 * '<S84>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CurrSnsrFlt/DSM_ReportCheck/Bit Set1'
 * '<S85>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CurrSnsrFlt/DSM_ReportCheck/Bit Set2'
 * '<S86>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/CurrSnsrFlt/DSM_ReportCheck/Bit Set4'
 * '<S87>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk/Compare To Constant1'
 * '<S88>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk/Compare To Constant3'
 * '<S89>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk/DSM_ReportCheck'
 * '<S90>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk/DSM_ReportCheck1'
 * '<S91>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk/TONV_10msTimeDebounce'
 * '<S92>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk/TONV_10msTimeDebounce1'
 * '<S93>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk/TONV_10msTimeDebounce2'
 * '<S94>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk/TONV_10msTimeDebounce3'
 * '<S95>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk/DSM_ReportCheck/Bit Clear1'
 * '<S96>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk/DSM_ReportCheck/Bit Clear2'
 * '<S97>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk/DSM_ReportCheck/Bit Set'
 * '<S98>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk/DSM_ReportCheck/Bit Set1'
 * '<S99>'  : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk/DSM_ReportCheck/Bit Set2'
 * '<S100>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk/DSM_ReportCheck/Bit Set4'
 * '<S101>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk/DSM_ReportCheck1/Bit Clear1'
 * '<S102>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk/DSM_ReportCheck1/Bit Clear2'
 * '<S103>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk/DSM_ReportCheck1/Bit Set'
 * '<S104>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk/DSM_ReportCheck1/Bit Set1'
 * '<S105>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk/DSM_ReportCheck1/Bit Set2'
 * '<S106>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/HwCurrChk/DSM_ReportCheck1/Bit Set4'
 * '<S107>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/SupplyDTC/DSM_ReportCheck'
 * '<S108>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/SupplyDTC/TONV_10msTimeDebounce'
 * '<S109>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/SupplyDTC/TONV_10msTimeDebounce1'
 * '<S110>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/SupplyDTC/DSM_ReportCheck/Bit Clear1'
 * '<S111>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/SupplyDTC/DSM_ReportCheck/Bit Clear2'
 * '<S112>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/SupplyDTC/DSM_ReportCheck/Bit Set'
 * '<S113>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/SupplyDTC/DSM_ReportCheck/Bit Set1'
 * '<S114>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/SupplyDTC/DSM_ReportCheck/Bit Set2'
 * '<S115>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/SupplyDTC/DSM_ReportCheck/Bit Set4'
 * '<S116>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/SysOverCurrDet/DSM_ReportCheck'
 * '<S117>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/SysOverCurrDet/TONV_10msTimeDebounce'
 * '<S118>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/SysOverCurrDet/TONV_10msTimeDebounce1'
 * '<S119>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/SysOverCurrDet/DSM_ReportCheck/Bit Clear1'
 * '<S120>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/SysOverCurrDet/DSM_ReportCheck/Bit Clear2'
 * '<S121>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/SysOverCurrDet/DSM_ReportCheck/Bit Set'
 * '<S122>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/SysOverCurrDet/DSM_ReportCheck/Bit Set1'
 * '<S123>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/SysOverCurrDet/DSM_ReportCheck/Bit Set2'
 * '<S124>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/BattCurrCheck/SysOverCurrDet/DSM_ReportCheck/Bit Set4'
 * '<S125>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/CABLEM_SW/Moving Average'
 * '<S126>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/CABLEM_SW/TONV_10msTimeDebounce1'
 * '<S127>' : 'BSPR_BattCurrCoord/BattCurrCoord/BattCurrCalc/CABLEM_SW/Moving Average/Chart'
 */
#endif                                 /* RTW_HEADER_BSPR_BattCurrCoord_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
