/*
 * File: BSPR_BattCurrDiag.h
 *
 * Code generated for Simulink model 'BSPR_BattCurrDiag'.
 *
 * Model version                  : A1.3_0
 * Simulink Coder version         : 8.11 (R2016b) 25-Aug-2016
 * C/C++ source code generated on : Sun Aug 16 22:05:12 2020
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#ifndef RTW_HEADER_BSPR_BattCurrDiag_h_
#define RTW_HEADER_BSPR_BattCurrDiag_h_
#include <math.h>
#include <stddef.h>
#ifndef BSPR_BattCurrDiag_COMMON_INCLUDES_
# define BSPR_BattCurrDiag_COMMON_INCLUDES_
#include "rtwtypes.h"
#include "zero_crossing_types.h"
#endif                                 /* BSPR_BattCurrDiag_COMMON_INCLUDES_ */

#include "BSPR_BattCurrDiag_types.h"

/* Includes for objects with custom storage classes. */
#include "BSPR_BattCurrDiagParameter.h"

/* Macros for accessing real-time model data structure */

/* user code (top of header file) */
#include "ASW_Interface.h"

/* Block signals (auto storage) */
typedef struct {
  boolean_T RelationalOperator;        /* '<S8>/Relational Operator' */
  boolean_T LogicalOperator;           /* '<S8>/Logical Operator' */
  boolean_T LogicalOperator1;          /* '<S7>/Logical Operator1' */
  boolean_T LogicalOperator_o;         /* '<S7>/Logical Operator' */
  boolean_T LogicalOperator1_l;        /* '<S6>/Logical Operator1' */
  boolean_T RelationalOperator_p;      /* '<S17>/Relational Operator' */
} B_BSPR_BattCurrDiag_T;

/* Block states (auto storage) for system '<Root>' */
typedef struct {
  real32_T Delay_DSTATE;                 /* '<S15>/Delay' */
  real32_T Delay_DSTATE_j;             /* '<S47>/Delay' */
  real32_T Delay_DSTATE_k;             /* '<S46>/Delay' */
  real32_T Delay_DSTATE_p;             /* '<S45>/Delay' */
  real32_T Delay_DSTATE_po;            /* '<S44>/Delay' */
  real32_T Delay_DSTATE_i;             /* '<S17>/Delay' */
  real32_T Delay_DSTATE_l;             /* '<S16>/Delay' */
  real32_T UnitDelay_DSTATE;           /* '<S15>/Unit Delay' */
  uint8_T Delay3_DSTATE;               /* '<S20>/Delay3' */
  uint8_T Delay3_DSTATE_g;             /* '<S19>/Delay3' */
  uint8_T Delay3_DSTATE_i;             /* '<S18>/Delay3' */
  boolean_T Delay2_DSTATE;             /* '<S20>/Delay2' */
  boolean_T Delay2_DSTATE_l;           /* '<S19>/Delay2' */
  boolean_T Delay2_DSTATE_f;           /* '<S18>/Delay2' */
} DW_BSPR_BattCurrDiag_T;

/* Zero-crossing (trigger) state */
typedef struct {
  ZCSigState FunctionCallSubsystem3_Trig_ZCE;/* '<S10>/Function-Call Subsystem3' */
  ZCSigState FunctionCallSubsystem2_Trig_ZCE;/* '<S10>/Function-Call Subsystem2' */
  ZCSigState FunctionCallSubsystem1_Trig_ZCE;/* '<S10>/Function-Call Subsystem1' */
  ZCSigState FunctionCallSubsystem_Trig_ZCE;/* '<S10>/Function-Call Subsystem' */
} PrevZCX_BSPR_BattCurrDiag_T;

/* Block signals (auto storage) */
extern B_BSPR_BattCurrDiag_T BSPR_BattCurrDiag_B;

/* Block states (auto storage) */
extern DW_BSPR_BattCurrDiag_T BSPR_BattCurrDiag_DW;

/*
 * Exported Global Signals
 *
 * Note: Exported global signals are block signals with an exported global
 * storage class designation.  Code generation will declare the memory for
 * these signals and export their symbols.
 *
 */
extern real32_T BSPR_iCurrMxStuk;      /* '<S10>/MinMax' */
extern real32_T BSPR_iCurrMnStuk;      /* '<S10>/MinMax1' */
extern uint8_T BSPR_cntCurrPedStukLo;  /* '<S43>/Add' */
extern uint8_T BSPR_cntCurrPedStukUp;  /* '<S42>/Add' */
extern uint8_T BSPR_cntCurrVehStukLo;  /* '<S41>/Add' */
extern uint8_T BSPR_cntCurrVehStukUp;  /* '<S40>/Add' */
extern boolean_T BSPR_bCurrDiagStukEn; /* '<S10>/Logical Operator10' */
extern boolean_T BSPR_bCurrDiagChrgPlausEn;/* '<S5>/Logical Operator' */

/* Model entry point functions */
extern void BSPR_BattCurrDiag_initialize(void);
extern void BSPR_BattCurrDiag_step(void);

/* Exported data declaration */

/* Volatile memory section */
/* Declaration for custom storage class: Volatile */
extern volatile uint8_T DFC_CurrChrgPlaus_ASW;
extern volatile uint8_T DFC_CurrOffsPlaus_ASW;
extern volatile uint8_T DFC_CurrStukPlaus_ASW;

/* Declaration for custom storage class: OutputSignal */
extern volatile boolean_T BSPR_bCurrChrgPlausDet;/* Condition for battery current charge fault */
extern volatile boolean_T BSPR_bCurrChrgPlausHeal;/* Condition for battery current charge healing */
extern volatile boolean_T BSPR_bCurrOffsDet;/* Condition for battery current offset fault */
extern volatile boolean_T BSPR_bCurrOffsHeal;/* Condition for battery current offset healing */
extern volatile boolean_T BSPR_bCurrStukDet;/* Condition for battery current stuck fault */
extern volatile boolean_T BSPR_bCurrStukHeal;/* Condition for battery current stuck healing */

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'BSPR_BattCurrDiag'
 * '<S1>'   : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag'
 * '<S2>'   : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/CWChrg'
 * '<S3>'   : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/CWOffs'
 * '<S4>'   : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/CWStuk'
 * '<S5>'   : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/ChrgPlausEna'
 * '<S6>'   : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/DiagChrgCurr'
 * '<S7>'   : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/DiagOffs'
 * '<S8>'   : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/DiagStuck'
 * '<S9>'   : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM'
 * '<S10>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/StuckEna'
 * '<S11>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/CWChrg/Compare To Constant'
 * '<S12>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/CWOffs/Compare To Constant'
 * '<S13>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/CWStuk/Compare To Constant'
 * '<S14>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/ChrgPlausEna/Compare To Constant'
 * '<S15>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/ChrgPlausEna/K_Lowpass'
 * '<S16>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/ChrgPlausEna/TONV_VariableTimeDebounce1'
 * '<S17>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/DiagChrgCurr/TONV_VariableTimeDebounce1'
 * '<S18>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck1'
 * '<S19>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck3'
 * '<S20>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck4'
 * '<S21>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck1/Bit Clear1'
 * '<S22>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck1/Bit Clear2'
 * '<S23>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck1/Bit Set'
 * '<S24>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck1/Bit Set1'
 * '<S25>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck1/Bit Set2'
 * '<S26>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck1/Bit Set4'
 * '<S27>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck3/Bit Clear1'
 * '<S28>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck3/Bit Clear2'
 * '<S29>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck3/Bit Set'
 * '<S30>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck3/Bit Set1'
 * '<S31>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck3/Bit Set2'
 * '<S32>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck3/Bit Set4'
 * '<S33>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck4/Bit Clear1'
 * '<S34>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck4/Bit Clear2'
 * '<S35>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck4/Bit Set'
 * '<S36>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck4/Bit Set1'
 * '<S37>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck4/Bit Set2'
 * '<S38>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/RptDSM/DSM_ReportCheck4/Bit Set4'
 * '<S39>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/StuckEna/Compare To Constant3'
 * '<S40>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/StuckEna/Function-Call Subsystem'
 * '<S41>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/StuckEna/Function-Call Subsystem1'
 * '<S42>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/StuckEna/Function-Call Subsystem2'
 * '<S43>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/StuckEna/Function-Call Subsystem3'
 * '<S44>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/StuckEna/TONV_VariableTimeDebounce'
 * '<S45>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/StuckEna/TONV_VariableTimeDebounce1'
 * '<S46>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/StuckEna/TONV_VariableTimeDebounce2'
 * '<S47>'  : 'BSPR_BattCurrDiag/BSPR_BattCurrDiag/StuckEna/TONV_VariableTimeDebounce3'
 */
#endif                                 /* RTW_HEADER_BSPR_BattCurrDiag_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
