/*
 * File: BCMR_DChrgGbFlow.h
 *
 * Code generated for Simulink model 'BCMR_DChrgGbFlow'.
 *
 * Model version                  : 1.299
 * Simulink Coder version         : 8.11 (R2016b) 25-Aug-2016
 * C/C++ source code generated on : Wed Nov 17 15:49:51 2021
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#ifndef RTW_HEADER_BCMR_DChrgGbFlow_h_
#define RTW_HEADER_BCMR_DChrgGbFlow_h_
#include <math.h>
#include <stddef.h>
#ifndef BCMR_DChrgGbFlow_COMMON_INCLUDES_
# define BCMR_DChrgGbFlow_COMMON_INCLUDES_
#include "rtwtypes.h"
#endif                                 /* BCMR_DChrgGbFlow_COMMON_INCLUDES_ */

#include "BCMR_DChrgGbFlow_types.h"

/* Includes for objects with custom storage classes. */
#include "dchrg_gbflow_parameters.h"

/* Macros for accessing real-time model data structure */

/* user code (top of header file) */
#include "ASW_Interface.h"

/* Block signals (auto storage) */
typedef struct {
  uint8_T BCMR_stDChrgElockReq_p;      /* '<S3>/DcChrgStateFlow' */
  boolean_T BCMR_bDChrgIsoStopCmd_e;   /* '<S3>/DcChrgStateFlow' */
  boolean_T BCMR_bDChrgFul_j;          /* '<S3>/DcChrgStateFlow' */
} B_BCMR_DChrgGbFlow_T;

/* Block states (auto storage) for system '<Root>' */
typedef struct {
  real32_T UnitDelay_DSTATE;           /* '<S17>/Unit Delay' */
  real32_T BCMR_IsoSWTimeCnt;          /* '<S3>/DcChrgStateFlow' */
  uint32_T temporalCounter_i1;         /* '<S3>/DcChrgStateFlow' */
  uint32_T temporalCounter_i2;         /* '<S3>/DcChrgStateFlow' */
  uint32_T temporalCounter_i3;         /* '<S3>/DcChrgStateFlow' */
  uint16_T FixPtUnitDelay1_DSTATE;     /* '<S14>/FixPt Unit Delay1' */
  uint16_T Local_cntSysStartCnt;       /* '<S3>/DcChrgStateFlow' */
  uint16_T Local_cntBroTxCnt;          /* '<S3>/DcChrgStateFlow' */
  uint8_T FixPtUnitDelay2_DSTATE;      /* '<S14>/FixPt Unit Delay2' */
  boolean_T StateName;                 /* '<S7>/Unit Delay1' */
  boolean_T Delay2_DSTATE;             /* '<S8>/Delay2' */
  boolean_T Delay1_DSTATE;             /* '<S15>/Delay1' */
  uint8_T is_active_c1_BCMR_DChrgGbFlow;/* '<S3>/DcChrgStateFlow' */
  uint8_T is_c1_BCMR_DChrgGbFlow;      /* '<S3>/DcChrgStateFlow' */
  uint8_T is_MsgMutual;                /* '<S3>/DcChrgStateFlow' */
  uint8_T is_DChrgHandOvr;             /* '<S3>/DcChrgStateFlow' */
  uint8_T is_DChrgParaConfig;          /* '<S3>/DcChrgStateFlow' */
  uint8_T is_DChrgRelayControl;        /* '<S3>/DcChrgStateFlow' */
  uint8_T is_DChrging;                 /* '<S3>/DcChrgStateFlow' */
  uint8_T is_DChrgStop;                /* '<S3>/DcChrgStateFlow' */
  uint8_T is_DChrgEnd;                 /* '<S3>/DcChrgStateFlow' */
  uint8_T is_DChrgRelayOpen;           /* '<S3>/DcChrgStateFlow' */
  uint8_T is_TimeOutOpen;              /* '<S3>/DcChrgStateFlow' */
  uint8_T is_RelayOpen;                /* '<S3>/DcChrgStateFlow' */
  uint8_T is_TimeOutOpen_m;            /* '<S3>/DcChrgStateFlow' */
  uint8_T is_NonTimeOutOpen;           /* '<S3>/DcChrgStateFlow' */
  uint8_T is_TimeOutDChrgEnd;          /* '<S3>/DcChrgStateFlow' */
  uint8_T BEM_TimeOutLv;               /* '<S3>/DcChrgStateFlow' */
  uint8_T is_active_c3_BCMR_DChrgGbFlow;/* '<S1>/DChrgEna' */
  uint8_T is_c3_BCMR_DChrgGbFlow;      /* '<S1>/DChrgEna' */
} DW_BCMR_DChrgGbFlow_T;

/* Block signals (auto storage) */
extern B_BCMR_DChrgGbFlow_T BCMR_DChrgGbFlow_B;

/* Block states (auto storage) */
extern DW_BCMR_DChrgGbFlow_T BCMR_DChrgGbFlow_DW;

/*
 * Exported Global Signals
 *
 * Note: Exported global signals are block signals with an exported global
 * storage class designation.  Code generation will declare the memory for
 * these signals and export their symbols.
 *
 */
extern real32_T BCMR_cntDcAftTxBst;    /* '<S3>/DcChrgStateFlow' */
extern real32_T BCMR_cntDcAftRxCst;    /* '<S3>/DcChrgStateFlow' */
extern real32_T BCMR_cntDcAftTxBem;    /* '<S3>/DcChrgStateFlow' */
extern uint8_T BCMR_cntTimeOutCnt;     /* '<S3>/DcChrgStateFlow' */
extern boolean_T BCMR_bDChrgFulRaw;    /* '<S3>/Logical Operator' */

/* Model entry point functions */
extern void BCMR_DChrgGbFlow_initialize(void);
extern void BCMR_DChrgGbFlow_step(void);

/* Exported data declaration */
#define ASW1_OEM_START_SEC_DEFAULT_RAM1_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: OutputSignal */
extern volatile boolean_T BCMR_bDChrgAbrtWait;
extern volatile boolean_T BCMR_bDChrgFul;
extern volatile boolean_T BCMR_bDChrgIsoStopCmd;
extern volatile boolean_T BCMR_bDChrgPwrDwnReq;
extern volatile boolean_T BCMR_bDChrgPwrUpReq;
extern volatile boolean_T BCMR_bDChrgRdy;
extern volatile boolean_T BCMR_flgDChrgStopBActive;
extern volatile boolean_T BCMR_flgDChrgStopCActive;
extern volatile boolean_T BCMR_flgDChrgVer2015;
extern volatile boolean_T BCMR_flgReConnectFail;
extern volatile boolean_T BCMR_flgTxBCL;
extern volatile boolean_T BCMR_flgTxBCP;
extern volatile boolean_T BCMR_flgTxBCS;
extern volatile boolean_T BCMR_flgTxBEM;
extern volatile boolean_T BCMR_flgTxBHM;
extern volatile boolean_T BCMR_flgTxBRM;
extern volatile boolean_T BCMR_flgTxBRO;
extern volatile boolean_T BCMR_flgTxBSD;
extern volatile boolean_T BCMR_flgTxBSM;
extern volatile boolean_T BCMR_flgTxBST;
extern volatile uint8_T BCMR_stBmsRdyBro;
extern volatile uint8_T BCMR_stDChrgDebugOut;
extern volatile uint8_T BCMR_stDChrgElockReq;
extern volatile uint8_T BCMR_stDChrgGbFlowTimeout;
extern volatile uint8_T BCMR_stDChrgMode;
extern volatile uint8_T BCMR_stOtherErrBem;
extern volatile uint8_T BCMR_stSpn3901TimeoutBem;
extern volatile uint8_T BCMR_stSpn3902TimeoutBem;
extern volatile uint8_T BCMR_stSpn3903TimeoutBem;
extern volatile uint8_T BCMR_stSpn3904TimeoutBem;
extern volatile uint8_T BCMR_stSpn3905TimeoutBem;
extern volatile uint8_T BCMR_stSpn3906TimeoutBem;
extern volatile uint8_T BCMR_stSpn3907TimeoutBem;
extern volatile boolean_T COMR_flgRxCCS;
extern volatile boolean_T COMR_flgRxCEM;
extern volatile boolean_T COMR_flgRxCHM;
extern volatile boolean_T COMR_flgRxCML;
extern volatile boolean_T COMR_flgRxCRM;
extern volatile boolean_T COMR_flgRxCRO;
extern volatile boolean_T COMR_flgRxCSD;
extern volatile boolean_T COMR_flgRxCST;
extern volatile boolean_T COMR_flgRxCTS;
extern volatile boolean_T LcBCMR_ElockReq_flg;

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM1_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'BCMR_DChrgGbFlow'
 * '<S1>'   : 'BCMR_DChrgGbFlow/BCMR_DChrg_GbFlow'
 * '<S2>'   : 'BCMR_DChrgGbFlow/BCMR_DChrg_GbFlow/DChrgEna'
 * '<S3>'   : 'BCMR_DChrgGbFlow/BCMR_DChrg_GbFlow/DChrg_GbFlow'
 * '<S4>'   : 'BCMR_DChrgGbFlow/BCMR_DChrg_GbFlow/DChrg_GbFlow/Compare To Constant'
 * '<S5>'   : 'BCMR_DChrgGbFlow/BCMR_DChrg_GbFlow/DChrg_GbFlow/Compare To Constant1'
 * '<S6>'   : 'BCMR_DChrgGbFlow/BCMR_DChrg_GbFlow/DChrg_GbFlow/DcChrgStateFlow'
 * '<S7>'   : 'BCMR_DChrgGbFlow/BCMR_DChrg_GbFlow/DChrg_GbFlow/ElockRequest'
 * '<S8>'   : 'BCMR_DChrgGbFlow/BCMR_DChrg_GbFlow/DChrg_GbFlow/StateRetention'
 * '<S9>'   : 'BCMR_DChrgGbFlow/BCMR_DChrg_GbFlow/DChrg_GbFlow/ElockRequest/BMSDelay'
 * '<S10>'  : 'BCMR_DChrgGbFlow/BCMR_DChrg_GbFlow/DChrg_GbFlow/ElockRequest/Compare To Constant1'
 * '<S11>'  : 'BCMR_DChrgGbFlow/BCMR_DChrg_GbFlow/DChrg_GbFlow/ElockRequest/Compare To Constant2'
 * '<S12>'  : 'BCMR_DChrgGbFlow/BCMR_DChrg_GbFlow/DChrg_GbFlow/ElockRequest/Compare To Constant3'
 * '<S13>'  : 'BCMR_DChrgGbFlow/BCMR_DChrg_GbFlow/DChrg_GbFlow/ElockRequest/Compare To Constant8'
 * '<S14>'  : 'BCMR_DChrgGbFlow/BCMR_DChrg_GbFlow/DChrg_GbFlow/ElockRequest/BMSDelay/Unit Delay Resettable'
 * '<S15>'  : 'BCMR_DChrgGbFlow/BCMR_DChrg_GbFlow/DChrg_GbFlow/StateRetention/EdgeRising'
 * '<S16>'  : 'BCMR_DChrgGbFlow/BCMR_DChrg_GbFlow/DChrg_GbFlow/StateRetention/Subsystem3'
 * '<S17>'  : 'BCMR_DChrgGbFlow/BCMR_DChrg_GbFlow/DChrg_GbFlow/StateRetention/Timer'
 */
#endif                                 /* RTW_HEADER_BCMR_DChrgGbFlow_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
