/*
 * File: DSMR_FaultClr.c
 *
 * Code generated for Simulink model 'DSMR_FaultClr'.
 *
 * Model version                  : A1.0_1
 * Simulink Coder version         : 8.11 (R2016b) 25-Aug-2016
 * C/C++ source code generated on : Mon Aug 10 23:48:37 2020
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#include "DSMR_FaultClr.h"
#include "DSMR_FaultClr_private.h"

/* Previous zero-crossings (trigger) states */
PrevZCX_DSMR_FaultClr_T DSMR_FaultClr_PrevZCX;

/* Model step function */
void DSMR_FaultClr_step(void)
{
  boolean_T rtb_LogicalOperator;
  rtb_LogicalOperator = (COMR_bClrAllDtc || (DSMAUX_xClearTrg_C != 0));
  if (rtb_LogicalOperator && (DSMR_FaultClr_PrevZCX.Subsystem_Trig_ZCE !=
       POS_ZCSIG)) {
    DFC_CurrRngErr_ASW = 0U;
    DFC_Msg2A3Tmt_ASW = 0U;
    DFC_DChrgBattTMin_ASW = 0U;
    DFC_CC2Chk_ASW = 0U;
    DFC_APlusChk_ASW = 0U;
    DFC_DChrgMsgTmt_ASW = 0U;
    DFC_DChrgTNegElecMax_ASW = 0U;
    DFC_DChrgTNegElecMin_ASW = 0U;
    DFC_DChrgTNegElecSig_ASW = 0U;
    DFC_DChrgTPosElecMax_ASW = 0U;
    DFC_DChrgTPosElecMin_ASW = 0U;
    DFC_DChrgTPosElecSig_ASW = 0U;
    DFC_RcMsg2A3Mis_ASW = 0U;
    DFC_CcuSelfChkErr_ASW = 0U;
    DFC_ChrgOCMin_ASW = 0U;
    DFC_ChrgOCMax_ASW = 0U;
    DFC_DisChOCMax_ASW = 0U;
    DFC_SocRngLoMax_ASW = 0U;
    DFC_SocRngLoMin_ASW = 0U;
    DFC_SocRngHiMax_ASW = 0U;
    DFC_SocRngHiMin_ASW = 0U;
    DFC_InClntOverTmp_ASW = 0U;
    DFC_OutClntOverTmp_ASW = 0U;
    DFC_ChkSumMsg2A3Err_ASW = 0U;
    DFC_ClntDsTElecMax_ASW = 0U;
    DFC_ClntDsTElecMin_ASW = 0U;
    DFC_ClntDsTElecSig_ASW = 0U;
    DFC_ClntUsTElecMax_ASW = 0U;
    DFC_ClntUsTElecMin_ASW = 0U;
    DFC_ClntUsTElecSig_ASW = 0U;
    DFC_CoolPerfPlaus_ASW = 0U;
    DFC_HtgPerfPlaus_ASW = 0U;
    DFC_DChrgFobd_ASW = 0U;
    DFC_DChrgHvOnFail_ASW = 0U;
    DFC_RcMsg2A5Mis_ASW = 0U;
    DFC_AChgHVOnTmt_ASW = 0U;
    DFC_AChgHVOffTmt_ASW = 0U;
    DFC_AChgS2ClsdTmt_ASW = 0U;
    DFC_DChrgStakeErr_ASW = 0U;
    DFC_DChrgStkVoltErr_ASW = 0U;
    DFC_DChrgStkCurrErr_ASW = 0U;
    DFC_AChgPileRdyTmt_ASW = 0U;
    DFC_DChrgCHMTmt_ASW = 0U;
    DFC_DChrgCRMTmt_ASW = 0U;
    DFC_DChrgCMLTmt_ASW = 0U;
    DFC_RcMsg2A7Mis_ASW = 0U;
    DFC_DChrgCROTmt_ASW = 0U;
    DFC_DChrgCCSTmt_ASW = 0U;
    DFC_DChrgCSTTmt_ASW = 0U;
    DFC_DChrgCSDTmt_ASW = 0U;
    DFC_DChrgParaChk_ASW = 0U;
    DFC_DChrgCableChk_ASW = 0U;
    DFC_DChrgSLACTOut_ASW = 0U;
    DFC_DChrgCnntErr_ASW = 0U;
    DFC_DChrgLckErr_ASW = 0U;
    DFC_AChrgCnntErr_ASW = 0U;
    DFC_CrashNpl_ASW = 0U;
    DFC_AChgLckTmt_ASW = 0U;
    DFC_AChgRdyPndiTmt_ASW = 0U;
    DFC_AChgRdyTmt_ASW = 0U;
    DFC_AChgingErr_ASW = 0U;
    DFC_AChgUnlckTmt_ASW = 0U;
    DFC_AChgFobd_ASW = 0U;
    DFC_SocValJmp_ASW = 0U;
    DFC_FuseNpl_ASW = 0U;
    DFC_Kl30cVoltLoErr_ASW = 0U;
    DFC_PosStuckMax_ASW = 0U;
    DFC_MPosStuckMin_ASW = 0U;
    DFC_BattVoltRngErr_ASW = 0U;
    DFC_MNegStuckMax_ASW = 0U;
    DFC_MNegStuckMin_ASW = 0U;
    DFC_PrStuckMin_ASW = 0U;
    DFC_DChrgPosStuckMax_ASW = 0U;
    DFC_DChrgPosStuckMin_ASW = 0U;
    DFC_DChrgNegStuckMax_ASW = 0U;
    DFC_DChrgNegStuckMin_ASW = 0U;
    DFC_HvPwrUpFail_ASW = 0U;
    DFC_DChrgPwrUpFail_ASW = 0U;
    DFC_BattTAlrmMax_ASW = 0U;
    DFC_BattHVMsgTmt_ASW = 0U;
    DFC_BattTFaultMax_ASW = 0U;
    DFC_BattTAlrmMin_ASW = 0U;
    DFC_BattTFaultMin_ASW = 0U;
    DFC_BattTempVldMin_ASW = 0U;
    DFC_BattTCnstMax_ASW = 0U;
    DFC_BattTGradtMax_ASW = 0U;
    DFC_CellVoltAlrmMax_ASW = 0U;
    DFC_CellVoltFaultMax_ASW = 0U;
    DFC_CellVoltFusfMax_ASW = 0U;
    DFC_CellVoltAlrmMin_ASW = 0U;
    DFC_BusHVMsgTmt_ASW = 0U;
    DFC_CellVoltFusfMin_ASW = 0U;
    DFC_CellVoltFaultMin_ASW = 0U;
    DFC_CellVoltVldMin_ASW = 0U;
    DFC_CellVoltNpl_ASW = 0U;
    DFC_Msg2E6Tmt_ASW = 0U;
    DFC_RcMsg2E0Mis_ASW = 0U;
    DFC_ChkSumMsg2E0Err_ASW = 0U;
    DFC_RcMsg2E1Mis_ASW = 0U;
    DFC_ChkSumMsg2E1Err_ASW = 0U;
    DFC_DcCanBusOff_ASW = 0U;
    DFC_638LinCommErr_ASW = 0U;
    DFC_DChrgTCnntMax_ASW = 0U;
    DFC_ChrgOCNpl_ASW = 0U;
    DFC_DisChOCNpl_ASW = 0U;
    DFC_BattVoltHiMax_ASW = 0U;
    DFC_BattVoltLoMin_ASW = 0U;
    DFC_ThmRnwy_ASW = 0U;
    DFC_AChrgPortOvrTemp_ASW = 0U;
    DFC_CurrOffsPlaus_ASW = 0U;
    DFC_CurrStukPlaus_ASW = 0U;
    DFC_CurrChrgPlaus_ASW = 0U;
    DFC_CellTempTmt_ASW = 0U;
    DFC_BattUNpl_ASW = 0U;
    DFC_BattVoltVld_ASW = 0U;
    DFC_PackUNpl_ASW = 0U;
    DFC_PackVoltVld_ASW = 0U;
    DFC_DChrgUNpl_ASW = 0U;
    DFC_DChrgVoltVld_ASW = 0U;
    DFC_BoardTempTmt_ASW = 0U;
    DFC_HvilMax_ASW = 0U;
    DFC_HvilMin_ASW = 0U;
    DFC_HvilSig_ASW = 0U;
    DFC_CellVoltTmt_ASW = 0U;
    DFC_ChkSumMsg050Err_ASW = 0U;
    DFC_RcMsg050Mis_ASW = 0U;
    DFC_CrashHwNpl_ASW = 0U;
    DFC_IsoChkLv1_ASW = 0U;
    DFC_IsoChkLv2_ASW = 0U;
    DFC_DisChOCMin_ASW = 0U;
    DFC_InsResValdFault_ASW = 0U;
    DFC_Kl30OutRngErr_ASW = 0U;
    DFC_Kl30VoltLoErr_ASW = 0U;
    DFC_Kl30VoltHiErr_ASW = 0U;
    DFC_InCanBusOff_ASW = 0U;
    DFC_EepReadErr_ASW = 0U;
    DFC_BalStuckMax_ASW = 0U;
    DFC_BalStuckMin_ASW = 0U;
    DFC_CSCPwrSpyHiErr_ASW = 0U;
    DFC_CSCPwrSpyLoErr_ASW = 0U;
    DFC_BattTWarnMax_ASW = 0U;
    DFC_BattTWarnMin_ASW = 0U;
    DFC_CmcBordOTMax_ASW = 0U;
    DFC_BattTempVldMax_ASW = 0U;
    DFC_BattTHopMax_ASW = 0U;
    DFC_VeCanBusOff_ASW = 0U;
    DFC_CellVoltRngHiErr_ASW = 0U;
    DFC_CellVoltRngLoErr_ASW = 0U;
    DFC_CellVoltWarnMax_ASW = 0U;
    DFC_CellVoltWarnMin_ASW = 0U;
    DFC_CellVoltVldMax_ASW = 0U;
    DFC_AChrgCurrMish_ASW = 0U;
    DFC_DChrgCurrMish_ASW = 0U;
    DFC_DChrgLowTempCurrMish_ASW = 0U;
    DFC_AChrgVoltMish_ASW = 0U;
    DFC_DChrgVoltMish_ASW = 0U;
  }

  DSMR_FaultClr_PrevZCX.Subsystem_Trig_ZCE = rtb_LogicalOperator;
}

/* Model initialize function */
void DSMR_FaultClr_initialize(void)
{
  DSMR_FaultClr_PrevZCX.Subsystem_Trig_ZCE = POS_ZCSIG;
}

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
