/*
 * File: BCCR_CtrDsmDiag.h
 *
 * Code generated for Simulink model 'BCCR_CtrDsmDiag'.
 *
 * Model version                  : 1.1112F
 * Simulink Coder version         : 8.11F (R2016b) 25-Aug-2016
 * C/C++ source code generated on : Mon Dec 10 11:39:46 2018
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#ifndef RTW_HEADER_BCCR_CtrDsmDiag_h_
#define RTW_HEADER_BCCR_CtrDsmDiag_h_
#include <stddef.h>
#ifndef BCCR_CtrDsmDiag_COMMON_INCLUDES_
# define BCCR_CtrDsmDiag_COMMON_INCLUDES_
#include "rtwtypes.h"
#endif                                 /* BCCR_CtrDsmDiag_COMMON_INCLUDES_ */

#include "BCCR_CtrDsmDiag_types.h"

/* Includes for objects with custom storage classes. */
#include "BCCR_CtrDsmDiag_parameters.h"

/* Macros for accessing real-time model data structure */

/* user code (top of header file) */
#include "ASW_Interface.h"

/* Block states (auto storage) for system '<Root>' */
typedef struct {
  uint8_T Delay3_DSTATE;               /* '<S45>/Delay3' */
  uint8_T Delay3_DSTATE_n;             /* '<S44>/Delay3' */
  uint8_T Delay3_DSTATE_d;             /* '<S43>/Delay3' */
  uint8_T Delay3_DSTATE_h;             /* '<S42>/Delay3' */
  uint8_T Delay3_DSTATE_p;             /* '<S41>/Delay3' */
  uint8_T Delay3_DSTATE_a;             /* '<S11>/Delay3' */
  uint8_T Delay3_DSTATE_c;             /* '<S10>/Delay3' */
  uint8_T Delay3_DSTATE_b;             /* '<S9>/Delay3' */
  uint8_T Delay3_DSTATE_o;             /* '<S8>/Delay3' */
  boolean_T Delay2_DSTATE;             /* '<S45>/Delay2' */
  boolean_T Delay2_DSTATE_c;           /* '<S44>/Delay2' */
  boolean_T Delay2_DSTATE_k;           /* '<S43>/Delay2' */
  boolean_T Delay2_DSTATE_c2;          /* '<S42>/Delay2' */
  boolean_T Delay2_DSTATE_o;           /* '<S41>/Delay2' */
  boolean_T Delay2_DSTATE_a;           /* '<S11>/Delay2' */
  boolean_T Delay2_DSTATE_p;           /* '<S10>/Delay2' */
  boolean_T Delay2_DSTATE_l;           /* '<S9>/Delay2' */
  boolean_T Delay2_DSTATE_d;           /* '<S8>/Delay2' */
} DW_BCCR_CtrDsmDiag_T;

/* Block states (auto storage) */
extern DW_BCCR_CtrDsmDiag_T BCCR_CtrDsmDiag_DW;

/* Model entry point functions */
extern void BCCR_CtrDsmDiag_initialize(void);
extern void BCCR_CtrDsmDiag_step(void);

/* Exported data declaration */

/* Volatile memory section */
 
 

/* Declaration for custom storage class: Volatile */
extern volatile uint8_T DFC_DChrgNegStuckMax_ASW;/* Max fault of dc charge negative contactor */
extern volatile uint8_T DFC_DChrgNegStuckMin_ASW;/* Min fault of dc charge negative contactor */
extern volatile uint8_T DFC_DChrgPosStuckMax_ASW;/* Max fault of dc charge positive contactor */
extern volatile uint8_T DFC_DChrgPosStuckMin_ASW;/* Min fault of dc charge positive contactor */
extern volatile uint8_T DFC_MNegStuckMax_ASW;/* Max fault of main negative contactor */
extern volatile uint8_T DFC_MNegStuckMin_ASW;/* Min fault of main negative contactor */
extern volatile uint8_T DFC_MPosStuckMin_ASW;/* Min fault of main positive contactor */
extern volatile uint8_T DFC_PosStuckMax_ASW;/* Max fault of positive contactor include main positive contactor and precharge contactor */
extern volatile uint8_T DFC_PrStuckMin_ASW;/* Min fault of precharge contactor */

 
 

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'BCCR_CtrDsmDiag'
 * '<S1>'   : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag'
 * '<S2>'   : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag'
 * '<S3>'   : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag'
 * '<S4>'   : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/Compare To Constant'
 * '<S5>'   : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/Compare To Constant1'
 * '<S6>'   : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/Compare To Constant2'
 * '<S7>'   : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/Compare To Constant3'
 * '<S8>'   : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck'
 * '<S9>'   : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck1'
 * '<S10>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck2'
 * '<S11>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck3'
 * '<S12>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck/Bit Clear1'
 * '<S13>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck/Bit Clear2'
 * '<S14>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck/Bit Set'
 * '<S15>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck/Bit Set1'
 * '<S16>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck/Bit Set2'
 * '<S17>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck/Bit Set4'
 * '<S18>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck1/Bit Clear1'
 * '<S19>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck1/Bit Clear2'
 * '<S20>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck1/Bit Set'
 * '<S21>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck1/Bit Set1'
 * '<S22>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck1/Bit Set2'
 * '<S23>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck1/Bit Set4'
 * '<S24>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck2/Bit Clear1'
 * '<S25>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck2/Bit Clear2'
 * '<S26>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck2/Bit Set'
 * '<S27>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck2/Bit Set1'
 * '<S28>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck2/Bit Set2'
 * '<S29>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck2/Bit Set4'
 * '<S30>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck3/Bit Clear1'
 * '<S31>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck3/Bit Clear2'
 * '<S32>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck3/Bit Set'
 * '<S33>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck3/Bit Set1'
 * '<S34>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck3/Bit Set2'
 * '<S35>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/DChrgCtrPlausDsmDiag/DSM_ReportCheck3/Bit Set4'
 * '<S36>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/Compare To Constant'
 * '<S37>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/Compare To Constant1'
 * '<S38>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/Compare To Constant2'
 * '<S39>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/Compare To Constant3'
 * '<S40>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/Compare To Constant4'
 * '<S41>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck'
 * '<S42>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck1'
 * '<S43>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck2'
 * '<S44>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck3'
 * '<S45>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck4'
 * '<S46>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck/Bit Clear1'
 * '<S47>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck/Bit Clear2'
 * '<S48>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck/Bit Set'
 * '<S49>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck/Bit Set1'
 * '<S50>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck/Bit Set2'
 * '<S51>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck/Bit Set4'
 * '<S52>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck1/Bit Clear1'
 * '<S53>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck1/Bit Clear2'
 * '<S54>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck1/Bit Set'
 * '<S55>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck1/Bit Set1'
 * '<S56>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck1/Bit Set2'
 * '<S57>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck1/Bit Set4'
 * '<S58>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck2/Bit Clear1'
 * '<S59>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck2/Bit Clear2'
 * '<S60>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck2/Bit Set'
 * '<S61>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck2/Bit Set1'
 * '<S62>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck2/Bit Set2'
 * '<S63>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck2/Bit Set4'
 * '<S64>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck3/Bit Clear1'
 * '<S65>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck3/Bit Clear2'
 * '<S66>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck3/Bit Set'
 * '<S67>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck3/Bit Set1'
 * '<S68>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck3/Bit Set2'
 * '<S69>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck3/Bit Set4'
 * '<S70>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck4/Bit Clear1'
 * '<S71>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck4/Bit Clear2'
 * '<S72>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck4/Bit Set'
 * '<S73>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck4/Bit Set1'
 * '<S74>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck4/Bit Set2'
 * '<S75>'  : 'BCCR_CtrDsmDiag/BCCR_CtrDsmDiag/MainCtrPlausDsmDiag/DSM_ReportCheck4/Bit Set4'
 */
#endif                                 /* RTW_HEADER_BCCR_CtrDsmDiag_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
