/*
 * File: HVSR_HvilChk.c
 *
 * Code generated for Simulink model 'HVSR_HvilChk'.
 *
 * Model version                  : 1.168
 * Simulink Coder version         : 8.13 (R2017b) 24-Jul-2017
 * C/C++ source code generated on : Thu Jul 29 11:20:56 2021
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#include "HVSR_HvilChk.h"
#include "HVSR_HvilChk_private.h"

/* Exported data definition */

/* Volatile memory section */
#define ASW1_OEM_START_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Definition for custom storage class: Volatile */
volatile uint8_T DFC_HvilMax_ASW;          /* Max fault for HVIL Scb diagnosis */
volatile uint8_T DFC_HvilMin_ASW;          /* Min fault for HVIL Scg diagnosis */
volatile uint8_T DFC_HvilSig_ASW;          /* Sig fault for HVIL Opl diagnosis */

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"
#define ASW1_OEM_START_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Definition for custom storage class: OutputSignal */
volatile boolean_T BSPR_bHvilDiagCond; /* Condition for HVIL  diagnosis */
volatile boolean_T BSPR_bKl30HvilDiagCond;/* kl30 condition for HVIL diagnosis */
volatile real32_T BSPR_dcHvilPwmDuty;  /* 高压互锁PWM占空比设定 */
volatile boolean_T HVSR_bHvilOplErrDet;/* Error flag for HVIL open load diagnosis */
volatile boolean_T HVSR_bHvilOplErrHeal;/* Healing flag for HVIL open load  diagnosis */
volatile boolean_T HVSR_bHvilScbErrDet;/* Error flag for HVIL short circuit to battery diagnosis */
volatile boolean_T HVSR_bHvilScbErrHeal;/* Healing flag for HVIL short circuit to battery diagnosis */
volatile boolean_T HVSR_bHvilScgErrDet;/* Error flag for HVIL short circuit to ground diagnosis */
volatile boolean_T HVSR_bHvilScgErrHeal;/* Healing flag for HVIL short circuit to ground diagnosis */
volatile boolean_T HVSR_flgHvilFault;  /* Fault flag for HVIL detect */

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM2_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Block signals (auto storage) */
B_HVSR_HvilChk_T HVSR_HvilChk_B;

/* Block states (auto storage) */
DW_HVSR_HvilChk_T HVSR_HvilChk_DW;

/* Forward declaration for local functions */
static void HVSR_enter_internal_RS_FlipFlop(const boolean_T *RelationalOperator);
static void HVSR_HvilChk_RS_FlipFlop(const boolean_T *RelationalOperator);

/* Function for Chart: '<S34>/RS' */
static void HVSR_enter_internal_RS_FlipFlop(const boolean_T *RelationalOperator)
{
  if (HVSR_bHvilOplErrHeal) {
    HVSR_HvilChk_B.Q = false;
  } else {
    if (*RelationalOperator) {
      HVSR_HvilChk_B.Q = true;
    }
  }
}

/* Function for Chart: '<S34>/RS' */
static void HVSR_HvilChk_RS_FlipFlop(const boolean_T *RelationalOperator)
{
  HVSR_enter_internal_RS_FlipFlop(RelationalOperator);
}

/* Model step function */
void HVSR_HvilChk_step(void)
{
  boolean_T rtb_LogicalOperator4_i;
  boolean_T rtb_Compare_o;
  boolean_T rtb_LogicalOperator5_b;
  boolean_T rtb_LogicalOperator3_h;
  real32_T rtb_Add;
  real32_T rtb_Product_h;
  uint8_T rtb_Switch4_g;
  boolean_T RelationalOperator;
  int32_T rtb_LogicalOperator3_l_tmp;
  BSPR_bKl30HvilDiagCond = ((BSPR_uKl30 <= HVSR_uKL30ThresHi_C) && (BSPR_uKl30 >=
    HVSR_uKL30ThresLo_C));
  rtb_LogicalOperator4_i = ((BSPR_dcHvilPwmDutyInp > HVSR_dcHvilPwmDutyHi_C) &&
    (BSPR_dcHvilPwmDutyOutDet > HVSR_dcHvilPwmDutyHi_C));
  rtb_Compare_o = ((BSPR_stHVILInp & 8) == 8);
  rtb_LogicalOperator5_b = (BSPR_dcHvilPwmDutyInp < HVSR_dcHvilPwmDutyOpl_C);
  BSPR_bHvilDiagCond = (BSPR_bKl30HvilDiagCond && ((BSPR_fHvilPwmFrqOutDet <=
    HVSR_fHvilPwmFrqHi_C) && (BSPR_fHvilPwmFrqOutDet >= HVSR_fHvilPwmFrqLo_C)) &&
                        (((BSPR_stHVILInp & 16) == 0) && ((BSPR_stHVILOutpFdbk &
    16) == 0)));
  rtb_LogicalOperator3_h = (BSPR_bHvilDiagCond && (fabsf
    (BSPR_dcHvilPwmDutyOutDet - HVSR_dcHvilPwmDutyNrm_C) <
    HVSR_dcHvilPwmDutyThres_C));
  if (rtb_Compare_o && rtb_LogicalOperator5_b && rtb_LogicalOperator3_h) {
    rtb_Add = 0.01F;
  } else {
    rtb_Add = -0.01F;
  }

  rtb_Add += fmaxf(fminf(HVSR_tiHvilOplErr_C, HVSR_HvilChk_DW.Delay_DSTATE),
                   0.0F);
  RelationalOperator = (rtb_Add > HVSR_tiHvilOplErr_C);
  rtb_LogicalOperator3_h = (rtb_LogicalOperator3_h && (!rtb_Compare_o) &&
    (!rtb_LogicalOperator5_b));
  if (rtb_LogicalOperator3_h) {
    rtb_Product_h = 0.01F;
  } else {
    rtb_Product_h = 0.0F;
  }

  rtb_Product_h = (rtb_Product_h + fminf(HVSR_tiHvilOplHealErr_C,
    HVSR_HvilChk_DW.Delay_DSTATE_k)) * (real32_T)rtb_LogicalOperator3_h;
  HVSR_bHvilOplErrHeal = (rtb_Product_h > HVSR_tiHvilOplHealErr_C);
  HVSR_HvilChk_DW.Delay_DSTATE_k = rtb_Product_h;
  if (HVSR_HvilChk_DW.is_active_c3_HVSR_HvilChk == 0U) {
    HVSR_HvilChk_DW.is_active_c3_HVSR_HvilChk = 1U;
    HVSR_enter_internal_RS_FlipFlop(&RelationalOperator);
  } else {
    HVSR_HvilChk_RS_FlipFlop(&RelationalOperator);
  }

  if (HVSR_flgHvilOplOvrSwt_C) {
    HVSR_bHvilOplErrDet = HVSR_flgHvilOplOvr_C;
  } else {
    HVSR_bHvilOplErrDet = HVSR_HvilChk_B.Q;
  }

  if (HVSR_bHvilOplErrDet) {
    rtb_Compare_o = ((BSPR_stHVILOutpFdbk & 9) == 8);
  } else {
    rtb_Compare_o = ((BSPR_stHVILOutpFdbk & 9) == 9);
  }

  rtb_LogicalOperator3_l_tmp = BSPR_stHVILInp & 9;
  rtb_LogicalOperator3_h = ((rtb_LogicalOperator3_l_tmp == 9) && rtb_Compare_o);
  RelationalOperator = (BSPR_bKl30HvilDiagCond && rtb_LogicalOperator4_i &&
                        rtb_LogicalOperator3_h);
  if (RelationalOperator) {
    rtb_Product_h = 0.01F;
  } else {
    rtb_Product_h = 0.0F;
  }

  rtb_Product_h = (rtb_Product_h + fminf(HVSR_tiHvilScbErr_C,
    HVSR_HvilChk_DW.Delay_DSTATE_l)) * (real32_T)RelationalOperator;
  HVSR_HvilChk_DW.Delay_DSTATE_l = rtb_Product_h;
  if (HVSR_flgHvilScbOvrSwt_C) {
    HVSR_bHvilScbErrDet = HVSR_flgHvilScbOvr_C;
  } else {
    HVSR_bHvilScbErrDet = (rtb_Product_h > HVSR_tiHvilScbErr_C);
  }

  rtb_LogicalOperator5_b = ((BCCR_cntHvilDiag_CW & 1) == 1);
  RelationalOperator = (rtb_LogicalOperator5_b && HVSR_bHvilScbErrDet);
  rtb_LogicalOperator3_h = (BSPR_bKl30HvilDiagCond && (!rtb_LogicalOperator4_i) &&
    (!rtb_LogicalOperator3_h));
  if (rtb_LogicalOperator3_h) {
    rtb_Product_h = 0.01F;
  } else {
    rtb_Product_h = 0.0F;
  }

  rtb_Product_h = (rtb_Product_h + fminf(HVSR_tiHvilScbHealErr_C,
    HVSR_HvilChk_DW.Delay_DSTATE_p)) * (real32_T)rtb_LogicalOperator3_h;
  HVSR_bHvilScbErrHeal = (rtb_Product_h > HVSR_tiHvilScbHealErr_C);
  HVSR_HvilChk_DW.Delay_DSTATE_p = rtb_Product_h;
  if (HVSR_HvilChk_DW.Delay2_DSTATE_o) {
    rtb_Switch4_g = (uint8_T)~(uint8_T)((uint8_T)~DFC_HvilMax_ASW | 8U);
  } else if (RelationalOperator) {
    rtb_Switch4_g = (uint8_T)(DFC_HvilMax_ASW | 152U);
  } else if ((!rtb_LogicalOperator5_b) || HVSR_bHvilScbErrHeal) {
    rtb_Switch4_g = (uint8_T)((uint8_T)~(uint8_T)((uint8_T)~DFC_HvilMax_ASW | 16U) |
      8U);
  } else {
    rtb_Switch4_g = HVSR_HvilChk_DW.Delay3_DSTATE_j;
  }

  HVSR_HvilChk_DW.Delay2_DSTATE_o = false;
  HVSR_HvilChk_DW.Delay3_DSTATE_j = rtb_Switch4_g;
  DFC_HvilMax_ASW = rtb_Switch4_g;
  rtb_LogicalOperator3_h = ((BSPR_dcHvilPwmDutyInp < HVSR_dcHvilPwmDutyLo_C) &&
    (BSPR_dcHvilPwmDutyOutDet < HVSR_dcHvilPwmDutyLo_C));
  rtb_LogicalOperator5_b = ((rtb_LogicalOperator3_l_tmp == 8) &&
    ((BSPR_stHVILOutpFdbk & 9) == 8));
  rtb_LogicalOperator4_i = (BSPR_bKl30HvilDiagCond && rtb_LogicalOperator3_h &&
    rtb_LogicalOperator5_b);
  if (rtb_LogicalOperator4_i) {
    rtb_Product_h = 0.01F;
  } else {
    rtb_Product_h = 0.0F;
  }

  rtb_Product_h = (rtb_Product_h + fminf(HVSR_tiHvilScgErr_C,
    HVSR_HvilChk_DW.Delay_DSTATE_j)) * (real32_T)rtb_LogicalOperator4_i;
  HVSR_HvilChk_DW.Delay_DSTATE_j = rtb_Product_h;
  if (HVSR_flgHvilScgOvrSwt_C) {
    HVSR_bHvilScgErrDet = HVSR_flgHvilScgOvr_C;
  } else {
    HVSR_bHvilScgErrDet = (rtb_Product_h > HVSR_tiHvilScgErr_C);
  }

  rtb_Compare_o = ((BCCR_cntHvilDiag_CW & 2) == 2);
  rtb_LogicalOperator4_i = (rtb_Compare_o && HVSR_bHvilScgErrDet);
  rtb_LogicalOperator3_h = (BSPR_bKl30HvilDiagCond && (!rtb_LogicalOperator3_h) &&
    (!rtb_LogicalOperator5_b));
  if (rtb_LogicalOperator3_h) {
    rtb_Product_h = 0.01F;
  } else {
    rtb_Product_h = 0.0F;
  }

  rtb_Product_h = (rtb_Product_h + fminf(HVSR_tiHvilScgHealErr_C,
    HVSR_HvilChk_DW.Delay_DSTATE_i)) * (real32_T)rtb_LogicalOperator3_h;
  HVSR_bHvilScgErrHeal = (rtb_Product_h > HVSR_tiHvilScgHealErr_C);
  HVSR_HvilChk_DW.Delay_DSTATE_i = rtb_Product_h;
  if (HVSR_HvilChk_DW.Delay2_DSTATE_p) {
    rtb_Switch4_g = (uint8_T)~(uint8_T)((uint8_T)~DFC_HvilMin_ASW | 8U);
  } else if (rtb_LogicalOperator4_i) {
    rtb_Switch4_g = (uint8_T)(DFC_HvilMin_ASW | 152U);
  } else if ((!rtb_Compare_o) || HVSR_bHvilScgErrHeal) {
    rtb_Switch4_g = (uint8_T)((uint8_T)~(uint8_T)((uint8_T)~DFC_HvilMin_ASW | 16U) |
      8U);
  } else {
    rtb_Switch4_g = HVSR_HvilChk_DW.Delay3_DSTATE_i;
  }

  HVSR_HvilChk_DW.Delay2_DSTATE_p = false;
  HVSR_HvilChk_DW.Delay3_DSTATE_i = rtb_Switch4_g;
  DFC_HvilMin_ASW = rtb_Switch4_g;
  rtb_LogicalOperator3_h = ((BCCR_cntHvilDiag_CW & 4) == 4);
  rtb_LogicalOperator5_b = (rtb_LogicalOperator3_h && HVSR_bHvilOplErrDet);
  if (HVSR_HvilChk_DW.Delay2_DSTATE) {
    rtb_Switch4_g = (uint8_T)~(uint8_T)((uint8_T)~DFC_HvilSig_ASW | 8U);
  } else if (rtb_LogicalOperator5_b) {
    rtb_Switch4_g = (uint8_T)(DFC_HvilSig_ASW | 152U);
  } else if ((!rtb_LogicalOperator3_h) || HVSR_bHvilOplErrHeal) {
    rtb_Switch4_g = (uint8_T)((uint8_T)~(uint8_T)((uint8_T)~DFC_HvilSig_ASW | 16U) |
      8U);
  } else {
    rtb_Switch4_g = HVSR_HvilChk_DW.Delay3_DSTATE;
  }

  HVSR_HvilChk_DW.Delay2_DSTATE = false;
  HVSR_HvilChk_DW.Delay3_DSTATE = rtb_Switch4_g;
  DFC_HvilSig_ASW = rtb_Switch4_g;
  HVSR_flgHvilFault = (RelationalOperator || rtb_LogicalOperator4_i ||
                       rtb_LogicalOperator5_b);
  BSPR_dcHvilPwmDuty = HVSR_dcHvilPwmDutyOptSet_C;
  HVSR_HvilChk_DW.Delay_DSTATE = rtb_Add;
}

/* Model initialize function */
void HVSR_HvilChk_initialize(void)
{
  /* Registration code */

  /* block I/O */

  /* custom signals */
  BSPR_dcHvilPwmDuty = 0.0F;
  HVSR_flgHvilFault = false;
  HVSR_HvilChk_DW.Delay2_DSTATE_o = true;
  HVSR_HvilChk_DW.Delay2_DSTATE_p = true;
  HVSR_HvilChk_DW.Delay2_DSTATE = true;
}

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
