/*
 * File: COMR_MsgRcDiag.h
 *
 * Code generated for Simulink model 'COMR_MsgRcDiag'.
 *
 * Model version                  : A1.1_0
 * Simulink Coder version         : 8.11 (R2016b) 25-Aug-2016
 * C/C++ source code generated on : Fri Nov 20 15:52:00 2020
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#ifndef RTW_HEADER_COMR_MsgRcDiag_h_
#define RTW_HEADER_COMR_MsgRcDiag_h_
#include <stddef.h>
#ifndef COMR_MsgRcDiag_COMMON_INCLUDES_
# define COMR_MsgRcDiag_COMMON_INCLUDES_
#include "rtwtypes.h"
#endif                                 /* COMR_MsgRcDiag_COMMON_INCLUDES_ */

#include "COMR_MsgRcDiag_types.h"

/* Macros for accessing real-time model data structure */

/* user code (top of header file) */
#include "ASW_Interface.h"

/* Block signals (auto storage) */
typedef struct {
  uint8_T OutportBufferForCOMR_cntRCMsg2E;/* '<S18>/Constant' */
  uint8_T OutportBufferForCOMR_cntRCMsg_m;/* '<S18>/Constant1' */
  boolean_T COMR_DFC_RcMsg2E6Mis_j;    /* '<S18>/COMR_DFC_RcMsg2E6Mis' */
  boolean_T COMR_DFC_RcMsg2E1Mis_g;    /* '<S18>/COMR_DFC_RcMsg2E1Mis' */
} B_COMR_MsgRcDiag_T;

/* Block states (auto storage) for system '<Root>' */
typedef struct {
  real32_T Delay_DSTATE;               /* '<S14>/Delay' */
  real32_T Delay_DSTATE_b;             /* '<S6>/Delay' */
  boolean_T Delay2_DSTATE;             /* '<S56>/Delay2' */
  boolean_T Delay2_DSTATE_f;           /* '<S43>/Delay2' */
  boolean_T Delay2_DSTATE_b;           /* '<S42>/Delay2' */
  boolean_T Delay2_DSTATE_g;           /* '<S23>/Delay2' */
  boolean_T Delay2_DSTATE_c;           /* '<S22>/Delay2' */
  boolean_T Delay2_DSTATE_i;           /* '<S21>/Delay2' */
  boolean_T Delay2_DSTATE_m;           /* '<S7>/Delay2' */
  boolean_T VcuObc_RC_Diag_MODE;       /* '<S1>/VcuObc_RC_Diag' */
  boolean_T Abm_RC_Diag_MODE;          /* '<S1>/Abm_RC_Diag' */
} DW_COMR_MsgRcDiag_T;

/* Invariant block signals (auto storage) */
typedef struct {
  const uint8_T Constant;              /* '<S20>/Constant' */
  const uint8_T Constant_g;            /* '<S18>/Constant' */
  const uint8_T Constant1;             /* '<S18>/Constant1' */
  const uint8_T Constant_b;            /* '<S3>/Constant' */
} ConstB_COMR_MsgRcDiag_T;

/* Block signals (auto storage) */
extern B_COMR_MsgRcDiag_T COMR_MsgRcDiag_B;

/* Block states (auto storage) */
extern DW_COMR_MsgRcDiag_T COMR_MsgRcDiag_DW;
extern const ConstB_COMR_MsgRcDiag_T COMR_MsgRcDiag_ConstB;/* constant block i/o */

/* Model entry point functions */
extern void COMR_MsgRcDiag_initialize(void);
extern void COMR_MsgRcDiag_step(void);

/* Exported data declaration */

/* Volatile memory section */
#define ASW1_OEM_START_SEC_DEFAULT_RAM1_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: Volatile */
extern volatile uint8_T DFC_RcMsg050Mis_ASW;
extern volatile uint8_T DFC_RcMsg2A3Mis_ASW;
extern volatile uint8_T DFC_RcMsg2A5Mis_ASW;
extern volatile uint8_T DFC_RcMsg2A7Mis_ASW;
extern volatile uint8_T DFC_RcMsg2E0Mis_ASW;
extern volatile uint8_T DFC_RcMsg2E1Mis_ASW;
extern volatile uint8_T DFC_RcMsg2EBMis_ASW;

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM1_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"
#define ASW1_OEM_START_SEC_DEFAULT_RAM1_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: OutputSignal */
extern volatile uint8_T COMR_cntRCMsg050Pre;
extern volatile uint8_T COMR_cntRCMsg2A3Pre;
extern volatile uint8_T COMR_cntRCMsg2A5Pre;
extern volatile uint8_T COMR_cntRCMsg2A7Pre;
extern volatile uint8_T COMR_cntRCMsg2E1Pre;
extern volatile uint8_T COMR_cntRCMsg2E6Pre;
extern volatile boolean_T COMR_flgRcMsg050MissErr;
extern volatile boolean_T COMR_flgRcMsg2A3MissErr;
extern volatile boolean_T COMR_flgRcMsg2A5MissErr;
extern volatile boolean_T COMR_flgRcMsg2A7MissErr;
extern volatile boolean_T COMR_flgRcMsg2E1MissErr;
extern volatile boolean_T COMR_flgRcMsg2E6MissErr;

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM1_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'COMR_MsgRcDiag'
 * '<S1>'   : 'COMR_MsgRcDiag/COMR_MsgRcDiag'
 * '<S2>'   : 'COMR_MsgRcDiag/COMR_MsgRcDiag/AbmEnCond'
 * '<S3>'   : 'COMR_MsgRcDiag/COMR_MsgRcDiag/Abm_RC_Diag'
 * '<S4>'   : 'COMR_MsgRcDiag/COMR_MsgRcDiag/EnCond'
 * '<S5>'   : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag'
 * '<S6>'   : 'COMR_MsgRcDiag/COMR_MsgRcDiag/AbmEnCond/TONV_10msTimeDebounce'
 * '<S7>'   : 'COMR_MsgRcDiag/COMR_MsgRcDiag/Abm_RC_Diag/DSM_ReportCheck'
 * '<S8>'   : 'COMR_MsgRcDiag/COMR_MsgRcDiag/Abm_RC_Diag/DSM_ReportCheck/Bit Clear1'
 * '<S9>'   : 'COMR_MsgRcDiag/COMR_MsgRcDiag/Abm_RC_Diag/DSM_ReportCheck/Bit Clear2'
 * '<S10>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/Abm_RC_Diag/DSM_ReportCheck/Bit Set'
 * '<S11>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/Abm_RC_Diag/DSM_ReportCheck/Bit Set1'
 * '<S12>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/Abm_RC_Diag/DSM_ReportCheck/Bit Set2'
 * '<S13>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/Abm_RC_Diag/DSM_ReportCheck/Bit Set4'
 * '<S14>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/EnCond/TONV_10msTimeDebounce'
 * '<S15>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/Compare To Constant'
 * '<S16>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/Compare To Constant1'
 * '<S17>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/DocBlock'
 * '<S18>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms'
 * '<S19>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_100ms'
 * '<S20>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_10ms'
 * '<S21>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck'
 * '<S22>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck1'
 * '<S23>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck2'
 * '<S24>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck/Bit Clear1'
 * '<S25>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck/Bit Clear2'
 * '<S26>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck/Bit Set'
 * '<S27>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck/Bit Set1'
 * '<S28>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck/Bit Set2'
 * '<S29>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck/Bit Set4'
 * '<S30>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck1/Bit Clear1'
 * '<S31>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck1/Bit Clear2'
 * '<S32>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck1/Bit Set'
 * '<S33>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck1/Bit Set1'
 * '<S34>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck1/Bit Set2'
 * '<S35>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck1/Bit Set4'
 * '<S36>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck2/Bit Clear1'
 * '<S37>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck2/Bit Clear2'
 * '<S38>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck2/Bit Set'
 * '<S39>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck2/Bit Set1'
 * '<S40>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck2/Bit Set2'
 * '<S41>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/OBC_100ms/DSM_ReportCheck2/Bit Set4'
 * '<S42>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_100ms/DSM_ReportCheck'
 * '<S43>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_100ms/DSM_ReportCheck1'
 * '<S44>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_100ms/DSM_ReportCheck/Bit Clear1'
 * '<S45>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_100ms/DSM_ReportCheck/Bit Clear2'
 * '<S46>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_100ms/DSM_ReportCheck/Bit Set'
 * '<S47>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_100ms/DSM_ReportCheck/Bit Set1'
 * '<S48>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_100ms/DSM_ReportCheck/Bit Set2'
 * '<S49>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_100ms/DSM_ReportCheck/Bit Set4'
 * '<S50>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_100ms/DSM_ReportCheck1/Bit Clear1'
 * '<S51>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_100ms/DSM_ReportCheck1/Bit Clear2'
 * '<S52>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_100ms/DSM_ReportCheck1/Bit Set'
 * '<S53>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_100ms/DSM_ReportCheck1/Bit Set1'
 * '<S54>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_100ms/DSM_ReportCheck1/Bit Set2'
 * '<S55>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_100ms/DSM_ReportCheck1/Bit Set4'
 * '<S56>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_10ms/DSM_ReportCheck'
 * '<S57>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_10ms/DSM_ReportCheck/Bit Clear1'
 * '<S58>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_10ms/DSM_ReportCheck/Bit Clear2'
 * '<S59>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_10ms/DSM_ReportCheck/Bit Set'
 * '<S60>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_10ms/DSM_ReportCheck/Bit Set1'
 * '<S61>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_10ms/DSM_ReportCheck/Bit Set2'
 * '<S62>'  : 'COMR_MsgRcDiag/COMR_MsgRcDiag/VcuObc_RC_Diag/VCU_10ms/DSM_ReportCheck/Bit Set4'
 */
#endif                                 /* RTW_HEADER_COMR_MsgRcDiag_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
