/*
 * File: BSER_BattSocCalc.h
 *
 * Code generated for Simulink model 'BSER_BattSocCalc'.
 *
 * Model version                  : 'M1.5.6'
 * Simulink Coder version         : 8.13 (R2017b) 24-Jul-2017
 * C/C++ source code generated on : Mon Aug 16 10:09:47 2021
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Infineon->TriCore
 * Code generation objectives:
 *    1. MISRA C:2012 guidelines
 *    2. Execution efficiency
 * Validation result: Not run
 */

#ifndef RTW_HEADER_BSER_BattSocCalc_h_
#define RTW_HEADER_BSER_BattSocCalc_h_
#include <math.h>
#include <string.h>
#ifndef BSER_BattSocCalc_COMMON_INCLUDES_
# define BSER_BattSocCalc_COMMON_INCLUDES_
#include "rtwtypes.h"
#endif                                 /* BSER_BattSocCalc_COMMON_INCLUDES_ */

#include "BSER_BattSocCalc_types.h"

/* Includes for objects with custom storage classes. */
#include "SocParameter.h"

/* Macros for accessing real-time model data structure */

/* user code (top of header file) */
#include "ASW_Interface.h"

/* Block signals (auto storage) */
typedef struct {
  real32_T Saturation3;                /* '<S16>/Saturation3' */
  real32_T Saturation;                 /* '<S16>/Saturation' */
  real32_T Saturation1;                /* '<S16>/Saturation1' */
  real32_T Saturation2;                /* '<S16>/Saturation2' */
  real32_T Sum;                        /* '<S62>/Sum' */
  real32_T Sum_c;                      /* '<S63>/Sum' */
  real32_T Sum_i;                      /* '<S64>/Sum' */
  real32_T Switch2;                    /* '<S72>/Switch2' */
  real32_T In1;                        /* '<S61>/In1' */
  boolean_T Initial_Enable;            /* '<S18>/SOC State' */
  boolean_T Ah_Enable;                 /* '<S18>/SOC State' */
  boolean_T Fault_Enable;              /* '<S18>/SOC State' */
  boolean_T RunINI;                    /* '<S18>/SOC State' */
  boolean_T bOcvRevHld;                /* '<S18>/SOC State' */
  boolean_T flag;                      /* '<S35>/Chart' */
  boolean_T Q;                         /* '<S33>/RS' */
} B_BSER_BattSocCalc_T;

/* Block states (auto storage) for system '<Root>' */
typedef struct {
  real32_T conter;                       /* '<S35>/Chart' */
  real32_T Delay_DSTATE;               /* '<S10>/Delay' */
  real32_T Delay4_DSTATE;              /* '<S1>/Delay4' */
  real32_T Delay8_DSTATE;              /* '<S1>/Delay8' */
  real32_T Delay1_DSTATE;              /* '<S1>/Delay1' */
  real32_T Delay2_DSTATE;              /* '<S1>/Delay2' */
  real32_T Delay5_DSTATE;              /* '<S1>/Delay5' */
  real32_T Delay6_DSTATE;              /* '<S1>/Delay6' */
  real32_T Delay7_DSTATE;              /* '<S1>/Delay7' */
  real32_T Delay1_DSTATE_e;            /* '<S17>/Delay1' */
  real32_T Delay1_DSTATE_n;            /* '<S19>/Delay1' */
  real32_T Delay_DSTATE_o;             /* '<S29>/Delay' */
  real32_T Delay_DSTATE_c;             /* '<S36>/Delay' */
  real32_T Delay_DSTATE_i;             /* '<S38>/Delay' */
  real32_T Delay1_DSTATE_i;            /* '<S8>/Delay1' */
  real32_T Delay_DSTATE_g;             /* '<S31>/Delay' */
  real32_T Delay_DSTATE_j;             /* '<S8>/Delay' */
  real32_T Delay_DSTATE_b;             /* '<S56>/Delay' */
  real32_T Delay_DSTATE_od;            /* '<S57>/Delay' */
  real32_T counter;                    /* '<S18>/SOC State' */
  real32_T count;                      /* '<S18>/SOC State' */
  real32_T cnt;                        /* '<S20>/Chart' */
  uint8_T Delay1_DSTATE_ia;            /* '<S41>/Delay1' */
  uint8_T Delay_DSTATE_a;              /* '<S37>/Delay' */
  uint8_T DelayInput1_DSTATE;          /* '<S46>/Delay Input1' */
  boolean_T Delay3_DSTATE;             /* '<S1>/Delay3' */
  boolean_T Delay_DSTATE_e;            /* '<S19>/Delay' */
  boolean_T Delay2_DSTATE_a;           /* '<S19>/Delay2' */
  boolean_T Delay1_DSTATE_g;           /* '<S37>/Delay1' */
  boolean_T Delay2_DSTATE_c;           /* '<S38>/Delay2' */
  boolean_T Delay1_DSTATE_j;           /* '<S36>/Delay1' */
  boolean_T DelayInput1_DSTATE_n;      /* '<S43>/Delay Input1' */
  boolean_T Delay2_DSTATE_l;           /* '<S35>/Delay2' */
  boolean_T UnitDelay_DSTATE;          /* '<S60>/Unit Delay' */
  boolean_T UnitDelay_DSTATE_f;        /* '<S55>/Unit Delay' */
  boolean_T Delay1_DSTATE_d;           /* '<S48>/Delay1' */
  boolean_T Delay1_DSTATE_l;           /* '<S40>/Delay1' */
  boolean_T Delay1_DSTATE_eo;          /* '<S44>/Delay1' */
  uint8_T is_active_c1_BSER_BattSocCalc;/* '<S18>/SOC State' */
  uint8_T is_c1_BSER_BattSocCalc;      /* '<S18>/SOC State' */
  uint8_T is_active_c3_BSER_BattSocCalc;/* '<S35>/Chart' */
  uint8_T is_c3_BSER_BattSocCalc;      /* '<S35>/Chart' */
  uint8_T is_active_c2_BSER_BattSocCalc;/* '<S33>/RS' */
  uint8_T is_active_c4_BSER_BattSocCalc;/* '<S20>/Chart' */
  uint8_T is_c4_BSER_BattSocCalc;      /* '<S20>/Chart' */
  uint8_T is_active_c6_BSER_BattSocCalc;/* '<S41>/Chart' */
  uint8_T is_c6_BSER_BattSocCalc;      /* '<S41>/Chart' */
  uint8_T i;                           /* '<S41>/Chart' */
  uint8_T is_active_c5_BSER_BattSocCalc;/* '<S19>/Chart' */
  uint8_T is_c5_BSER_BattSocCalc;      /* '<S19>/Chart' */
} DW_BSER_BattSocCalc_T;

/* Invariant block signals (auto storage) */
typedef struct {
  const uint8_T DataTypeConversion1;   /* '<S19>/Data Type Conversion1' */
} ConstB_BSER_BattSocCalc_T;

/* External outputs (root outports fed by signals with auto storage) */
typedef struct {
  boolean_T BSER_bSocVldFlg;           /* '<Root>/BSER_bSocVldFlg' */
} ExtY_BSER_BattSocCalc_T;

/* Block signals (auto storage) */
extern B_BSER_BattSocCalc_T BSER_BattSocCalc_B;

/* Block states (auto storage) */
extern DW_BSER_BattSocCalc_T BSER_BattSocCalc_DW;

/* External outputs (root outports fed by signals with auto storage) */
extern ExtY_BSER_BattSocCalc_T BSER_BattSocCalc_Y;
extern const ConstB_BSER_BattSocCalc_T BSER_BattSocCalc_ConstB;/* constant block i/o */

/* Model entry point functions */
extern void BSER_BattSocCalc_initialize(void);
extern void BSER_BattSocCalc_step(void);

/* Exported data declaration */

/* Volatile memory section */
#define ASW1_OEM_START_SEC_DEFAULT_RAM1_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: Volatile */
extern volatile real32_T BSER_cSocDchAhFulRev;/* DchAh Since Full Rev Soc. */
extern volatile real32_T BSER_rSocAvrg;
extern volatile real32_T BSER_rSocMax;
extern volatile real32_T BSER_rSocMin;
extern volatile uint8_T BSER_stSocFulHld;

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM1_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"
#define ASW1_OEM_START_SEC_DEFAULT_RAM1_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/* Declaration for custom storage class: OutputSignal */
extern volatile boolean_T BSER_DispSOCZero_flg;
extern volatile real32_T BSER_LowSocCorLowCellVoltThres2_C;
extern volatile real32_T BSER_LowSocCorLowCellVoltThres3_C;
extern volatile boolean_T BSER_flgSocSave;
extern volatile real32_T BSER_rRSocTableUpLimit_C;
extern volatile real32_T BSER_rSoc;
extern volatile real32_T BSER_rSocDspl;

#define ASW1_OEM_STOP_SEC_DEFAULT_RAM1_CLEARED_UNSPECIFIED
#include "Asw1_OEM_MemMap.h"

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'BSER_BattSocCalc'
 * '<S1>'   : 'BSER_BattSocCalc/BSER_SOC_V201'
 * '<S2>'   : 'BSER_BattSocCalc/BSER_SOC_V201/Compare To Constant'
 * '<S3>'   : 'BSER_BattSocCalc/BSER_SOC_V201/Compare To Constant1'
 * '<S4>'   : 'BSER_BattSocCalc/BSER_SOC_V201/Compare To Constant2'
 * '<S5>'   : 'BSER_BattSocCalc/BSER_SOC_V201/Compare To Constant3'
 * '<S6>'   : 'BSER_BattSocCalc/BSER_SOC_V201/Compare To Constant4'
 * '<S7>'   : 'BSER_BattSocCalc/BSER_SOC_V201/Compare To Constant8'
 * '<S8>'   : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output'
 * '<S9>'   : 'BSER_BattSocCalc/BSER_SOC_V201/CurrFilter'
 * '<S10>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Debounce_COVhit'
 * '<S11>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Limiter'
 * '<S12>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Limiter1'
 * '<S13>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Limiter2'
 * '<S14>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Limiter3'
 * '<S15>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC'
 * '<S16>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Initial'
 * '<S17>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Merge&Batt_SOC'
 * '<S18>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SocStateControl'
 * '<S19>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/BSER_SocFullHldCalc'
 * '<S20>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/BmsStsDel'
 * '<S21>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/Compare To Constant1'
 * '<S22>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/Compare To Constant2'
 * '<S23>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/Compare To Constant3'
 * '<S24>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/Compare To Constant5'
 * '<S25>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/Compare To Constant6'
 * '<S26>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/Compare To Constant7'
 * '<S27>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/Compare To Zero'
 * '<S28>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/DSOC_Filter '
 * '<S29>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/Debounce_COVhit'
 * '<S30>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/DispSOC'
 * '<S31>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/Final_Corrt'
 * '<S32>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/Hold'
 * '<S33>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/RS_FlipFlop'
 * '<S34>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/SOCCorrect'
 * '<S35>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/SocSave'
 * '<S36>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/keep1'
 * '<S37>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/keep6'
 * '<S38>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/BSER_SocFullHldCalc/BSER_SocDchAhFulRevCalc'
 * '<S39>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/BSER_SocFullHldCalc/Chart'
 * '<S40>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/BSER_SocFullHldCalc/EdgeRising'
 * '<S41>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/BSER_SocFullHldCalc/Stable_Calc'
 * '<S42>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/BSER_SocFullHldCalc/BSER_SocDchAhFulRevCalc/BSER_cSocAhSmlCalc'
 * '<S43>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/BSER_SocFullHldCalc/BSER_SocDchAhFulRevCalc/Detect Change'
 * '<S44>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/BSER_SocFullHldCalc/BSER_SocDchAhFulRevCalc/EdgeFalling'
 * '<S45>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/BSER_SocFullHldCalc/Stable_Calc/Chart'
 * '<S46>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/BSER_SocFullHldCalc/Stable_Calc/Detect Change'
 * '<S47>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/BmsStsDel/Chart'
 * '<S48>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/BmsStsDel/EdgeFalling'
 * '<S49>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/DSOC_Filter /Compare To Constant'
 * '<S50>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/Final_Corrt/Compare To Constant'
 * '<S51>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/Final_Corrt/Compare To Constant1'
 * '<S52>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/Final_Corrt/Compare To Constant5'
 * '<S53>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/Final_Corrt/Compare To Zero1'
 * '<S54>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/RS_FlipFlop/RS'
 * '<S55>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/SOCCorrect/EdgeRising2'
 * '<S56>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/SOCCorrect/LowSOCCorrect'
 * '<S57>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/SOCCorrect/LowSOCCorrect1'
 * '<S58>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/SocSave/Chart'
 * '<S59>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/SocSave/Compare To Constant1'
 * '<S60>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/SocSave/EdgeRising2'
 * '<S61>'  : 'BSER_BattSocCalc/BSER_SOC_V201/Correct&Output/SocSave/Triggered Subsystem'
 * '<S62>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/ SOC_Ah_Agv'
 * '<S63>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/ SOC_Ah_Max'
 * '<S64>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/ SOC_Ah_Min'
 * '<S65>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/Display_SOC'
 * '<S66>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/ SOC_Ah_Agv/Protect from Divided by zero'
 * '<S67>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/ SOC_Ah_Agv/Protect from Divided by zero/Compare To Constant'
 * '<S68>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/ SOC_Ah_Max/Protect from Divided by zero'
 * '<S69>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/ SOC_Ah_Max/Protect from Divided by zero/Compare To Constant'
 * '<S70>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/ SOC_Ah_Min/Protect from Divided by zero'
 * '<S71>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/ SOC_Ah_Min/Protect from Divided by zero/Compare To Constant'
 * '<S72>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/Display_SOC/DisSOC'
 * '<S73>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/Display_SOC/DisSOC/Compare To Constant1'
 * '<S74>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/Display_SOC/DisSOC/Dischage'
 * '<S75>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/Display_SOC/DisSOC/Normal'
 * '<S76>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/Display_SOC/DisSOC/Protect from Divided by zero'
 * '<S77>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/Display_SOC/DisSOC/charge'
 * '<S78>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/Display_SOC/DisSOC/Dischage/Faster'
 * '<S79>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/Display_SOC/DisSOC/Dischage/Slower'
 * '<S80>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/Display_SOC/DisSOC/Protect from Divided by zero/Compare To Constant'
 * '<S81>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/Display_SOC/DisSOC/charge/Faster'
 * '<S82>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/Display_SOC/DisSOC/charge/Slower'
 * '<S83>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Ah&DSOC/Display_SOC/DisSOC/charge/Subsystem'
 * '<S84>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Initial/Compare To Constant1'
 * '<S85>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Initial/Compare To Constant8'
 * '<S86>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Initial/LUT_DSOC'
 * '<S87>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Initial/NVM_DSOC'
 * '<S88>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Initial/NVM_Judge'
 * '<S89>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Initial/RunIni'
 * '<S90>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Initial/SOC_LUT'
 * '<S91>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Initial/SOC_NVM'
 * '<S92>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Initial/NVM_Judge/Compare To Constant'
 * '<S93>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Initial/NVM_Judge/Compare To Constant1'
 * '<S94>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Initial/NVM_Judge/Compare To Constant2'
 * '<S95>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Merge&Batt_SOC/DSOC_Fault'
 * '<S96>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Merge&Batt_SOC/DSOC_Normal'
 * '<S97>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Merge&Batt_SOC/Protect from Divided by zero'
 * '<S98>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Merge&Batt_SOC/DSOC_Normal/Compare To Constant'
 * '<S99>'  : 'BSER_BattSocCalc/BSER_SOC_V201/SOC_Merge&Batt_SOC/Protect from Divided by zero/Compare To Constant'
 * '<S100>' : 'BSER_BattSocCalc/BSER_SOC_V201/SocStateControl/SOC State'
 */
#endif                                 /* RTW_HEADER_BSER_BattSocCalc_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
